X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fm32r%2Fcpu.h;h=9f8a0d1fbb9960515dd292bc8ddcf1ffd2157265;hb=5fd104addfddb68844fb8df67be832ee98ad9888;hp=fa475d575030f87f3a52c9c7beb209ad0300e6a1;hpb=96baa820df8126165bd3c4a33c561556b21203af;p=deliverable%2Fbinutils-gdb.git diff --git a/sim/m32r/cpu.h b/sim/m32r/cpu.h index fa475d5750..9f8a0d1fbb 100644 --- a/sim/m32r/cpu.h +++ b/sim/m32r/cpu.h @@ -2,23 +2,22 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. +Copyright 1996-2020 Free Software Foundation, Inc. -This file is part of the GNU Simulators. +This file is part of the GNU simulators. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License along -with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + You should have received a copy of the GNU General Public License along + with this program; if not, see . */ @@ -32,6 +31,12 @@ with this program; if not, write to the Free Software Foundation, Inc., /* Maximum number of instructions that can be executed in parallel. */ #define MAX_PARALLEL_INSNS 1 +/* The size of an "int" needed to hold an instruction word. + This is usually 32 bits, but some architectures needs 64 bits. */ +typedef CGEN_INSN_INT CGEN_INSN_WORD; + +#include "cgen-engine.h" + /* CPU state information. */ typedef struct { /* Hardware elements. */ @@ -50,14 +55,14 @@ typedef struct { #define SET_H_CR(index, x) \ do { \ m32rbf_h_cr_set_handler (current_cpu, (index), (x));\ -} while (0) +;} while (0) /* accumulator */ DI h_accum; #define GET_H_ACCUM() m32rbf_h_accum_get_handler (current_cpu) #define SET_H_ACCUM(x) \ do { \ m32rbf_h_accum_set_handler (current_cpu, (x));\ -} while (0) +;} while (0) /* condition bit */ BI h_cond; #define GET_H_COND() CPU (h_cond) @@ -68,7 +73,7 @@ m32rbf_h_accum_set_handler (current_cpu, (x));\ #define SET_H_PSW(x) \ do { \ m32rbf_h_psw_set_handler (current_cpu, (x));\ -} while (0) +;} while (0) /* backup psw */ UQI h_bpsw; #define GET_H_BPSW() CPU (h_bpsw) @@ -122,45 +127,49 @@ typedef struct { union sem_fields { struct { /* no operands */ int empty; - } fmt_empty; + } sfmt_empty; + struct { /* */ + UINT f_uimm8; + } sfmt_clrpsw; struct { /* */ UINT f_uimm4; } sfmt_trap; struct { /* */ IADDR i_disp24; - unsigned char out_h_gr_14; + unsigned char out_h_gr_SI_14; } sfmt_bl24; struct { /* */ IADDR i_disp8; - unsigned char out_h_gr_14; + unsigned char out_h_gr_SI_14; } sfmt_bl8; struct { /* */ SI* i_dr; UINT f_hi16; - unsigned char out_dr; - } sfmt_seth; - struct { /* */ - SI* i_sr; UINT f_r1; - unsigned char in_sr; - } sfmt_mvtc; - struct { /* */ - SI* i_dr; - UINT f_r2; unsigned char out_dr; - } sfmt_mvfc; + } sfmt_seth; struct { /* */ ADDR i_uimm24; SI* i_dr; + UINT f_r1; unsigned char out_dr; } sfmt_ld24; struct { /* */ SI* i_sr; + UINT f_r2; unsigned char in_sr; - unsigned char out_h_gr_14; + unsigned char out_h_gr_SI_14; } sfmt_jl; + struct { /* */ + SI* i_sr; + INT f_simm16; + UINT f_r2; + UINT f_uimm3; + unsigned char in_sr; + } sfmt_bset; struct { /* */ SI* i_dr; + UINT f_r1; UINT f_uimm5; unsigned char in_dr; unsigned char out_dr; @@ -168,12 +177,15 @@ union sem_fields { struct { /* */ SI* i_dr; INT f_simm8; + UINT f_r1; unsigned char in_dr; unsigned char out_dr; } sfmt_addi; struct { /* */ SI* i_src1; SI* i_src2; + UINT f_r1; + UINT f_r2; unsigned char in_src1; unsigned char in_src2; unsigned char out_src2; @@ -182,12 +194,16 @@ union sem_fields { SI* i_src1; SI* i_src2; INT f_simm16; + UINT f_r1; + UINT f_r2; unsigned char in_src1; unsigned char in_src2; } sfmt_st_d; struct { /* */ SI* i_dr; SI* i_sr; + UINT f_r1; + UINT f_r2; unsigned char in_sr; unsigned char out_dr; unsigned char out_sr; @@ -196,12 +212,16 @@ union sem_fields { IADDR i_disp16; SI* i_src1; SI* i_src2; + UINT f_r1; + UINT f_r2; unsigned char in_src1; unsigned char in_src2; } sfmt_beq; struct { /* */ SI* i_dr; SI* i_sr; + UINT f_r1; + UINT f_r2; UINT f_uimm16; unsigned char in_sr; unsigned char out_dr; @@ -210,12 +230,16 @@ union sem_fields { SI* i_dr; SI* i_sr; INT f_simm16; + UINT f_r1; + UINT f_r2; unsigned char in_sr; unsigned char out_dr; } sfmt_add3; struct { /* */ SI* i_dr; SI* i_sr; + UINT f_r1; + UINT f_r2; unsigned char in_dr; unsigned char in_sr; unsigned char out_dr; @@ -306,7 +330,7 @@ struct scache { f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ - f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \ + f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \ #define EXTRACT_IFMT_AND3_VARS \ UINT f_op1; \ @@ -347,7 +371,7 @@ struct scache { length = 2; \ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ - f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); \ + f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); \ #define EXTRACT_IFMT_ADDV3_VARS \ UINT f_op1; \ @@ -362,7 +386,7 @@ struct scache { f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ - f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \ + f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \ #define EXTRACT_IFMT_BC8_VARS \ UINT f_op1; \ @@ -373,7 +397,7 @@ struct scache { length = 2; \ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ - f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \ + f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \ #define EXTRACT_IFMT_BC24_VARS \ UINT f_op1; \ @@ -384,7 +408,7 @@ struct scache { length = 4; \ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ - f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); \ + f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); \ #define EXTRACT_IFMT_BEQ_VARS \ UINT f_op1; \ @@ -399,7 +423,7 @@ struct scache { f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ - f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \ + f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \ #define EXTRACT_IFMT_BEQZ_VARS \ UINT f_op1; \ @@ -414,7 +438,7 @@ struct scache { f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ - f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \ + f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \ #define EXTRACT_IFMT_CMP_VARS \ UINT f_op1; \ @@ -442,7 +466,7 @@ struct scache { f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ - f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \ + f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \ #define EXTRACT_IFMT_DIV_VARS \ UINT f_op1; \ @@ -457,7 +481,7 @@ struct scache { f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ - f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \ + f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \ #define EXTRACT_IFMT_JL_VARS \ UINT f_op1; \ @@ -496,7 +520,7 @@ struct scache { f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ - f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \ + f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \ #define EXTRACT_IFMT_MVFACHI_VARS \ UINT f_op1; \ @@ -604,7 +628,7 @@ struct scache { f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ - f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \ + f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \ #define EXTRACT_IFMT_TRAP_VARS \ UINT f_op1; \ @@ -619,6 +643,49 @@ struct scache { f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ +#define EXTRACT_IFMT_CLRPSW_VARS \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_uimm8; \ + unsigned int length; +#define EXTRACT_IFMT_CLRPSW_CODE \ + length = 2; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \ + +#define EXTRACT_IFMT_BSET_VARS \ + UINT f_op1; \ + UINT f_bit4; \ + UINT f_uimm3; \ + UINT f_op2; \ + UINT f_r2; \ + INT f_simm16; \ + unsigned int length; +#define EXTRACT_IFMT_BSET_CODE \ + length = 4; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_bit4 = EXTRACT_MSB0_UINT (insn, 32, 4, 1); \ + f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \ + +#define EXTRACT_IFMT_BTST_VARS \ + UINT f_op1; \ + UINT f_bit4; \ + UINT f_uimm3; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_IFMT_BTST_CODE \ + length = 2; \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_bit4 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \ + f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ + /* Collection of various things for the trace handler to use. */ typedef struct trace_record {