X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fm32r%2Fcpu2.h;h=83e03465e472b93314ffbafebff62e3382101dc7;hb=3922b302645fda04da42a5279399578ae2f6206c;hp=10f06fc8bfafa1e00bac93c5e63b415ba0ea5f59;hpb=4744ac1bb0d2f2294c7762577262fdcafb67883b;p=deliverable%2Fbinutils-gdb.git
diff --git a/sim/m32r/cpu2.h b/sim/m32r/cpu2.h
index 10f06fc8bf..83e03465e4 100644
--- a/sim/m32r/cpu2.h
+++ b/sim/m32r/cpu2.h
@@ -2,22 +2,22 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+Copyright 1996-2020 Free Software Foundation, Inc.
This file is part of the GNU simulators.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
-You should have received a copy of the GNU General Public License
-along with this program. If not, see .
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, see .
*/
@@ -31,6 +31,12 @@ along with this program. If not, see .
/* Maximum number of instructions that can be executed in parallel. */
#define MAX_PARALLEL_INSNS 2
+/* The size of an "int" needed to hold an instruction word.
+ This is usually 32 bits, but some architectures needs 64 bits. */
+typedef CGEN_INSN_INT CGEN_INSN_WORD;
+
+#include "cgen-engine.h"
+
/* CPU state information. */
typedef struct {
/* Hardware elements. */
@@ -126,7 +132,7 @@ typedef struct {
union sem_fields {
struct { /* no operands */
int empty;
- } fmt_empty;
+ } sfmt_empty;
struct { /* */
UINT f_uimm8;
} sfmt_clrpsw;
@@ -355,7 +361,7 @@ struct scache {
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
- f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+ f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
#define EXTRACT_IFMT_AND3_VARS \
UINT f_op1; \
@@ -396,7 +402,7 @@ struct scache {
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
- f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); \
+ f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); \
#define EXTRACT_IFMT_ADDV3_VARS \
UINT f_op1; \
@@ -411,7 +417,7 @@ struct scache {
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
- f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+ f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
#define EXTRACT_IFMT_BC8_VARS \
UINT f_op1; \
@@ -422,7 +428,7 @@ struct scache {
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
- f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
+ f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
#define EXTRACT_IFMT_BC24_VARS \
UINT f_op1; \
@@ -433,7 +439,7 @@ struct scache {
length = 4; \
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
- f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
+ f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); \
#define EXTRACT_IFMT_BEQ_VARS \
UINT f_op1; \
@@ -448,7 +454,7 @@ struct scache {
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
- f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
+ f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
#define EXTRACT_IFMT_BEQZ_VARS \
UINT f_op1; \
@@ -463,7 +469,7 @@ struct scache {
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
- f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
+ f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
#define EXTRACT_IFMT_CMP_VARS \
UINT f_op1; \
@@ -491,7 +497,7 @@ struct scache {
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
- f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+ f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
#define EXTRACT_IFMT_CMPZ_VARS \
UINT f_op1; \
@@ -519,7 +525,7 @@ struct scache {
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
- f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+ f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
#define EXTRACT_IFMT_JC_VARS \
UINT f_op1; \
@@ -558,7 +564,7 @@ struct scache {
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
- f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+ f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
#define EXTRACT_IFMT_MACHI_A_VARS \
UINT f_op1; \
@@ -704,7 +710,7 @@ struct scache {
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
- f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+ f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
#define EXTRACT_IFMT_TRAP_VARS \
UINT f_op1; \
@@ -760,7 +766,7 @@ struct scache {
f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
- f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+ f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
#define EXTRACT_IFMT_BTST_VARS \
UINT f_op1; \
@@ -949,24 +955,24 @@ struct parexec {
USI h_memory_SI_src2_idx;
} sfmt_st;
struct { /* e.g. st $src1,@($slo16,$src2) */
- SI h_memory_SI_add__DFLT_src2_slo16;
- USI h_memory_SI_add__DFLT_src2_slo16_idx;
+ SI h_memory_SI_add__SI_src2_slo16;
+ USI h_memory_SI_add__SI_src2_slo16_idx;
} sfmt_st_d;
struct { /* e.g. stb $src1,@$src2 */
QI h_memory_QI_src2;
USI h_memory_QI_src2_idx;
} sfmt_stb;
struct { /* e.g. stb $src1,@($slo16,$src2) */
- QI h_memory_QI_add__DFLT_src2_slo16;
- USI h_memory_QI_add__DFLT_src2_slo16_idx;
+ QI h_memory_QI_add__SI_src2_slo16;
+ USI h_memory_QI_add__SI_src2_slo16_idx;
} sfmt_stb_d;
struct { /* e.g. sth $src1,@$src2 */
HI h_memory_HI_src2;
USI h_memory_HI_src2_idx;
} sfmt_sth;
struct { /* e.g. sth $src1,@($slo16,$src2) */
- HI h_memory_HI_add__DFLT_src2_slo16;
- USI h_memory_HI_add__DFLT_src2_slo16_idx;
+ HI h_memory_HI_add__SI_src2_slo16;
+ USI h_memory_HI_add__SI_src2_slo16_idx;
} sfmt_sth_d;
struct { /* e.g. st $src1,@+$src2 */
SI h_memory_SI_new_src2;
@@ -989,7 +995,7 @@ struct parexec {
USI h_cr_USI_14;
USI h_cr_USI_6;
UQI h_psw_UQI;
- SI pc;
+ USI pc;
} sfmt_trap;
struct { /* e.g. unlock $src1,@$src2 */
BI h_lock_BI;
@@ -1024,8 +1030,8 @@ struct parexec {
USI h_cr_USI_0;
} sfmt_setpsw;
struct { /* e.g. bset $uimm3,@($slo16,$sr) */
- QI h_memory_QI_add__DFLT_sr_slo16;
- USI h_memory_QI_add__DFLT_sr_slo16_idx;
+ QI h_memory_QI_add__SI_sr_slo16;
+ USI h_memory_QI_add__SI_sr_slo16_idx;
} sfmt_bset;
struct { /* e.g. btst $uimm3,$sr */
BI condbit;