X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fm32r%2Fcpux.h;h=3f41bc5af10bad31d7b842f4e12a1e21d7eec361;hb=5fd104addfddb68844fb8df67be832ee98ad9888;hp=c8894dfb82d77231672c5bcde8e5055ac2b1f03b;hpb=eb2346970afecdf18739229ad0d4dbe6aab18723;p=deliverable%2Fbinutils-gdb.git

diff --git a/sim/m32r/cpux.h b/sim/m32r/cpux.h
index c8894dfb82..3f41bc5af1 100644
--- a/sim/m32r/cpux.h
+++ b/sim/m32r/cpux.h
@@ -2,23 +2,22 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+Copyright 1996-2020 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, see <http://www.gnu.org/licenses/>.
 
 */
 
@@ -32,6 +31,12 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 /* Maximum number of instructions that can be executed in parallel.  */
 #define MAX_PARALLEL_INSNS 2
 
+/* The size of an "int" needed to hold an instruction word.
+   This is usually 32 bits, but some architectures needs 64 bits.  */
+typedef CGEN_INSN_INT CGEN_INSN_WORD;
+
+#include "cgen-engine.h"
+
 /* CPU state information.  */
 typedef struct {
   /* Hardware elements.  */
@@ -46,28 +51,36 @@ typedef struct {
 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
   /* control registers */
   USI h_cr[16];
-/* GET_H_CR macro user-written */
-/* SET_H_CR macro user-written */
+#define GET_H_CR(index) m32rxf_h_cr_get_handler (current_cpu, index)
+#define SET_H_CR(index, x) \
+do { \
+m32rxf_h_cr_set_handler (current_cpu, (index), (x));\
+;} while (0)
   /* accumulator */
   DI h_accum;
-/* GET_H_ACCUM macro user-written */
-/* SET_H_ACCUM macro user-written */
-/* start-sanitize-m32rx */
+#define GET_H_ACCUM() m32rxf_h_accum_get_handler (current_cpu)
+#define SET_H_ACCUM(x) \
+do { \
+m32rxf_h_accum_set_handler (current_cpu, (x));\
+;} while (0)
   /* accumulators */
   DI h_accums[2];
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-/* GET_H_ACCUMS macro user-written */
-/* SET_H_ACCUMS macro user-written */
-/* end-sanitize-m32rx */
+#define GET_H_ACCUMS(index) m32rxf_h_accums_get_handler (current_cpu, index)
+#define SET_H_ACCUMS(index, x) \
+do { \
+m32rxf_h_accums_set_handler (current_cpu, (index), (x));\
+;} while (0)
   /* condition bit */
   BI h_cond;
 #define GET_H_COND() CPU (h_cond)
 #define SET_H_COND(x) (CPU (h_cond) = (x))
   /* psw part of psw */
   UQI h_psw;
-/* GET_H_PSW macro user-written */
-/* SET_H_PSW macro user-written */
+#define GET_H_PSW() m32rxf_h_psw_get_handler (current_cpu)
+#define SET_H_PSW(x) \
+do { \
+m32rxf_h_psw_set_handler (current_cpu, (x));\
+;} while (0)
   /* backup psw */
   UQI h_bpsw;
 #define GET_H_BPSW() CPU (h_bpsw)
@@ -114,375 +127,154 @@ typedef struct {
   int empty;
 } MODEL_M32RX_DATA;
 
+/* Instruction argument buffer.  */
+
 union sem_fields {
-    struct { /* empty sformat for unspecified field list */
-      int empty;
-    } fmt_empty;
-    struct { /* e.g. add $dr,$sr */
-      SI * i_dr;
-      SI * i_sr;
-      unsigned char in_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_add;
-    struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
-      INT f_simm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_add3;
-    struct { /* e.g. and3 $dr,$sr,$uimm16 */
-      UINT f_uimm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_and3;
-    struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
-      UINT f_uimm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_or3;
-    struct { /* e.g. addi $dr,$simm8 */
-      INT f_simm8;
-      SI * i_dr;
-      unsigned char in_dr;
-      unsigned char out_dr;
-    } fmt_addi;
-    struct { /* e.g. addv $dr,$sr */
-      SI * i_dr;
-      SI * i_sr;
-      unsigned char in_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_addv;
-    struct { /* e.g. addv3 $dr,$sr,$simm16 */
-      INT f_simm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_addv3;
-    struct { /* e.g. addx $dr,$sr */
-      SI * i_dr;
-      SI * i_sr;
-      unsigned char in_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_addx;
-    struct { /* e.g. cmp $src1,$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_cmp;
-    struct { /* e.g. cmpi $src2,$simm16 */
-      INT f_simm16;
-      SI * i_src2;
-      unsigned char in_src2;
-    } fmt_cmpi;
-    struct { /* e.g. cmpz $src2 */
-      SI * i_src2;
-      unsigned char in_src2;
-    } fmt_cmpz;
-    struct { /* e.g. div $dr,$sr */
-      SI * i_dr;
-      SI * i_sr;
-      unsigned char in_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_div;
-    struct { /* e.g. ld $dr,@$sr */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_ld;
-    struct { /* e.g. ld $dr,@($slo16,$sr) */
-      INT f_simm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_ld_d;
-    struct { /* e.g. ldb $dr,@$sr */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_ldb;
-    struct { /* e.g. ldb $dr,@($slo16,$sr) */
-      INT f_simm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_ldb_d;
-    struct { /* e.g. ldh $dr,@$sr */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_ldh;
-    struct { /* e.g. ldh $dr,@($slo16,$sr) */
-      INT f_simm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_ldh_d;
-    struct { /* e.g. ld $dr,@$sr+ */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-      unsigned char out_sr;
-    } fmt_ld_plus;
-    struct { /* e.g. ld24 $dr,$uimm24 */
-      ADDR i_uimm24;
-      SI * i_dr;
-      unsigned char out_dr;
-    } fmt_ld24;
-    struct { /* e.g. ldi8 $dr,$simm8 */
-      INT f_simm8;
-      SI * i_dr;
-      unsigned char out_dr;
-    } fmt_ldi8;
-    struct { /* e.g. ldi16 $dr,$hash$slo16 */
-      INT f_simm16;
-      SI * i_dr;
-      unsigned char out_dr;
-    } fmt_ldi16;
-    struct { /* e.g. lock $dr,@$sr */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_lock;
-    struct { /* e.g. machi $src1,$src2,$acc */
-      UINT f_acc;
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_machi_a;
-    struct { /* e.g. mulhi $src1,$src2,$acc */
-      UINT f_acc;
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_mulhi_a;
-    struct { /* e.g. mv $dr,$sr */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_mv;
-    struct { /* e.g. mvfachi $dr,$accs */
-      UINT f_accs;
-      SI * i_dr;
-      unsigned char out_dr;
-    } fmt_mvfachi_a;
-    struct { /* e.g. mvfc $dr,$scr */
-      UINT f_r2;
-      SI * i_dr;
-      unsigned char out_dr;
-    } fmt_mvfc;
-    struct { /* e.g. mvtachi $src1,$accs */
-      UINT f_accs;
-      SI * i_src1;
-      unsigned char in_src1;
-    } fmt_mvtachi_a;
-    struct { /* e.g. mvtc $sr,$dcr */
-      UINT f_r1;
-      SI * i_sr;
-      unsigned char in_sr;
-    } fmt_mvtc;
-    struct { /* e.g. nop */
-      int empty;
-    } fmt_nop;
-    struct { /* e.g. rac $accd,$accs,$imm1 */
-      UINT f_accs;
-      SI f_imm1;
-      UINT f_accd;
-    } fmt_rac_dsi;
-    struct { /* e.g. seth $dr,$hash$hi16 */
-      UINT f_hi16;
-      SI * i_dr;
-      unsigned char out_dr;
-    } fmt_seth;
-    struct { /* e.g. sll3 $dr,$sr,$simm16 */
-      INT f_simm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_sll3;
-    struct { /* e.g. slli $dr,$uimm5 */
-      UINT f_uimm5;
-      SI * i_dr;
-      unsigned char in_dr;
-      unsigned char out_dr;
-    } fmt_slli;
-    struct { /* e.g. st $src1,@$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_st;
-    struct { /* e.g. st $src1,@($slo16,$src2) */
-      INT f_simm16;
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_st_d;
-    struct { /* e.g. stb $src1,@$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_stb;
-    struct { /* e.g. stb $src1,@($slo16,$src2) */
-      INT f_simm16;
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_stb_d;
-    struct { /* e.g. sth $src1,@$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_sth;
-    struct { /* e.g. sth $src1,@($slo16,$src2) */
-      INT f_simm16;
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_sth_d;
-    struct { /* e.g. st $src1,@+$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-      unsigned char out_src2;
-    } fmt_st_plus;
-    struct { /* e.g. unlock $src1,@$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_unlock;
-    struct { /* e.g. satb $dr,$sr */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_satb;
-    struct { /* e.g. sat $dr,$sr */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_sat;
-    struct { /* e.g. sadd */
-      int empty;
-    } fmt_sadd;
-    struct { /* e.g. macwu1 $src1,$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_macwu1;
-    struct { /* e.g. msblo $src1,$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_msblo;
-    struct { /* e.g. mulwu1 $src1,$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_mulwu1;
-  /* cti insns, kept separately so addr_cache is in fixed place */
-  struct {
-    union {
-    struct { /* e.g. bc.s $disp8 */
-      IADDR i_disp8;
-    } fmt_bc8;
-    struct { /* e.g. bc.l $disp24 */
-      IADDR i_disp24;
-    } fmt_bc24;
-    struct { /* e.g. beq $src1,$src2,$disp16 */
-      IADDR i_disp16;
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_beq;
-    struct { /* e.g. beqz $src2,$disp16 */
-      IADDR i_disp16;
-      SI * i_src2;
-      unsigned char in_src2;
-    } fmt_beqz;
-    struct { /* e.g. bl.s $disp8 */
-      IADDR i_disp8;
-      unsigned char out_h_gr_14;
-    } fmt_bl8;
-    struct { /* e.g. bl.l $disp24 */
-      IADDR i_disp24;
-      unsigned char out_h_gr_14;
-    } fmt_bl24;
-    struct { /* e.g. bcl.s $disp8 */
-      IADDR i_disp8;
-      unsigned char out_h_gr_14;
-    } fmt_bcl8;
-    struct { /* e.g. bcl.l $disp24 */
-      IADDR i_disp24;
-      unsigned char out_h_gr_14;
-    } fmt_bcl24;
-    struct { /* e.g. bra.s $disp8 */
-      IADDR i_disp8;
-    } fmt_bra8;
-    struct { /* e.g. bra.l $disp24 */
-      IADDR i_disp24;
-    } fmt_bra24;
-    struct { /* e.g. jc $sr */
-      SI * i_sr;
-      unsigned char in_sr;
-    } fmt_jc;
-    struct { /* e.g. jl $sr */
-      SI * i_sr;
-      unsigned char in_sr;
-      unsigned char out_h_gr_14;
-    } fmt_jl;
-    struct { /* e.g. jmp $sr */
-      SI * i_sr;
-      unsigned char in_sr;
-    } fmt_jmp;
-    struct { /* e.g. rte */
-      int empty;
-    } fmt_rte;
-    struct { /* e.g. trap $uimm4 */
-      UINT f_uimm4;
-    } fmt_trap;
-    struct { /* e.g. sc */
-      int empty;
-    } fmt_sc;
-    } fields;
-#if WITH_SCACHE_PBB
-    SEM_PC addr_cache;
-#endif
-  } cti;
+  struct { /* no operands */
+    int empty;
+  } sfmt_empty;
+  struct { /*  */
+    UINT f_uimm8;
+  } sfmt_clrpsw;
+  struct { /*  */
+    UINT f_uimm4;
+  } sfmt_trap;
+  struct { /*  */
+    IADDR i_disp24;
+    unsigned char out_h_gr_SI_14;
+  } sfmt_bl24;
+  struct { /*  */
+    IADDR i_disp8;
+    unsigned char out_h_gr_SI_14;
+  } sfmt_bl8;
+  struct { /*  */
+    SI f_imm1;
+    UINT f_accd;
+    UINT f_accs;
+  } sfmt_rac_dsi;
+  struct { /*  */
+    SI* i_dr;
+    UINT f_hi16;
+    UINT f_r1;
+    unsigned char out_dr;
+  } sfmt_seth;
+  struct { /*  */
+    SI* i_src1;
+    UINT f_accs;
+    UINT f_r1;
+    unsigned char in_src1;
+  } sfmt_mvtachi_a;
+  struct { /*  */
+    SI* i_dr;
+    UINT f_accs;
+    UINT f_r1;
+    unsigned char out_dr;
+  } sfmt_mvfachi_a;
+  struct { /*  */
+    ADDR i_uimm24;
+    SI* i_dr;
+    UINT f_r1;
+    unsigned char out_dr;
+  } sfmt_ld24;
+  struct { /*  */
+    SI* i_sr;
+    UINT f_r2;
+    unsigned char in_sr;
+    unsigned char out_h_gr_SI_14;
+  } sfmt_jl;
+  struct { /*  */
+    SI* i_sr;
+    INT f_simm16;
+    UINT f_r2;
+    UINT f_uimm3;
+    unsigned char in_sr;
+  } sfmt_bset;
+  struct { /*  */
+    SI* i_dr;
+    UINT f_r1;
+    UINT f_uimm5;
+    unsigned char in_dr;
+    unsigned char out_dr;
+  } sfmt_slli;
+  struct { /*  */
+    SI* i_dr;
+    INT f_simm8;
+    UINT f_r1;
+    unsigned char in_dr;
+    unsigned char out_dr;
+  } sfmt_addi;
+  struct { /*  */
+    SI* i_src1;
+    SI* i_src2;
+    UINT f_r1;
+    UINT f_r2;
+    unsigned char in_src1;
+    unsigned char in_src2;
+    unsigned char out_src2;
+  } sfmt_st_plus;
+  struct { /*  */
+    SI* i_src1;
+    SI* i_src2;
+    INT f_simm16;
+    UINT f_r1;
+    UINT f_r2;
+    unsigned char in_src1;
+    unsigned char in_src2;
+  } sfmt_st_d;
+  struct { /*  */
+    SI* i_src1;
+    SI* i_src2;
+    UINT f_acc;
+    UINT f_r1;
+    UINT f_r2;
+    unsigned char in_src1;
+    unsigned char in_src2;
+  } sfmt_machi_a;
+  struct { /*  */
+    SI* i_dr;
+    SI* i_sr;
+    UINT f_r1;
+    UINT f_r2;
+    unsigned char in_sr;
+    unsigned char out_dr;
+    unsigned char out_sr;
+  } sfmt_ld_plus;
+  struct { /*  */
+    IADDR i_disp16;
+    SI* i_src1;
+    SI* i_src2;
+    UINT f_r1;
+    UINT f_r2;
+    unsigned char in_src1;
+    unsigned char in_src2;
+  } sfmt_beq;
+  struct { /*  */
+    SI* i_dr;
+    SI* i_sr;
+    UINT f_r1;
+    UINT f_r2;
+    UINT f_uimm16;
+    unsigned char in_sr;
+    unsigned char out_dr;
+  } sfmt_and3;
+  struct { /*  */
+    SI* i_dr;
+    SI* i_sr;
+    INT f_simm16;
+    UINT f_r1;
+    UINT f_r2;
+    unsigned char in_sr;
+    unsigned char out_dr;
+  } sfmt_add3;
+  struct { /*  */
+    SI* i_dr;
+    SI* i_sr;
+    UINT f_r1;
+    UINT f_r2;
+    unsigned char in_dr;
+    unsigned char in_sr;
+    unsigned char out_dr;
+  } sfmt_add;
 #if WITH_SCACHE_PBB
   /* Writeback handler.  */
   struct {
@@ -504,6 +296,7 @@ union sem_fields {
     int insn_count;
     /* Next pbb to execute.  */
     SCACHE *next;
+    SCACHE *branch_target;
   } chain;
 #endif
 };
@@ -515,6 +308,9 @@ struct argbuf {
   const IDESC *idesc;
   char trace_p;
   char profile_p;
+  /* ??? Temporary hack for skip insns.  */
+  char skip_count;
+  char unused;
   /* cpu specific data follows */
   union sem semantic;
   int written;
@@ -535,13 +331,11 @@ struct scache {
    These define and assign the local vars that contain the insn's fields.  */
 
 #define EXTRACT_IFMT_EMPTY_VARS \
-  /* Instruction fields.  */ \
   unsigned int length;
 #define EXTRACT_IFMT_EMPTY_CODE \
   length = 0; \
 
 #define EXTRACT_IFMT_ADD_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -549,13 +343,12 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_ADD_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_IFMT_ADD3_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -564,14 +357,13 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_ADD3_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
 
 #define EXTRACT_IFMT_AND3_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -580,14 +372,13 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_AND3_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
 
 #define EXTRACT_IFMT_OR3_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -596,26 +387,24 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_OR3_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
 
 #define EXTRACT_IFMT_ADDI_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   INT f_simm8; \
   unsigned int length;
 #define EXTRACT_IFMT_ADDI_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); \
 
 #define EXTRACT_IFMT_ADDV3_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -624,38 +413,35 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_ADDV3_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
 
 #define EXTRACT_IFMT_BC8_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   SI f_disp8; \
   unsigned int length;
 #define EXTRACT_IFMT_BC8_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 
 #define EXTRACT_IFMT_BC24_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   SI f_disp24; \
   unsigned int length;
 #define EXTRACT_IFMT_BC24_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); \
 
 #define EXTRACT_IFMT_BEQ_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -664,14 +450,13 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_BEQ_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
 
 #define EXTRACT_IFMT_BEQZ_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -680,14 +465,13 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_BEQZ_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
 
 #define EXTRACT_IFMT_CMP_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -695,13 +479,12 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_CMP_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_IFMT_CMPI_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -710,14 +493,13 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_CMPI_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
 
 #define EXTRACT_IFMT_CMPZ_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -725,13 +507,12 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_CMPZ_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_IFMT_DIV_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -740,14 +521,13 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_DIV_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
 
 #define EXTRACT_IFMT_JC_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -755,25 +535,23 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_JC_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_IFMT_LD24_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_uimm24; \
   unsigned int length;
 #define EXTRACT_IFMT_LD24_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
 
 #define EXTRACT_IFMT_LDI16_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -782,14 +560,13 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_LDI16_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
 
 #define EXTRACT_IFMT_MACHI_A_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_acc; \
@@ -798,14 +575,13 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_MACHI_A_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_acc = EXTRACT_UINT (insn, 16, 8, 1); \
-  f_op23 = EXTRACT_UINT (insn, 16, 9, 3); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); \
+  f_op23 = EXTRACT_MSB0_UINT (insn, 16, 9, 3); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_IFMT_MVFACHI_A_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -814,14 +590,13 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_MVFACHI_A_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
-  f_op3 = EXTRACT_UINT (insn, 16, 14, 2); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
+  f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
 
 #define EXTRACT_IFMT_MVFC_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -829,13 +604,12 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_MVFC_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_IFMT_MVTACHI_A_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -844,14 +618,13 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_MVTACHI_A_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
-  f_op3 = EXTRACT_UINT (insn, 16, 14, 2); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
+  f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
 
 #define EXTRACT_IFMT_MVTC_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -859,13 +632,12 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_MVTC_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_IFMT_NOP_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -873,13 +645,12 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_NOP_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_IFMT_RAC_DSI_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_accd; \
   UINT f_bits67; \
@@ -890,16 +661,15 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_RAC_DSI_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_accd = EXTRACT_UINT (insn, 16, 4, 2); \
-  f_bits67 = EXTRACT_UINT (insn, 16, 6, 2); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
-  f_bit14 = EXTRACT_UINT (insn, 16, 14, 1); \
-  f_imm1 = ((EXTRACT_UINT (insn, 16, 15, 1)) + (1)); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); \
+  f_bits67 = EXTRACT_MSB0_UINT (insn, 16, 6, 2); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
+  f_bit14 = EXTRACT_MSB0_UINT (insn, 16, 14, 1); \
+  f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); \
 
 #define EXTRACT_IFMT_SETH_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -908,14 +678,13 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_SETH_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
 
 #define EXTRACT_IFMT_SLLI_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_shift_op2; \
@@ -923,13 +692,12 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_SLLI_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \
-  f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
+  f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
 
 #define EXTRACT_IFMT_ST_D_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -938,14 +706,13 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_ST_D_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
 
 #define EXTRACT_IFMT_TRAP_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -953,13 +720,12 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_TRAP_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_IFMT_SATB_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -968,11 +734,54 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_SATB_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_CLRPSW_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_uimm8; \
+  unsigned int length;
+#define EXTRACT_IFMT_CLRPSW_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
+
+#define EXTRACT_IFMT_BSET_VARS \
+  UINT f_op1; \
+  UINT f_bit4; \
+  UINT f_uimm3; \
+  UINT f_op2; \
+  UINT f_r2; \
+  INT f_simm16; \
+  unsigned int length;
+#define EXTRACT_IFMT_BSET_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_bit4 = EXTRACT_MSB0_UINT (insn, 32, 4, 1); \
+  f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_BTST_VARS \
+  UINT f_op1; \
+  UINT f_bit4; \
+  UINT f_uimm3; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_IFMT_BTST_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_bit4 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
+  f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 
 /* Queued output values of an instruction.  */
 
@@ -980,230 +789,253 @@ struct parexec {
   union {
     struct { /* empty sformat for unspecified field list */
       int empty;
-    } fmt_empty;
+    } sfmt_empty;
     struct { /* e.g. add $dr,$sr */
       SI dr;
-    } fmt_add;
+    } sfmt_add;
     struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
       SI dr;
-    } fmt_add3;
+    } sfmt_add3;
     struct { /* e.g. and3 $dr,$sr,$uimm16 */
       SI dr;
-    } fmt_and3;
+    } sfmt_and3;
     struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
       SI dr;
-    } fmt_or3;
+    } sfmt_or3;
     struct { /* e.g. addi $dr,$simm8 */
       SI dr;
-    } fmt_addi;
+    } sfmt_addi;
     struct { /* e.g. addv $dr,$sr */
       BI condbit;
       SI dr;
-    } fmt_addv;
+    } sfmt_addv;
     struct { /* e.g. addv3 $dr,$sr,$simm16 */
       BI condbit;
       SI dr;
-    } fmt_addv3;
+    } sfmt_addv3;
     struct { /* e.g. addx $dr,$sr */
       BI condbit;
       SI dr;
-    } fmt_addx;
+    } sfmt_addx;
     struct { /* e.g. bc.s $disp8 */
       USI pc;
-    } fmt_bc8;
+    } sfmt_bc8;
     struct { /* e.g. bc.l $disp24 */
       USI pc;
-    } fmt_bc24;
+    } sfmt_bc24;
     struct { /* e.g. beq $src1,$src2,$disp16 */
       USI pc;
-    } fmt_beq;
+    } sfmt_beq;
     struct { /* e.g. beqz $src2,$disp16 */
       USI pc;
-    } fmt_beqz;
+    } sfmt_beqz;
     struct { /* e.g. bl.s $disp8 */
-      SI h_gr_14;
+      SI h_gr_SI_14;
       USI pc;
-    } fmt_bl8;
+    } sfmt_bl8;
     struct { /* e.g. bl.l $disp24 */
-      SI h_gr_14;
+      SI h_gr_SI_14;
       USI pc;
-    } fmt_bl24;
+    } sfmt_bl24;
     struct { /* e.g. bcl.s $disp8 */
-      SI h_gr_14;
+      SI h_gr_SI_14;
       USI pc;
-    } fmt_bcl8;
+    } sfmt_bcl8;
     struct { /* e.g. bcl.l $disp24 */
-      SI h_gr_14;
+      SI h_gr_SI_14;
       USI pc;
-    } fmt_bcl24;
+    } sfmt_bcl24;
     struct { /* e.g. bra.s $disp8 */
       USI pc;
-    } fmt_bra8;
+    } sfmt_bra8;
     struct { /* e.g. bra.l $disp24 */
       USI pc;
-    } fmt_bra24;
+    } sfmt_bra24;
     struct { /* e.g. cmp $src1,$src2 */
       BI condbit;
-    } fmt_cmp;
+    } sfmt_cmp;
     struct { /* e.g. cmpi $src2,$simm16 */
       BI condbit;
-    } fmt_cmpi;
+    } sfmt_cmpi;
     struct { /* e.g. cmpz $src2 */
       BI condbit;
-    } fmt_cmpz;
+    } sfmt_cmpz;
     struct { /* e.g. div $dr,$sr */
       SI dr;
-    } fmt_div;
+    } sfmt_div;
     struct { /* e.g. jc $sr */
       USI pc;
-    } fmt_jc;
+    } sfmt_jc;
     struct { /* e.g. jl $sr */
-      SI h_gr_14;
+      SI h_gr_SI_14;
       USI pc;
-    } fmt_jl;
+    } sfmt_jl;
     struct { /* e.g. jmp $sr */
       USI pc;
-    } fmt_jmp;
+    } sfmt_jmp;
     struct { /* e.g. ld $dr,@$sr */
       SI dr;
-    } fmt_ld;
+    } sfmt_ld;
     struct { /* e.g. ld $dr,@($slo16,$sr) */
       SI dr;
-    } fmt_ld_d;
+    } sfmt_ld_d;
     struct { /* e.g. ldb $dr,@$sr */
       SI dr;
-    } fmt_ldb;
+    } sfmt_ldb;
     struct { /* e.g. ldb $dr,@($slo16,$sr) */
       SI dr;
-    } fmt_ldb_d;
+    } sfmt_ldb_d;
     struct { /* e.g. ldh $dr,@$sr */
       SI dr;
-    } fmt_ldh;
+    } sfmt_ldh;
     struct { /* e.g. ldh $dr,@($slo16,$sr) */
       SI dr;
-    } fmt_ldh_d;
+    } sfmt_ldh_d;
     struct { /* e.g. ld $dr,@$sr+ */
       SI dr;
       SI sr;
-    } fmt_ld_plus;
+    } sfmt_ld_plus;
     struct { /* e.g. ld24 $dr,$uimm24 */
       SI dr;
-    } fmt_ld24;
+    } sfmt_ld24;
     struct { /* e.g. ldi8 $dr,$simm8 */
       SI dr;
-    } fmt_ldi8;
+    } sfmt_ldi8;
     struct { /* e.g. ldi16 $dr,$hash$slo16 */
       SI dr;
-    } fmt_ldi16;
+    } sfmt_ldi16;
     struct { /* e.g. lock $dr,@$sr */
       SI dr;
-      BI h_lock_0;
-    } fmt_lock;
+      BI h_lock_BI;
+    } sfmt_lock;
     struct { /* e.g. machi $src1,$src2,$acc */
       DI acc;
-    } fmt_machi_a;
+    } sfmt_machi_a;
     struct { /* e.g. mulhi $src1,$src2,$acc */
       DI acc;
-    } fmt_mulhi_a;
+    } sfmt_mulhi_a;
     struct { /* e.g. mv $dr,$sr */
       SI dr;
-    } fmt_mv;
+    } sfmt_mv;
     struct { /* e.g. mvfachi $dr,$accs */
       SI dr;
-    } fmt_mvfachi_a;
+    } sfmt_mvfachi_a;
     struct { /* e.g. mvfc $dr,$scr */
       SI dr;
-    } fmt_mvfc;
+    } sfmt_mvfc;
     struct { /* e.g. mvtachi $src1,$accs */
       DI accs;
-    } fmt_mvtachi_a;
+    } sfmt_mvtachi_a;
     struct { /* e.g. mvtc $sr,$dcr */
       USI dcr;
-    } fmt_mvtc;
+    } sfmt_mvtc;
     struct { /* e.g. nop */
       int empty;
-    } fmt_nop;
+    } sfmt_nop;
     struct { /* e.g. rac $accd,$accs,$imm1 */
       DI accd;
-    } fmt_rac_dsi;
+    } sfmt_rac_dsi;
     struct { /* e.g. rte */
-      UQI h_bpsw_0;
-      USI h_cr_6;
-      UQI h_psw_0;
+      UQI h_bpsw_UQI;
+      USI h_cr_USI_6;
+      UQI h_psw_UQI;
       USI pc;
-    } fmt_rte;
+    } sfmt_rte;
     struct { /* e.g. seth $dr,$hash$hi16 */
       SI dr;
-    } fmt_seth;
+    } sfmt_seth;
     struct { /* e.g. sll3 $dr,$sr,$simm16 */
       SI dr;
-    } fmt_sll3;
+    } sfmt_sll3;
     struct { /* e.g. slli $dr,$uimm5 */
       SI dr;
-    } fmt_slli;
+    } sfmt_slli;
     struct { /* e.g. st $src1,@$src2 */
-      SI h_memory_src2;
-      USI h_memory_src2_idx;
-    } fmt_st;
+      SI h_memory_SI_src2;
+      USI h_memory_SI_src2_idx;
+    } sfmt_st;
     struct { /* e.g. st $src1,@($slo16,$src2) */
-      SI h_memory_add__VM_src2_slo16;
-      USI h_memory_add__VM_src2_slo16_idx;
-    } fmt_st_d;
+      SI h_memory_SI_add__SI_src2_slo16;
+      USI h_memory_SI_add__SI_src2_slo16_idx;
+    } sfmt_st_d;
     struct { /* e.g. stb $src1,@$src2 */
-      QI h_memory_src2;
-      USI h_memory_src2_idx;
-    } fmt_stb;
+      QI h_memory_QI_src2;
+      USI h_memory_QI_src2_idx;
+    } sfmt_stb;
     struct { /* e.g. stb $src1,@($slo16,$src2) */
-      QI h_memory_add__VM_src2_slo16;
-      USI h_memory_add__VM_src2_slo16_idx;
-    } fmt_stb_d;
+      QI h_memory_QI_add__SI_src2_slo16;
+      USI h_memory_QI_add__SI_src2_slo16_idx;
+    } sfmt_stb_d;
     struct { /* e.g. sth $src1,@$src2 */
-      HI h_memory_src2;
-      USI h_memory_src2_idx;
-    } fmt_sth;
+      HI h_memory_HI_src2;
+      USI h_memory_HI_src2_idx;
+    } sfmt_sth;
     struct { /* e.g. sth $src1,@($slo16,$src2) */
-      HI h_memory_add__VM_src2_slo16;
-      USI h_memory_add__VM_src2_slo16_idx;
-    } fmt_sth_d;
+      HI h_memory_HI_add__SI_src2_slo16;
+      USI h_memory_HI_add__SI_src2_slo16_idx;
+    } sfmt_sth_d;
     struct { /* e.g. st $src1,@+$src2 */
-      SI h_memory_new_src2;
-      USI h_memory_new_src2_idx;
+      SI h_memory_SI_new_src2;
+      USI h_memory_SI_new_src2_idx;
+      SI src2;
+    } sfmt_st_plus;
+    struct { /* e.g. sth $src1,@$src2+ */
+      HI h_memory_HI_new_src2;
+      USI h_memory_HI_new_src2_idx;
       SI src2;
-    } fmt_st_plus;
+    } sfmt_sth_plus;
+    struct { /* e.g. stb $src1,@$src2+ */
+      QI h_memory_QI_new_src2;
+      USI h_memory_QI_new_src2_idx;
+      SI src2;
+    } sfmt_stb_plus;
     struct { /* e.g. trap $uimm4 */
-      UQI h_bbpsw_0;
-      UQI h_bpsw_0;
-      USI h_cr_14;
-      USI h_cr_6;
-      UQI h_psw_0;
-      SI pc;
-    } fmt_trap;
+      UQI h_bbpsw_UQI;
+      UQI h_bpsw_UQI;
+      USI h_cr_USI_14;
+      USI h_cr_USI_6;
+      UQI h_psw_UQI;
+      USI pc;
+    } sfmt_trap;
     struct { /* e.g. unlock $src1,@$src2 */
-      BI h_lock_0;
-      SI h_memory_src2;
-      USI h_memory_src2_idx;
-    } fmt_unlock;
+      BI h_lock_BI;
+      SI h_memory_SI_src2;
+      USI h_memory_SI_src2_idx;
+    } sfmt_unlock;
     struct { /* e.g. satb $dr,$sr */
       SI dr;
-    } fmt_satb;
+    } sfmt_satb;
     struct { /* e.g. sat $dr,$sr */
       SI dr;
-    } fmt_sat;
+    } sfmt_sat;
     struct { /* e.g. sadd */
-      DI h_accums_0;
-    } fmt_sadd;
+      DI h_accums_DI_0;
+    } sfmt_sadd;
     struct { /* e.g. macwu1 $src1,$src2 */
-      DI h_accums_1;
-    } fmt_macwu1;
+      DI h_accums_DI_1;
+    } sfmt_macwu1;
     struct { /* e.g. msblo $src1,$src2 */
       DI accum;
-    } fmt_msblo;
+    } sfmt_msblo;
     struct { /* e.g. mulwu1 $src1,$src2 */
-      DI h_accums_1;
-    } fmt_mulwu1;
+      DI h_accums_DI_1;
+    } sfmt_mulwu1;
     struct { /* e.g. sc */
       int empty;
-    } fmt_sc;
+    } sfmt_sc;
+    struct { /* e.g. clrpsw $uimm8 */
+      USI h_cr_USI_0;
+    } sfmt_clrpsw;
+    struct { /* e.g. setpsw $uimm8 */
+      USI h_cr_USI_0;
+    } sfmt_setpsw;
+    struct { /* e.g. bset $uimm3,@($slo16,$sr) */
+      QI h_memory_QI_add__SI_sr_slo16;
+      USI h_memory_QI_add__SI_sr_slo16_idx;
+    } sfmt_bset;
+    struct { /* e.g. btst $uimm3,$sr */
+      BI condbit;
+    } sfmt_btst;
   } operands;
   /* For conditionally written operands, bitmask of which ones were.  */
   int written;