X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fm32r%2Fdecode.c;h=a80c9901d56be4a8caa59b7a746dc42e0a084d80;hb=2951f6c068f961a2ea1de892fc82cf0229af67da;hp=6f9492607e2d5f29e480e3d562894a67d6af39e3;hpb=fa803dc60f0bf01297674c41d001798e18ade4dc;p=deliverable%2Fbinutils-gdb.git diff --git a/sim/m32r/decode.c b/sim/m32r/decode.c index 6f9492607e..a80c9901d5 100644 --- a/sim/m32r/decode.c +++ b/sim/m32r/decode.c @@ -1,541 +1,2212 @@ -/* Simulator instruction decoder for m32r. +/* Simulator instruction decoder for m32rbf. -This file is machine generated with CGEN. +THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. +Copyright 1996-2020 Free Software Foundation, Inc. -This file is part of the GNU Simulators. +This file is part of the GNU simulators. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License along -with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + You should have received a copy of the GNU General Public License along + with this program; if not, see . */ -#define WANT_CPU -#define WANT_CPU_M32R +#define WANT_CPU m32rbf +#define WANT_CPU_M32RBF #include "sim-main.h" -#include "sim-xcat.h" -#include "cpu-sim.h" -#include "cpu-opc.h" - -/* FIXME: wip, may eventually only want one form so this would then go - away. However, in the mean time, having both keeps a stable version - around while the cache version is being developed. - It may still be useful to allow two versions to exist though. */ -#if WITH_SCACHE -#define EX(fn) XCONCAT3 (m32r,_ex_,fn) -#else -#define EX(fn) 0 -#endif - -#ifdef HAVE_PARALLEL_EXEC -#ifdef __GNUC__ -#define READ(n) 0 -#else -#define READ(n) XCONCAT3 (READ,_,n) -#endif -#endif - -/* FIXME: Need to review choices for the following. */ - -#if WITH_SEM_SWITCH_FULL -#define FULL(fn) 0 -#else -#define FULL(fn) XCONCAT3 (m32r,_sem_,fn) -#endif - -#if WITH_FAST -#if WITH_SEM_SWITCH_FAST -#define FAST(fn) 0 -#else -#define FAST(fn) XCONCAT3 (m32r,_semf_,fn) /* f for fast */ -#endif -#else -#define FAST(fn) 0 -#endif - -/*#define DECODE M32R_DECODE*/ - -/* The decode_illegal case is currently non-static and the generator doesn't - prepend m32r_, so simplify things by handling it here. */ -#define decode_illegal m32r_decode_illegal - -#define ITAB(n) m32r_cgen_insn_table_entries[n] - -static DECODE decode_add = { M32R_INSN_ADD, & ITAB (M32R_INSN_ADD), EX (fmt_0_add), FULL (add), FAST (add) }; -static DECODE decode_add3 = { M32R_INSN_ADD3, & ITAB (M32R_INSN_ADD3), EX (fmt_1_add3), FULL (add3), FAST (add3) }; -static DECODE decode_and = { M32R_INSN_AND, & ITAB (M32R_INSN_AND), EX (fmt_0_add), FULL (and), FAST (and) }; -static DECODE decode_and3 = { M32R_INSN_AND3, & ITAB (M32R_INSN_AND3), EX (fmt_2_and3), FULL (and3), FAST (and3) }; -static DECODE decode_or = { M32R_INSN_OR, & ITAB (M32R_INSN_OR), EX (fmt_0_add), FULL (or), FAST (or) }; -static DECODE decode_or3 = { M32R_INSN_OR3, & ITAB (M32R_INSN_OR3), EX (fmt_3_or3), FULL (or3), FAST (or3) }; -static DECODE decode_xor = { M32R_INSN_XOR, & ITAB (M32R_INSN_XOR), EX (fmt_0_add), FULL (xor), FAST (xor) }; -static DECODE decode_xor3 = { M32R_INSN_XOR3, & ITAB (M32R_INSN_XOR3), EX (fmt_2_and3), FULL (xor3), FAST (xor3) }; -static DECODE decode_addi = { M32R_INSN_ADDI, & ITAB (M32R_INSN_ADDI), EX (fmt_4_addi), FULL (addi), FAST (addi) }; -static DECODE decode_addv = { M32R_INSN_ADDV, & ITAB (M32R_INSN_ADDV), EX (fmt_5_addv), FULL (addv), FAST (addv) }; -static DECODE decode_addv3 = { M32R_INSN_ADDV3, & ITAB (M32R_INSN_ADDV3), EX (fmt_6_addv3), FULL (addv3), FAST (addv3) }; -static DECODE decode_addx = { M32R_INSN_ADDX, & ITAB (M32R_INSN_ADDX), EX (fmt_7_addx), FULL (addx), FAST (addx) }; -static DECODE decode_bc8 = { M32R_INSN_BC8, & ITAB (M32R_INSN_BC8), EX (fmt_8_bc8), FULL (bc8), FAST (bc8) }; -static DECODE decode_bc24 = { M32R_INSN_BC24, & ITAB (M32R_INSN_BC24), EX (fmt_9_bc24), FULL (bc24), FAST (bc24) }; -static DECODE decode_beq = { M32R_INSN_BEQ, & ITAB (M32R_INSN_BEQ), EX (fmt_10_beq), FULL (beq), FAST (beq) }; -static DECODE decode_beqz = { M32R_INSN_BEQZ, & ITAB (M32R_INSN_BEQZ), EX (fmt_11_beqz), FULL (beqz), FAST (beqz) }; -static DECODE decode_bgez = { M32R_INSN_BGEZ, & ITAB (M32R_INSN_BGEZ), EX (fmt_11_beqz), FULL (bgez), FAST (bgez) }; -static DECODE decode_bgtz = { M32R_INSN_BGTZ, & ITAB (M32R_INSN_BGTZ), EX (fmt_11_beqz), FULL (bgtz), FAST (bgtz) }; -static DECODE decode_blez = { M32R_INSN_BLEZ, & ITAB (M32R_INSN_BLEZ), EX (fmt_11_beqz), FULL (blez), FAST (blez) }; -static DECODE decode_bltz = { M32R_INSN_BLTZ, & ITAB (M32R_INSN_BLTZ), EX (fmt_11_beqz), FULL (bltz), FAST (bltz) }; -static DECODE decode_bnez = { M32R_INSN_BNEZ, & ITAB (M32R_INSN_BNEZ), EX (fmt_11_beqz), FULL (bnez), FAST (bnez) }; -static DECODE decode_bl8 = { M32R_INSN_BL8, & ITAB (M32R_INSN_BL8), EX (fmt_12_bl8), FULL (bl8), FAST (bl8) }; -static DECODE decode_bl24 = { M32R_INSN_BL24, & ITAB (M32R_INSN_BL24), EX (fmt_13_bl24), FULL (bl24), FAST (bl24) }; -static DECODE decode_bnc8 = { M32R_INSN_BNC8, & ITAB (M32R_INSN_BNC8), EX (fmt_8_bc8), FULL (bnc8), FAST (bnc8) }; -static DECODE decode_bnc24 = { M32R_INSN_BNC24, & ITAB (M32R_INSN_BNC24), EX (fmt_9_bc24), FULL (bnc24), FAST (bnc24) }; -static DECODE decode_bne = { M32R_INSN_BNE, & ITAB (M32R_INSN_BNE), EX (fmt_10_beq), FULL (bne), FAST (bne) }; -static DECODE decode_bra8 = { M32R_INSN_BRA8, & ITAB (M32R_INSN_BRA8), EX (fmt_14_bra8), FULL (bra8), FAST (bra8) }; -static DECODE decode_bra24 = { M32R_INSN_BRA24, & ITAB (M32R_INSN_BRA24), EX (fmt_15_bra24), FULL (bra24), FAST (bra24) }; -static DECODE decode_cmp = { M32R_INSN_CMP, & ITAB (M32R_INSN_CMP), EX (fmt_16_cmp), FULL (cmp), FAST (cmp) }; -static DECODE decode_cmpi = { M32R_INSN_CMPI, & ITAB (M32R_INSN_CMPI), EX (fmt_17_cmpi), FULL (cmpi), FAST (cmpi) }; -static DECODE decode_cmpu = { M32R_INSN_CMPU, & ITAB (M32R_INSN_CMPU), EX (fmt_16_cmp), FULL (cmpu), FAST (cmpu) }; -static DECODE decode_cmpui = { M32R_INSN_CMPUI, & ITAB (M32R_INSN_CMPUI), EX (fmt_18_cmpui), FULL (cmpui), FAST (cmpui) }; -static DECODE decode_div = { M32R_INSN_DIV, & ITAB (M32R_INSN_DIV), EX (fmt_19_div), FULL (div), FAST (div) }; -static DECODE decode_divu = { M32R_INSN_DIVU, & ITAB (M32R_INSN_DIVU), EX (fmt_19_div), FULL (divu), FAST (divu) }; -static DECODE decode_rem = { M32R_INSN_REM, & ITAB (M32R_INSN_REM), EX (fmt_19_div), FULL (rem), FAST (rem) }; -static DECODE decode_remu = { M32R_INSN_REMU, & ITAB (M32R_INSN_REMU), EX (fmt_19_div), FULL (remu), FAST (remu) }; -static DECODE decode_jl = { M32R_INSN_JL, & ITAB (M32R_INSN_JL), EX (fmt_20_jl), FULL (jl), FAST (jl) }; -static DECODE decode_jmp = { M32R_INSN_JMP, & ITAB (M32R_INSN_JMP), EX (fmt_21_jmp), FULL (jmp), FAST (jmp) }; -static DECODE decode_ld = { M32R_INSN_LD, & ITAB (M32R_INSN_LD), EX (fmt_22_ld), FULL (ld), FAST (ld) }; -static DECODE decode_ld_d = { M32R_INSN_LD_D, & ITAB (M32R_INSN_LD_D), EX (fmt_23_ld_d), FULL (ld_d), FAST (ld_d) }; -static DECODE decode_ldb = { M32R_INSN_LDB, & ITAB (M32R_INSN_LDB), EX (fmt_24_ldb), FULL (ldb), FAST (ldb) }; -static DECODE decode_ldb_d = { M32R_INSN_LDB_D, & ITAB (M32R_INSN_LDB_D), EX (fmt_25_ldb_d), FULL (ldb_d), FAST (ldb_d) }; -static DECODE decode_ldh = { M32R_INSN_LDH, & ITAB (M32R_INSN_LDH), EX (fmt_26_ldh), FULL (ldh), FAST (ldh) }; -static DECODE decode_ldh_d = { M32R_INSN_LDH_D, & ITAB (M32R_INSN_LDH_D), EX (fmt_27_ldh_d), FULL (ldh_d), FAST (ldh_d) }; -static DECODE decode_ldub = { M32R_INSN_LDUB, & ITAB (M32R_INSN_LDUB), EX (fmt_24_ldb), FULL (ldub), FAST (ldub) }; -static DECODE decode_ldub_d = { M32R_INSN_LDUB_D, & ITAB (M32R_INSN_LDUB_D), EX (fmt_25_ldb_d), FULL (ldub_d), FAST (ldub_d) }; -static DECODE decode_lduh = { M32R_INSN_LDUH, & ITAB (M32R_INSN_LDUH), EX (fmt_26_ldh), FULL (lduh), FAST (lduh) }; -static DECODE decode_lduh_d = { M32R_INSN_LDUH_D, & ITAB (M32R_INSN_LDUH_D), EX (fmt_27_ldh_d), FULL (lduh_d), FAST (lduh_d) }; -static DECODE decode_ld_plus = { M32R_INSN_LD_PLUS, & ITAB (M32R_INSN_LD_PLUS), EX (fmt_28_ld_plus), FULL (ld_plus), FAST (ld_plus) }; -static DECODE decode_ld24 = { M32R_INSN_LD24, & ITAB (M32R_INSN_LD24), EX (fmt_29_ld24), FULL (ld24), FAST (ld24) }; -static DECODE decode_ldi8 = { M32R_INSN_LDI8, & ITAB (M32R_INSN_LDI8), EX (fmt_30_ldi8), FULL (ldi8), FAST (ldi8) }; -static DECODE decode_ldi16 = { M32R_INSN_LDI16, & ITAB (M32R_INSN_LDI16), EX (fmt_31_ldi16), FULL (ldi16), FAST (ldi16) }; -static DECODE decode_lock = { M32R_INSN_LOCK, & ITAB (M32R_INSN_LOCK), EX (fmt_32_lock), FULL (lock), FAST (lock) }; -static DECODE decode_machi = { M32R_INSN_MACHI, & ITAB (M32R_INSN_MACHI), EX (fmt_33_machi), FULL (machi), FAST (machi) }; -static DECODE decode_maclo = { M32R_INSN_MACLO, & ITAB (M32R_INSN_MACLO), EX (fmt_33_machi), FULL (maclo), FAST (maclo) }; -static DECODE decode_macwhi = { M32R_INSN_MACWHI, & ITAB (M32R_INSN_MACWHI), EX (fmt_33_machi), FULL (macwhi), FAST (macwhi) }; -static DECODE decode_macwlo = { M32R_INSN_MACWLO, & ITAB (M32R_INSN_MACWLO), EX (fmt_33_machi), FULL (macwlo), FAST (macwlo) }; -static DECODE decode_mul = { M32R_INSN_MUL, & ITAB (M32R_INSN_MUL), EX (fmt_0_add), FULL (mul), FAST (mul) }; -static DECODE decode_mulhi = { M32R_INSN_MULHI, & ITAB (M32R_INSN_MULHI), EX (fmt_34_mulhi), FULL (mulhi), FAST (mulhi) }; -static DECODE decode_mullo = { M32R_INSN_MULLO, & ITAB (M32R_INSN_MULLO), EX (fmt_34_mulhi), FULL (mullo), FAST (mullo) }; -static DECODE decode_mulwhi = { M32R_INSN_MULWHI, & ITAB (M32R_INSN_MULWHI), EX (fmt_34_mulhi), FULL (mulwhi), FAST (mulwhi) }; -static DECODE decode_mulwlo = { M32R_INSN_MULWLO, & ITAB (M32R_INSN_MULWLO), EX (fmt_34_mulhi), FULL (mulwlo), FAST (mulwlo) }; -static DECODE decode_mv = { M32R_INSN_MV, & ITAB (M32R_INSN_MV), EX (fmt_35_mv), FULL (mv), FAST (mv) }; -static DECODE decode_mvfachi = { M32R_INSN_MVFACHI, & ITAB (M32R_INSN_MVFACHI), EX (fmt_36_mvfachi), FULL (mvfachi), FAST (mvfachi) }; -static DECODE decode_mvfaclo = { M32R_INSN_MVFACLO, & ITAB (M32R_INSN_MVFACLO), EX (fmt_36_mvfachi), FULL (mvfaclo), FAST (mvfaclo) }; -static DECODE decode_mvfacmi = { M32R_INSN_MVFACMI, & ITAB (M32R_INSN_MVFACMI), EX (fmt_36_mvfachi), FULL (mvfacmi), FAST (mvfacmi) }; -static DECODE decode_mvfc = { M32R_INSN_MVFC, & ITAB (M32R_INSN_MVFC), EX (fmt_37_mvfc), FULL (mvfc), FAST (mvfc) }; -static DECODE decode_mvtachi = { M32R_INSN_MVTACHI, & ITAB (M32R_INSN_MVTACHI), EX (fmt_38_mvtachi), FULL (mvtachi), FAST (mvtachi) }; -static DECODE decode_mvtaclo = { M32R_INSN_MVTACLO, & ITAB (M32R_INSN_MVTACLO), EX (fmt_38_mvtachi), FULL (mvtaclo), FAST (mvtaclo) }; -static DECODE decode_mvtc = { M32R_INSN_MVTC, & ITAB (M32R_INSN_MVTC), EX (fmt_39_mvtc), FULL (mvtc), FAST (mvtc) }; -static DECODE decode_neg = { M32R_INSN_NEG, & ITAB (M32R_INSN_NEG), EX (fmt_35_mv), FULL (neg), FAST (neg) }; -static DECODE decode_nop = { M32R_INSN_NOP, & ITAB (M32R_INSN_NOP), EX (fmt_40_nop), FULL (nop), FAST (nop) }; -static DECODE decode_not = { M32R_INSN_NOT, & ITAB (M32R_INSN_NOT), EX (fmt_35_mv), FULL (not), FAST (not) }; -static DECODE decode_rac = { M32R_INSN_RAC, & ITAB (M32R_INSN_RAC), EX (fmt_41_rac), FULL (rac), FAST (rac) }; -static DECODE decode_rach = { M32R_INSN_RACH, & ITAB (M32R_INSN_RACH), EX (fmt_41_rac), FULL (rach), FAST (rach) }; -static DECODE decode_rte = { M32R_INSN_RTE, & ITAB (M32R_INSN_RTE), EX (fmt_42_rte), FULL (rte), FAST (rte) }; -static DECODE decode_seth = { M32R_INSN_SETH, & ITAB (M32R_INSN_SETH), EX (fmt_43_seth), FULL (seth), FAST (seth) }; -static DECODE decode_sll = { M32R_INSN_SLL, & ITAB (M32R_INSN_SLL), EX (fmt_0_add), FULL (sll), FAST (sll) }; -static DECODE decode_sll3 = { M32R_INSN_SLL3, & ITAB (M32R_INSN_SLL3), EX (fmt_44_sll3), FULL (sll3), FAST (sll3) }; -static DECODE decode_slli = { M32R_INSN_SLLI, & ITAB (M32R_INSN_SLLI), EX (fmt_45_slli), FULL (slli), FAST (slli) }; -static DECODE decode_sra = { M32R_INSN_SRA, & ITAB (M32R_INSN_SRA), EX (fmt_0_add), FULL (sra), FAST (sra) }; -static DECODE decode_sra3 = { M32R_INSN_SRA3, & ITAB (M32R_INSN_SRA3), EX (fmt_44_sll3), FULL (sra3), FAST (sra3) }; -static DECODE decode_srai = { M32R_INSN_SRAI, & ITAB (M32R_INSN_SRAI), EX (fmt_45_slli), FULL (srai), FAST (srai) }; -static DECODE decode_srl = { M32R_INSN_SRL, & ITAB (M32R_INSN_SRL), EX (fmt_0_add), FULL (srl), FAST (srl) }; -static DECODE decode_srl3 = { M32R_INSN_SRL3, & ITAB (M32R_INSN_SRL3), EX (fmt_44_sll3), FULL (srl3), FAST (srl3) }; -static DECODE decode_srli = { M32R_INSN_SRLI, & ITAB (M32R_INSN_SRLI), EX (fmt_45_slli), FULL (srli), FAST (srli) }; -static DECODE decode_st = { M32R_INSN_ST, & ITAB (M32R_INSN_ST), EX (fmt_46_st), FULL (st), FAST (st) }; -static DECODE decode_st_d = { M32R_INSN_ST_D, & ITAB (M32R_INSN_ST_D), EX (fmt_47_st_d), FULL (st_d), FAST (st_d) }; -static DECODE decode_stb = { M32R_INSN_STB, & ITAB (M32R_INSN_STB), EX (fmt_48_stb), FULL (stb), FAST (stb) }; -static DECODE decode_stb_d = { M32R_INSN_STB_D, & ITAB (M32R_INSN_STB_D), EX (fmt_49_stb_d), FULL (stb_d), FAST (stb_d) }; -static DECODE decode_sth = { M32R_INSN_STH, & ITAB (M32R_INSN_STH), EX (fmt_50_sth), FULL (sth), FAST (sth) }; -static DECODE decode_sth_d = { M32R_INSN_STH_D, & ITAB (M32R_INSN_STH_D), EX (fmt_51_sth_d), FULL (sth_d), FAST (sth_d) }; -static DECODE decode_st_plus = { M32R_INSN_ST_PLUS, & ITAB (M32R_INSN_ST_PLUS), EX (fmt_52_st_plus), FULL (st_plus), FAST (st_plus) }; -static DECODE decode_st_minus = { M32R_INSN_ST_MINUS, & ITAB (M32R_INSN_ST_MINUS), EX (fmt_52_st_plus), FULL (st_minus), FAST (st_minus) }; -static DECODE decode_sub = { M32R_INSN_SUB, & ITAB (M32R_INSN_SUB), EX (fmt_0_add), FULL (sub), FAST (sub) }; -static DECODE decode_subv = { M32R_INSN_SUBV, & ITAB (M32R_INSN_SUBV), EX (fmt_5_addv), FULL (subv), FAST (subv) }; -static DECODE decode_subx = { M32R_INSN_SUBX, & ITAB (M32R_INSN_SUBX), EX (fmt_7_addx), FULL (subx), FAST (subx) }; -static DECODE decode_trap = { M32R_INSN_TRAP, & ITAB (M32R_INSN_TRAP), EX (fmt_53_trap), FULL (trap), FAST (trap) }; -static DECODE decode_unlock = { M32R_INSN_UNLOCK, & ITAB (M32R_INSN_UNLOCK), EX (fmt_54_unlock), FULL (unlock), FAST (unlock) }; - -DECODE m32r_decode_illegal = { - M32R_INSN_ILLEGAL, & ITAB (M32R_INSN_ILLEGAL), - EX (illegal), FULL (illegal), FAST (illegal) +#include "sim-assert.h" + +/* The instruction descriptor array. + This is computed at runtime. Space for it is not malloc'd to save a + teensy bit of cpu in the decoder. Moving it to malloc space is trivial + but won't be done until necessary (we don't currently support the runtime + addition of instructions nor an SMP machine with different cpus). */ +static IDESC m32rbf_insn_data[M32RBF_INSN__MAX]; + +/* Commas between elements are contained in the macros. + Some of these are conditionally compiled out. */ + +static const struct insn_sem m32rbf_insn_sem[] = +{ + { VIRTUAL_INSN_X_INVALID, M32RBF_INSN_X_INVALID, M32RBF_SFMT_EMPTY }, + { VIRTUAL_INSN_X_AFTER, M32RBF_INSN_X_AFTER, M32RBF_SFMT_EMPTY }, + { VIRTUAL_INSN_X_BEFORE, M32RBF_INSN_X_BEFORE, M32RBF_SFMT_EMPTY }, + { VIRTUAL_INSN_X_CTI_CHAIN, M32RBF_INSN_X_CTI_CHAIN, M32RBF_SFMT_EMPTY }, + { VIRTUAL_INSN_X_CHAIN, M32RBF_INSN_X_CHAIN, M32RBF_SFMT_EMPTY }, + { VIRTUAL_INSN_X_BEGIN, M32RBF_INSN_X_BEGIN, M32RBF_SFMT_EMPTY }, + { M32R_INSN_ADD, M32RBF_INSN_ADD, M32RBF_SFMT_ADD }, + { M32R_INSN_ADD3, M32RBF_INSN_ADD3, M32RBF_SFMT_ADD3 }, + { M32R_INSN_AND, M32RBF_INSN_AND, M32RBF_SFMT_ADD }, + { M32R_INSN_AND3, M32RBF_INSN_AND3, M32RBF_SFMT_AND3 }, + { M32R_INSN_OR, M32RBF_INSN_OR, M32RBF_SFMT_ADD }, + { M32R_INSN_OR3, M32RBF_INSN_OR3, M32RBF_SFMT_OR3 }, + { M32R_INSN_XOR, M32RBF_INSN_XOR, M32RBF_SFMT_ADD }, + { M32R_INSN_XOR3, M32RBF_INSN_XOR3, M32RBF_SFMT_AND3 }, + { M32R_INSN_ADDI, M32RBF_INSN_ADDI, M32RBF_SFMT_ADDI }, + { M32R_INSN_ADDV, M32RBF_INSN_ADDV, M32RBF_SFMT_ADDV }, + { M32R_INSN_ADDV3, M32RBF_INSN_ADDV3, M32RBF_SFMT_ADDV3 }, + { M32R_INSN_ADDX, M32RBF_INSN_ADDX, M32RBF_SFMT_ADDX }, + { M32R_INSN_BC8, M32RBF_INSN_BC8, M32RBF_SFMT_BC8 }, + { M32R_INSN_BC24, M32RBF_INSN_BC24, M32RBF_SFMT_BC24 }, + { M32R_INSN_BEQ, M32RBF_INSN_BEQ, M32RBF_SFMT_BEQ }, + { M32R_INSN_BEQZ, M32RBF_INSN_BEQZ, M32RBF_SFMT_BEQZ }, + { M32R_INSN_BGEZ, M32RBF_INSN_BGEZ, M32RBF_SFMT_BEQZ }, + { M32R_INSN_BGTZ, M32RBF_INSN_BGTZ, M32RBF_SFMT_BEQZ }, + { M32R_INSN_BLEZ, M32RBF_INSN_BLEZ, M32RBF_SFMT_BEQZ }, + { M32R_INSN_BLTZ, M32RBF_INSN_BLTZ, M32RBF_SFMT_BEQZ }, + { M32R_INSN_BNEZ, M32RBF_INSN_BNEZ, M32RBF_SFMT_BEQZ }, + { M32R_INSN_BL8, M32RBF_INSN_BL8, M32RBF_SFMT_BL8 }, + { M32R_INSN_BL24, M32RBF_INSN_BL24, M32RBF_SFMT_BL24 }, + { M32R_INSN_BNC8, M32RBF_INSN_BNC8, M32RBF_SFMT_BC8 }, + { M32R_INSN_BNC24, M32RBF_INSN_BNC24, M32RBF_SFMT_BC24 }, + { M32R_INSN_BNE, M32RBF_INSN_BNE, M32RBF_SFMT_BEQ }, + { M32R_INSN_BRA8, M32RBF_INSN_BRA8, M32RBF_SFMT_BRA8 }, + { M32R_INSN_BRA24, M32RBF_INSN_BRA24, M32RBF_SFMT_BRA24 }, + { M32R_INSN_CMP, M32RBF_INSN_CMP, M32RBF_SFMT_CMP }, + { M32R_INSN_CMPI, M32RBF_INSN_CMPI, M32RBF_SFMT_CMPI }, + { M32R_INSN_CMPU, M32RBF_INSN_CMPU, M32RBF_SFMT_CMP }, + { M32R_INSN_CMPUI, M32RBF_INSN_CMPUI, M32RBF_SFMT_CMPI }, + { M32R_INSN_DIV, M32RBF_INSN_DIV, M32RBF_SFMT_DIV }, + { M32R_INSN_DIVU, M32RBF_INSN_DIVU, M32RBF_SFMT_DIV }, + { M32R_INSN_REM, M32RBF_INSN_REM, M32RBF_SFMT_DIV }, + { M32R_INSN_REMU, M32RBF_INSN_REMU, M32RBF_SFMT_DIV }, + { M32R_INSN_JL, M32RBF_INSN_JL, M32RBF_SFMT_JL }, + { M32R_INSN_JMP, M32RBF_INSN_JMP, M32RBF_SFMT_JMP }, + { M32R_INSN_LD, M32RBF_INSN_LD, M32RBF_SFMT_LD }, + { M32R_INSN_LD_D, M32RBF_INSN_LD_D, M32RBF_SFMT_LD_D }, + { M32R_INSN_LDB, M32RBF_INSN_LDB, M32RBF_SFMT_LDB }, + { M32R_INSN_LDB_D, M32RBF_INSN_LDB_D, M32RBF_SFMT_LDB_D }, + { M32R_INSN_LDH, M32RBF_INSN_LDH, M32RBF_SFMT_LDH }, + { M32R_INSN_LDH_D, M32RBF_INSN_LDH_D, M32RBF_SFMT_LDH_D }, + { M32R_INSN_LDUB, M32RBF_INSN_LDUB, M32RBF_SFMT_LDB }, + { M32R_INSN_LDUB_D, M32RBF_INSN_LDUB_D, M32RBF_SFMT_LDB_D }, + { M32R_INSN_LDUH, M32RBF_INSN_LDUH, M32RBF_SFMT_LDH }, + { M32R_INSN_LDUH_D, M32RBF_INSN_LDUH_D, M32RBF_SFMT_LDH_D }, + { M32R_INSN_LD_PLUS, M32RBF_INSN_LD_PLUS, M32RBF_SFMT_LD_PLUS }, + { M32R_INSN_LD24, M32RBF_INSN_LD24, M32RBF_SFMT_LD24 }, + { M32R_INSN_LDI8, M32RBF_INSN_LDI8, M32RBF_SFMT_LDI8 }, + { M32R_INSN_LDI16, M32RBF_INSN_LDI16, M32RBF_SFMT_LDI16 }, + { M32R_INSN_LOCK, M32RBF_INSN_LOCK, M32RBF_SFMT_LOCK }, + { M32R_INSN_MACHI, M32RBF_INSN_MACHI, M32RBF_SFMT_MACHI }, + { M32R_INSN_MACLO, M32RBF_INSN_MACLO, M32RBF_SFMT_MACHI }, + { M32R_INSN_MACWHI, M32RBF_INSN_MACWHI, M32RBF_SFMT_MACHI }, + { M32R_INSN_MACWLO, M32RBF_INSN_MACWLO, M32RBF_SFMT_MACHI }, + { M32R_INSN_MUL, M32RBF_INSN_MUL, M32RBF_SFMT_ADD }, + { M32R_INSN_MULHI, M32RBF_INSN_MULHI, M32RBF_SFMT_MULHI }, + { M32R_INSN_MULLO, M32RBF_INSN_MULLO, M32RBF_SFMT_MULHI }, + { M32R_INSN_MULWHI, M32RBF_INSN_MULWHI, M32RBF_SFMT_MULHI }, + { M32R_INSN_MULWLO, M32RBF_INSN_MULWLO, M32RBF_SFMT_MULHI }, + { M32R_INSN_MV, M32RBF_INSN_MV, M32RBF_SFMT_MV }, + { M32R_INSN_MVFACHI, M32RBF_INSN_MVFACHI, M32RBF_SFMT_MVFACHI }, + { M32R_INSN_MVFACLO, M32RBF_INSN_MVFACLO, M32RBF_SFMT_MVFACHI }, + { M32R_INSN_MVFACMI, M32RBF_INSN_MVFACMI, M32RBF_SFMT_MVFACHI }, + { M32R_INSN_MVFC, M32RBF_INSN_MVFC, M32RBF_SFMT_MVFC }, + { M32R_INSN_MVTACHI, M32RBF_INSN_MVTACHI, M32RBF_SFMT_MVTACHI }, + { M32R_INSN_MVTACLO, M32RBF_INSN_MVTACLO, M32RBF_SFMT_MVTACHI }, + { M32R_INSN_MVTC, M32RBF_INSN_MVTC, M32RBF_SFMT_MVTC }, + { M32R_INSN_NEG, M32RBF_INSN_NEG, M32RBF_SFMT_MV }, + { M32R_INSN_NOP, M32RBF_INSN_NOP, M32RBF_SFMT_NOP }, + { M32R_INSN_NOT, M32RBF_INSN_NOT, M32RBF_SFMT_MV }, + { M32R_INSN_RAC, M32RBF_INSN_RAC, M32RBF_SFMT_RAC }, + { M32R_INSN_RACH, M32RBF_INSN_RACH, M32RBF_SFMT_RAC }, + { M32R_INSN_RTE, M32RBF_INSN_RTE, M32RBF_SFMT_RTE }, + { M32R_INSN_SETH, M32RBF_INSN_SETH, M32RBF_SFMT_SETH }, + { M32R_INSN_SLL, M32RBF_INSN_SLL, M32RBF_SFMT_ADD }, + { M32R_INSN_SLL3, M32RBF_INSN_SLL3, M32RBF_SFMT_SLL3 }, + { M32R_INSN_SLLI, M32RBF_INSN_SLLI, M32RBF_SFMT_SLLI }, + { M32R_INSN_SRA, M32RBF_INSN_SRA, M32RBF_SFMT_ADD }, + { M32R_INSN_SRA3, M32RBF_INSN_SRA3, M32RBF_SFMT_SLL3 }, + { M32R_INSN_SRAI, M32RBF_INSN_SRAI, M32RBF_SFMT_SLLI }, + { M32R_INSN_SRL, M32RBF_INSN_SRL, M32RBF_SFMT_ADD }, + { M32R_INSN_SRL3, M32RBF_INSN_SRL3, M32RBF_SFMT_SLL3 }, + { M32R_INSN_SRLI, M32RBF_INSN_SRLI, M32RBF_SFMT_SLLI }, + { M32R_INSN_ST, M32RBF_INSN_ST, M32RBF_SFMT_ST }, + { M32R_INSN_ST_D, M32RBF_INSN_ST_D, M32RBF_SFMT_ST_D }, + { M32R_INSN_STB, M32RBF_INSN_STB, M32RBF_SFMT_STB }, + { M32R_INSN_STB_D, M32RBF_INSN_STB_D, M32RBF_SFMT_STB_D }, + { M32R_INSN_STH, M32RBF_INSN_STH, M32RBF_SFMT_STH }, + { M32R_INSN_STH_D, M32RBF_INSN_STH_D, M32RBF_SFMT_STH_D }, + { M32R_INSN_ST_PLUS, M32RBF_INSN_ST_PLUS, M32RBF_SFMT_ST_PLUS }, + { M32R_INSN_ST_MINUS, M32RBF_INSN_ST_MINUS, M32RBF_SFMT_ST_PLUS }, + { M32R_INSN_SUB, M32RBF_INSN_SUB, M32RBF_SFMT_ADD }, + { M32R_INSN_SUBV, M32RBF_INSN_SUBV, M32RBF_SFMT_ADDV }, + { M32R_INSN_SUBX, M32RBF_INSN_SUBX, M32RBF_SFMT_ADDX }, + { M32R_INSN_TRAP, M32RBF_INSN_TRAP, M32RBF_SFMT_TRAP }, + { M32R_INSN_UNLOCK, M32RBF_INSN_UNLOCK, M32RBF_SFMT_UNLOCK }, + { M32R_INSN_CLRPSW, M32RBF_INSN_CLRPSW, M32RBF_SFMT_CLRPSW }, + { M32R_INSN_SETPSW, M32RBF_INSN_SETPSW, M32RBF_SFMT_SETPSW }, + { M32R_INSN_BSET, M32RBF_INSN_BSET, M32RBF_SFMT_BSET }, + { M32R_INSN_BCLR, M32RBF_INSN_BCLR, M32RBF_SFMT_BSET }, + { M32R_INSN_BTST, M32RBF_INSN_BTST, M32RBF_SFMT_BTST }, }; -/* The order must match that of `labels' in sem-switch.c/read.c. */ - -DECODE *m32r_decode_vars[] = { - & m32r_decode_illegal, - & decode_add, - & decode_add3, - & decode_and, - & decode_and3, - & decode_or, - & decode_or3, - & decode_xor, - & decode_xor3, - & decode_addi, - & decode_addv, - & decode_addv3, - & decode_addx, - & decode_bc8, - & decode_bc24, - & decode_beq, - & decode_beqz, - & decode_bgez, - & decode_bgtz, - & decode_blez, - & decode_bltz, - & decode_bnez, - & decode_bl8, - & decode_bl24, - & decode_bnc8, - & decode_bnc24, - & decode_bne, - & decode_bra8, - & decode_bra24, - & decode_cmp, - & decode_cmpi, - & decode_cmpu, - & decode_cmpui, - & decode_div, - & decode_divu, - & decode_rem, - & decode_remu, - & decode_jl, - & decode_jmp, - & decode_ld, - & decode_ld_d, - & decode_ldb, - & decode_ldb_d, - & decode_ldh, - & decode_ldh_d, - & decode_ldub, - & decode_ldub_d, - & decode_lduh, - & decode_lduh_d, - & decode_ld_plus, - & decode_ld24, - & decode_ldi8, - & decode_ldi16, - & decode_lock, - & decode_machi, - & decode_maclo, - & decode_macwhi, - & decode_macwlo, - & decode_mul, - & decode_mulhi, - & decode_mullo, - & decode_mulwhi, - & decode_mulwlo, - & decode_mv, - & decode_mvfachi, - & decode_mvfaclo, - & decode_mvfacmi, - & decode_mvfc, - & decode_mvtachi, - & decode_mvtaclo, - & decode_mvtc, - & decode_neg, - & decode_nop, - & decode_not, - & decode_rac, - & decode_rach, - & decode_rte, - & decode_seth, - & decode_sll, - & decode_sll3, - & decode_slli, - & decode_sra, - & decode_sra3, - & decode_srai, - & decode_srl, - & decode_srl3, - & decode_srli, - & decode_st, - & decode_st_d, - & decode_stb, - & decode_stb_d, - & decode_sth, - & decode_sth_d, - & decode_st_plus, - & decode_st_minus, - & decode_sub, - & decode_subv, - & decode_subx, - & decode_trap, - & decode_unlock, - 0 +static const struct insn_sem m32rbf_insn_sem_invalid = +{ + VIRTUAL_INSN_X_INVALID, M32RBF_INSN_X_INVALID, M32RBF_SFMT_EMPTY }; -/* The decoder needs a slightly different computed goto switch control. */ -#ifdef __GNUC__ -#define DECODE_SWITCH(N, X) goto *labels_##N[X]; -#else -#define DECODE_SWITCH(N, X) switch (X) +/* Initialize an IDESC from the compile-time computable parts. */ + +static INLINE void +init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) +{ + const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries; + + id->num = t->index; + id->sfmt = t->sfmt; + if ((int) t->type <= 0) + id->idata = & cgen_virtual_insn_table[- (int) t->type]; + else + id->idata = & insn_table[t->type]; + id->attrs = CGEN_INSN_ATTRS (id->idata); + /* Oh my god, a magic number. */ + id->length = CGEN_INSN_BITSIZE (id->idata) / 8; + +#if WITH_PROFILE_MODEL_P + id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index]; + { + SIM_DESC sd = CPU_STATE (cpu); + SIM_ASSERT (t->index == id->timing->num); + } #endif -/* Given an instruction, return a pointer to its DECODE entry. */ + /* Semantic pointers are initialized elsewhere. */ +} + +/* Initialize the instruction descriptor table. */ + +void +m32rbf_init_idesc_table (SIM_CPU *cpu) +{ + IDESC *id,*tabend; + const struct insn_sem *t,*tend; + int tabsize = M32RBF_INSN__MAX; + IDESC *table = m32rbf_insn_data; + + memset (table, 0, tabsize * sizeof (IDESC)); + + /* First set all entries to the `invalid insn'. */ + t = & m32rbf_insn_sem_invalid; + for (id = table, tabend = table + tabsize; id < tabend; ++id) + init_idesc (cpu, id, t); + + /* Now fill in the values for the chosen cpu. */ + for (t = m32rbf_insn_sem, tend = t + ARRAY_SIZE (m32rbf_insn_sem); + t != tend; ++t) + { + init_idesc (cpu, & table[t->index], t); + } + + /* Link the IDESC table into the cpu. */ + CPU_IDESC (cpu) = table; +} + +/* Given an instruction, return a pointer to its IDESC entry. */ -DECODE * -m32r_decode (current_cpu, pc, insn) - SIM_CPU *current_cpu; - PCADDR pc; - insn_t insn; +const IDESC * +m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, + CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn, + ARGBUF *abuf) { + /* Result of decoder. */ + M32RBF_INSN_TYPE itype; + { -#ifdef __GNUC__ - static void *labels_0[256] = { - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && case_0_28, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && case_0_87, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && case_0_95, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && case_0_112, && case_0_113, && case_0_114, && case_0_115, - && case_0_116, && case_0_117, && case_0_118, && case_0_119, - && case_0_120, && case_0_121, && case_0_122, && case_0_123, - && case_0_124, && case_0_125, && case_0_126, && case_0_127, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && case_0_240, && case_0_241, && case_0_242, && case_0_243, - && case_0_244, && case_0_245, && case_0_246, && case_0_247, - && case_0_248, && case_0_249, && case_0_250, && case_0_251, - && case_0_252, && case_0_253, && case_0_254, && case_0_255, - }; -#endif - static DECODE *insns[256] = { - &decode_subv, &decode_subx, &decode_sub, &decode_neg, - &decode_cmp, &decode_cmpu, &decode_illegal, &decode_illegal, - &decode_addv, &decode_addx, &decode_add, &decode_not, - &decode_and, &decode_xor, &decode_or, &decode_illegal, - &decode_srl, &decode_illegal, &decode_sra, &decode_illegal, - &decode_sll, &decode_illegal, &decode_mul, &decode_illegal, - &decode_mv, &decode_mvfc, &decode_mvtc, &decode_illegal, - 0, &decode_rte, &decode_illegal, &decode_trap, - &decode_stb, &decode_illegal, &decode_sth, &decode_illegal, - &decode_st, &decode_unlock, &decode_st_plus, &decode_st_minus, - &decode_ldb, &decode_ldub, &decode_ldh, &decode_lduh, - &decode_ld, &decode_lock, &decode_ld_plus, &decode_illegal, - &decode_mulhi, &decode_mullo, &decode_mulwhi, &decode_mulwlo, - &decode_machi, &decode_maclo, &decode_macwhi, &decode_macwlo, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_addi, &decode_addi, &decode_addi, &decode_addi, - &decode_addi, &decode_addi, &decode_addi, &decode_addi, - &decode_addi, &decode_addi, &decode_addi, &decode_addi, - &decode_addi, &decode_addi, &decode_addi, &decode_addi, - &decode_srli, &decode_srli, &decode_srai, &decode_srai, - &decode_slli, &decode_slli, &decode_illegal, 0, - &decode_rach, &decode_rac, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, 0, - &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, - &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, - &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, - &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_cmpi, &decode_cmpui, &decode_illegal, &decode_illegal, - &decode_addv3, &decode_illegal, &decode_add3, &decode_illegal, - &decode_and3, &decode_xor3, &decode_or3, &decode_illegal, - &decode_div, &decode_divu, &decode_rem, &decode_remu, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_srl3, &decode_illegal, &decode_sra3, &decode_illegal, - &decode_sll3, &decode_illegal, &decode_illegal, &decode_ldi16, - &decode_stb_d, &decode_illegal, &decode_sth_d, &decode_illegal, - &decode_st_d, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_ldb_d, &decode_ldub_d, &decode_ldh_d, &decode_lduh_d, - &decode_ld_d, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_beq, &decode_bne, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_beqz, &decode_bnez, &decode_bltz, &decode_bgez, - &decode_blez, &decode_bgtz, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_seth, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24, - &decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24, - &decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24, - &decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }; - unsigned int val; - val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0))); - DECODE_SWITCH (0, val) + CGEN_INSN_WORD insn = base_insn; + + { + unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0))); + switch (val) { - CASE (0, 28) : + case 0 : itype = M32RBF_INSN_SUBV; goto extract_sfmt_addv; + case 1 : itype = M32RBF_INSN_SUBX; goto extract_sfmt_addx; + case 2 : itype = M32RBF_INSN_SUB; goto extract_sfmt_add; + case 3 : itype = M32RBF_INSN_NEG; goto extract_sfmt_mv; + case 4 : itype = M32RBF_INSN_CMP; goto extract_sfmt_cmp; + case 5 : itype = M32RBF_INSN_CMPU; goto extract_sfmt_cmp; + case 8 : itype = M32RBF_INSN_ADDV; goto extract_sfmt_addv; + case 9 : itype = M32RBF_INSN_ADDX; goto extract_sfmt_addx; + case 10 : itype = M32RBF_INSN_ADD; goto extract_sfmt_add; + case 11 : itype = M32RBF_INSN_NOT; goto extract_sfmt_mv; + case 12 : itype = M32RBF_INSN_AND; goto extract_sfmt_add; + case 13 : itype = M32RBF_INSN_XOR; goto extract_sfmt_add; + case 14 : itype = M32RBF_INSN_OR; goto extract_sfmt_add; + case 15 : + if ((entire_insn & 0xf8f0) == 0xf0) + { itype = M32RBF_INSN_BTST; goto extract_sfmt_btst; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 16 : itype = M32RBF_INSN_SRL; goto extract_sfmt_add; + case 18 : itype = M32RBF_INSN_SRA; goto extract_sfmt_add; + case 20 : itype = M32RBF_INSN_SLL; goto extract_sfmt_add; + case 22 : itype = M32RBF_INSN_MUL; goto extract_sfmt_add; + case 24 : itype = M32RBF_INSN_MV; goto extract_sfmt_mv; + case 25 : itype = M32RBF_INSN_MVFC; goto extract_sfmt_mvfc; + case 26 : itype = M32RBF_INSN_MVTC; goto extract_sfmt_mvtc; + case 28 : { - static DECODE *insns[16] = { - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_jl, &decode_jmp, - }; - unsigned int val = (((insn >> 8) & (15 << 0))); - return insns[val]; + unsigned int val = (((insn >> 8) & (1 << 0))); + switch (val) + { + case 0 : + if ((entire_insn & 0xfff0) == 0x1ec0) + { itype = M32RBF_INSN_JL; goto extract_sfmt_jl; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 1 : + if ((entire_insn & 0xfff0) == 0x1fc0) + { itype = M32RBF_INSN_JMP; goto extract_sfmt_jmp; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + } } - CASE (0, 87) : + case 29 : + if ((entire_insn & 0xffff) == 0x10d6) + { itype = M32RBF_INSN_RTE; goto extract_sfmt_rte; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 31 : + if ((entire_insn & 0xfff0) == 0x10f0) + { itype = M32RBF_INSN_TRAP; goto extract_sfmt_trap; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 32 : itype = M32RBF_INSN_STB; goto extract_sfmt_stb; + case 34 : itype = M32RBF_INSN_STH; goto extract_sfmt_sth; + case 36 : itype = M32RBF_INSN_ST; goto extract_sfmt_st; + case 37 : itype = M32RBF_INSN_UNLOCK; goto extract_sfmt_unlock; + case 38 : itype = M32RBF_INSN_ST_PLUS; goto extract_sfmt_st_plus; + case 39 : itype = M32RBF_INSN_ST_MINUS; goto extract_sfmt_st_plus; + case 40 : itype = M32RBF_INSN_LDB; goto extract_sfmt_ldb; + case 41 : itype = M32RBF_INSN_LDUB; goto extract_sfmt_ldb; + case 42 : itype = M32RBF_INSN_LDH; goto extract_sfmt_ldh; + case 43 : itype = M32RBF_INSN_LDUH; goto extract_sfmt_ldh; + case 44 : itype = M32RBF_INSN_LD; goto extract_sfmt_ld; + case 45 : itype = M32RBF_INSN_LOCK; goto extract_sfmt_lock; + case 46 : itype = M32RBF_INSN_LD_PLUS; goto extract_sfmt_ld_plus; + case 48 : itype = M32RBF_INSN_MULHI; goto extract_sfmt_mulhi; + case 49 : itype = M32RBF_INSN_MULLO; goto extract_sfmt_mulhi; + case 50 : itype = M32RBF_INSN_MULWHI; goto extract_sfmt_mulhi; + case 51 : itype = M32RBF_INSN_MULWLO; goto extract_sfmt_mulhi; + case 52 : itype = M32RBF_INSN_MACHI; goto extract_sfmt_machi; + case 53 : itype = M32RBF_INSN_MACLO; goto extract_sfmt_machi; + case 54 : itype = M32RBF_INSN_MACWHI; goto extract_sfmt_machi; + case 55 : itype = M32RBF_INSN_MACWLO; goto extract_sfmt_machi; + case 64 : /* fall through */ + case 65 : /* fall through */ + case 66 : /* fall through */ + case 67 : /* fall through */ + case 68 : /* fall through */ + case 69 : /* fall through */ + case 70 : /* fall through */ + case 71 : /* fall through */ + case 72 : /* fall through */ + case 73 : /* fall through */ + case 74 : /* fall through */ + case 75 : /* fall through */ + case 76 : /* fall through */ + case 77 : /* fall through */ + case 78 : /* fall through */ + case 79 : itype = M32RBF_INSN_ADDI; goto extract_sfmt_addi; + case 80 : /* fall through */ + case 81 : itype = M32RBF_INSN_SRLI; goto extract_sfmt_slli; + case 82 : /* fall through */ + case 83 : itype = M32RBF_INSN_SRAI; goto extract_sfmt_slli; + case 84 : /* fall through */ + case 85 : itype = M32RBF_INSN_SLLI; goto extract_sfmt_slli; + case 87 : { - static DECODE *insns[16] = { - &decode_mvtachi, &decode_mvtaclo, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - }; - unsigned int val = (((insn >> 0) & (15 << 0))); - return insns[val]; + unsigned int val = (((insn >> 0) & (1 << 0))); + switch (val) + { + case 0 : + if ((entire_insn & 0xf0ff) == 0x5070) + { itype = M32RBF_INSN_MVTACHI; goto extract_sfmt_mvtachi; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 1 : + if ((entire_insn & 0xf0ff) == 0x5071) + { itype = M32RBF_INSN_MVTACLO; goto extract_sfmt_mvtachi; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + } } - CASE (0, 95) : + case 88 : + if ((entire_insn & 0xffff) == 0x5080) + { itype = M32RBF_INSN_RACH; goto extract_sfmt_rac; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 89 : + if ((entire_insn & 0xffff) == 0x5090) + { itype = M32RBF_INSN_RAC; goto extract_sfmt_rac; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 95 : { - static DECODE *insns[16] = { - &decode_mvfachi, &decode_mvfaclo, &decode_mvfacmi, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - }; - unsigned int val = (((insn >> 0) & (15 << 0))); - return insns[val]; + unsigned int val = (((insn >> 0) & (3 << 0))); + switch (val) + { + case 0 : + if ((entire_insn & 0xf0ff) == 0x50f0) + { itype = M32RBF_INSN_MVFACHI; goto extract_sfmt_mvfachi; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 1 : + if ((entire_insn & 0xf0ff) == 0x50f1) + { itype = M32RBF_INSN_MVFACLO; goto extract_sfmt_mvfachi; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 2 : + if ((entire_insn & 0xf0ff) == 0x50f2) + { itype = M32RBF_INSN_MVFACMI; goto extract_sfmt_mvfachi; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + } } - CASE (0, 112) : + case 96 : /* fall through */ + case 97 : /* fall through */ + case 98 : /* fall through */ + case 99 : /* fall through */ + case 100 : /* fall through */ + case 101 : /* fall through */ + case 102 : /* fall through */ + case 103 : /* fall through */ + case 104 : /* fall through */ + case 105 : /* fall through */ + case 106 : /* fall through */ + case 107 : /* fall through */ + case 108 : /* fall through */ + case 109 : /* fall through */ + case 110 : /* fall through */ + case 111 : itype = M32RBF_INSN_LDI8; goto extract_sfmt_ldi8; + case 112 : { - static DECODE *insns[16] = { - &decode_nop, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_bc8, &decode_bnc8, &decode_bl8, &decode_bra8, - }; unsigned int val = (((insn >> 8) & (15 << 0))); - return insns[val]; + switch (val) + { + case 0 : + if ((entire_insn & 0xffff) == 0x7000) + { itype = M32RBF_INSN_NOP; goto extract_sfmt_nop; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 1 : itype = M32RBF_INSN_SETPSW; goto extract_sfmt_setpsw; + case 2 : itype = M32RBF_INSN_CLRPSW; goto extract_sfmt_clrpsw; + case 12 : itype = M32RBF_INSN_BC8; goto extract_sfmt_bc8; + case 13 : itype = M32RBF_INSN_BNC8; goto extract_sfmt_bc8; + case 14 : itype = M32RBF_INSN_BL8; goto extract_sfmt_bl8; + case 15 : itype = M32RBF_INSN_BRA8; goto extract_sfmt_bra8; + default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + } } - CASE (0, 113) : /* fall through */ - CASE (0, 114) : /* fall through */ - CASE (0, 115) : /* fall through */ - CASE (0, 116) : /* fall through */ - CASE (0, 117) : /* fall through */ - CASE (0, 118) : /* fall through */ - CASE (0, 119) : /* fall through */ - CASE (0, 120) : /* fall through */ - CASE (0, 121) : /* fall through */ - CASE (0, 122) : /* fall through */ - CASE (0, 123) : /* fall through */ - CASE (0, 124) : /* fall through */ - CASE (0, 125) : /* fall through */ - CASE (0, 126) : /* fall through */ - CASE (0, 127) : + case 113 : /* fall through */ + case 114 : /* fall through */ + case 115 : /* fall through */ + case 116 : /* fall through */ + case 117 : /* fall through */ + case 118 : /* fall through */ + case 119 : /* fall through */ + case 120 : /* fall through */ + case 121 : /* fall through */ + case 122 : /* fall through */ + case 123 : /* fall through */ + case 124 : /* fall through */ + case 125 : /* fall through */ + case 126 : /* fall through */ + case 127 : { - static DECODE *insns[16] = { - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_bc8, &decode_bnc8, &decode_bl8, &decode_bra8, - }; unsigned int val = (((insn >> 8) & (15 << 0))); - return insns[val]; + switch (val) + { + case 1 : itype = M32RBF_INSN_SETPSW; goto extract_sfmt_setpsw; + case 2 : itype = M32RBF_INSN_CLRPSW; goto extract_sfmt_clrpsw; + case 12 : itype = M32RBF_INSN_BC8; goto extract_sfmt_bc8; + case 13 : itype = M32RBF_INSN_BNC8; goto extract_sfmt_bc8; + case 14 : itype = M32RBF_INSN_BL8; goto extract_sfmt_bl8; + case 15 : itype = M32RBF_INSN_BRA8; goto extract_sfmt_bra8; + default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + } } - CASE (0, 240) : /* fall through */ - CASE (0, 241) : /* fall through */ - CASE (0, 242) : /* fall through */ - CASE (0, 243) : /* fall through */ - CASE (0, 244) : /* fall through */ - CASE (0, 245) : /* fall through */ - CASE (0, 246) : /* fall through */ - CASE (0, 247) : /* fall through */ - CASE (0, 248) : /* fall through */ - CASE (0, 249) : /* fall through */ - CASE (0, 250) : /* fall through */ - CASE (0, 251) : /* fall through */ - CASE (0, 252) : /* fall through */ - CASE (0, 253) : /* fall through */ - CASE (0, 254) : /* fall through */ - CASE (0, 255) : + case 132 : + if ((entire_insn & 0xfff00000) == 0x80400000) + { itype = M32RBF_INSN_CMPI; goto extract_sfmt_cmpi; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 133 : + if ((entire_insn & 0xfff00000) == 0x80500000) + { itype = M32RBF_INSN_CMPUI; goto extract_sfmt_cmpi; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 136 : itype = M32RBF_INSN_ADDV3; goto extract_sfmt_addv3; + case 138 : itype = M32RBF_INSN_ADD3; goto extract_sfmt_add3; + case 140 : itype = M32RBF_INSN_AND3; goto extract_sfmt_and3; + case 141 : itype = M32RBF_INSN_XOR3; goto extract_sfmt_and3; + case 142 : itype = M32RBF_INSN_OR3; goto extract_sfmt_or3; + case 144 : + if ((entire_insn & 0xf0f0ffff) == 0x90000000) + { itype = M32RBF_INSN_DIV; goto extract_sfmt_div; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 145 : + if ((entire_insn & 0xf0f0ffff) == 0x90100000) + { itype = M32RBF_INSN_DIVU; goto extract_sfmt_div; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 146 : + if ((entire_insn & 0xf0f0ffff) == 0x90200000) + { itype = M32RBF_INSN_REM; goto extract_sfmt_div; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 147 : + if ((entire_insn & 0xf0f0ffff) == 0x90300000) + { itype = M32RBF_INSN_REMU; goto extract_sfmt_div; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 152 : itype = M32RBF_INSN_SRL3; goto extract_sfmt_sll3; + case 154 : itype = M32RBF_INSN_SRA3; goto extract_sfmt_sll3; + case 156 : itype = M32RBF_INSN_SLL3; goto extract_sfmt_sll3; + case 159 : + if ((entire_insn & 0xf0ff0000) == 0x90f00000) + { itype = M32RBF_INSN_LDI16; goto extract_sfmt_ldi16; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 160 : itype = M32RBF_INSN_STB_D; goto extract_sfmt_stb_d; + case 162 : itype = M32RBF_INSN_STH_D; goto extract_sfmt_sth_d; + case 164 : itype = M32RBF_INSN_ST_D; goto extract_sfmt_st_d; + case 166 : + if ((entire_insn & 0xf8f00000) == 0xa0600000) + { itype = M32RBF_INSN_BSET; goto extract_sfmt_bset; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 167 : + if ((entire_insn & 0xf8f00000) == 0xa0700000) + { itype = M32RBF_INSN_BCLR; goto extract_sfmt_bset; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 168 : itype = M32RBF_INSN_LDB_D; goto extract_sfmt_ldb_d; + case 169 : itype = M32RBF_INSN_LDUB_D; goto extract_sfmt_ldb_d; + case 170 : itype = M32RBF_INSN_LDH_D; goto extract_sfmt_ldh_d; + case 171 : itype = M32RBF_INSN_LDUH_D; goto extract_sfmt_ldh_d; + case 172 : itype = M32RBF_INSN_LD_D; goto extract_sfmt_ld_d; + case 176 : itype = M32RBF_INSN_BEQ; goto extract_sfmt_beq; + case 177 : itype = M32RBF_INSN_BNE; goto extract_sfmt_beq; + case 184 : + if ((entire_insn & 0xfff00000) == 0xb0800000) + { itype = M32RBF_INSN_BEQZ; goto extract_sfmt_beqz; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 185 : + if ((entire_insn & 0xfff00000) == 0xb0900000) + { itype = M32RBF_INSN_BNEZ; goto extract_sfmt_beqz; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 186 : + if ((entire_insn & 0xfff00000) == 0xb0a00000) + { itype = M32RBF_INSN_BLTZ; goto extract_sfmt_beqz; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 187 : + if ((entire_insn & 0xfff00000) == 0xb0b00000) + { itype = M32RBF_INSN_BGEZ; goto extract_sfmt_beqz; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 188 : + if ((entire_insn & 0xfff00000) == 0xb0c00000) + { itype = M32RBF_INSN_BLEZ; goto extract_sfmt_beqz; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 189 : + if ((entire_insn & 0xfff00000) == 0xb0d00000) + { itype = M32RBF_INSN_BGTZ; goto extract_sfmt_beqz; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 220 : + if ((entire_insn & 0xf0ff0000) == 0xd0c00000) + { itype = M32RBF_INSN_SETH; goto extract_sfmt_seth; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 224 : /* fall through */ + case 225 : /* fall through */ + case 226 : /* fall through */ + case 227 : /* fall through */ + case 228 : /* fall through */ + case 229 : /* fall through */ + case 230 : /* fall through */ + case 231 : /* fall through */ + case 232 : /* fall through */ + case 233 : /* fall through */ + case 234 : /* fall through */ + case 235 : /* fall through */ + case 236 : /* fall through */ + case 237 : /* fall through */ + case 238 : /* fall through */ + case 239 : itype = M32RBF_INSN_LD24; goto extract_sfmt_ld24; + case 240 : /* fall through */ + case 241 : /* fall through */ + case 242 : /* fall through */ + case 243 : /* fall through */ + case 244 : /* fall through */ + case 245 : /* fall through */ + case 246 : /* fall through */ + case 247 : /* fall through */ + case 248 : /* fall through */ + case 249 : /* fall through */ + case 250 : /* fall through */ + case 251 : /* fall through */ + case 252 : /* fall through */ + case 253 : /* fall through */ + case 254 : /* fall through */ + case 255 : { - static DECODE *insns[16] = { - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_bc24, &decode_bnc24, &decode_bl24, &decode_bra24, - }; - unsigned int val = (((insn >> 8) & (15 << 0))); - return insns[val]; + unsigned int val = (((insn >> 8) & (3 << 0))); + switch (val) + { + case 0 : + if ((entire_insn & 0xff000000) == 0xfc000000) + { itype = M32RBF_INSN_BC24; goto extract_sfmt_bc24; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 1 : + if ((entire_insn & 0xff000000) == 0xfd000000) + { itype = M32RBF_INSN_BNC24; goto extract_sfmt_bc24; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 2 : + if ((entire_insn & 0xff000000) == 0xfe000000) + { itype = M32RBF_INSN_BL24; goto extract_sfmt_bl24; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + case 3 : + if ((entire_insn & 0xff000000) == 0xff000000) + { itype = M32RBF_INSN_BRA24; goto extract_sfmt_bra24; } + itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; + } } - DEFAULT (0) : return insns[val]; + default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; } - ENDSWITCH (0) + } + } + + /* The instruction has been decoded, now extract the fields. */ + + extract_sfmt_empty: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; +#define FLD(f) abuf->fields.sfmt_empty.f + + + /* Record the fields for the semantic handler. */ + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_add: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_dr) = f_r1; + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_add3: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add3.f + UINT f_r1; + UINT f_r2; + INT f_simm16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_simm16) = f_simm16; + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_and3: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_and3.f + UINT f_r1; + UINT f_r2; + UINT f_uimm16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_uimm16) = f_uimm16; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_or3: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_and3.f + UINT f_r1; + UINT f_r2; + UINT f_uimm16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_uimm16) = f_uimm16; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_addi: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_addi.f + UINT f_r1; + INT f_simm8; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_simm8) = f_simm8; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_r1 0x%x", 'x', f_r1, "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_dr) = f_r1; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_addv: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_dr) = f_r1; + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_addv3: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add3.f + UINT f_r1; + UINT f_r2; + INT f_simm16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_simm16) = f_simm16; + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_addx: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_dr) = f_r1; + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_bc8: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_bl8.f + SI f_disp8; + + f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); + + /* Record the fields for the semantic handler. */ + FLD (i_disp8) = f_disp8; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_bc24: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_bl24.f + SI f_disp24; + + f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); + + /* Record the fields for the semantic handler. */ + FLD (i_disp24) = f_disp24; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_beq: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_beq.f + UINT f_r1; + UINT f_r2; + SI f_disp16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_disp16) = f_disp16; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; } + + extract_sfmt_beqz: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_beq.f + UINT f_r2; + SI f_disp16; + + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (i_disp16) = f_disp16; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_bl8: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_bl8.f + SI f_disp8; + + f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); + + /* Record the fields for the semantic handler. */ + FLD (i_disp8) = f_disp8; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_h_gr_SI_14) = 14; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_bl24: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_bl24.f + SI f_disp24; + + f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); + + /* Record the fields for the semantic handler. */ + FLD (i_disp24) = f_disp24; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_h_gr_SI_14) = 14; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_bra8: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_bl8.f + SI f_disp8; + + f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); + + /* Record the fields for the semantic handler. */ + FLD (i_disp8) = f_disp8; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_bra24: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_bl24.f + SI f_disp24; + + f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); + + /* Record the fields for the semantic handler. */ + FLD (i_disp24) = f_disp24; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cmp: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_cmpi: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_d.f + UINT f_r2; + INT f_simm16; + + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_simm16) = f_simm16; + FLD (f_r2) = f_r2; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_div: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_dr) = f_r1; + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_jl: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_jl.f + UINT f_r2; + + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_h_gr_SI_14) = 14; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_jmp: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_jl.f + UINT f_r2; + + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ld: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ld_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ld_d: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add3.f + UINT f_r1; + UINT f_r2; + INT f_simm16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_simm16) = f_simm16; + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldb: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ld_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldb_d: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add3.f + UINT f_r1; + UINT f_r2; + INT f_simm16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_simm16) = f_simm16; + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldh: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ld_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldh_d: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add3.f + UINT f_r1; + UINT f_r2; + INT f_simm16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_simm16) = f_simm16; + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ld_plus: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ld_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + FLD (out_sr) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ld24: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ld24.f + UINT f_r1; + UINT f_uimm24; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (i_uimm24) = f_uimm24; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "f_r1 0x%x", 'x', f_r1, "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldi8: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_addi.f + UINT f_r1; + INT f_simm8; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); + + /* Record the fields for the semantic handler. */ + FLD (f_simm8) = f_simm8; + FLD (f_r1) = f_r1; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldi16: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add3.f + UINT f_r1; + INT f_simm16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_simm16) = f_simm16; + FLD (f_r1) = f_r1; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_lock: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ld_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_machi: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mulhi: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mv: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ld_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mvfachi: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_seth.f + UINT f_r1; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi", "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mvfc: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ld_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mvtachi: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi", "f_r1 0x%x", 'x', f_r1, "src1 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_mvtc: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ld_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_nop: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; +#define FLD(f) abuf->fields.sfmt_empty.f + + + /* Record the fields for the semantic handler. */ + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_rac: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; +#define FLD(f) abuf->fields.sfmt_empty.f + + + /* Record the fields for the semantic handler. */ + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac", (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_rte: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; +#define FLD(f) abuf->fields.sfmt_empty.f + + + /* Record the fields for the semantic handler. */ + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_seth: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_seth.f + UINT f_r1; + UINT f_hi16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_hi16) = f_hi16; + FLD (f_r1) = f_r1; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_sll3: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add3.f + UINT f_r1; + UINT f_r2; + INT f_simm16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_simm16) = f_simm16; + FLD (f_r2) = f_r2; + FLD (f_r1) = f_r1; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_slli: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_slli.f + UINT f_r1; + UINT f_uimm5; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_uimm5) = f_uimm5; + FLD (i_dr) = & CPU (h_gr)[f_r1]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_r1 0x%x", 'x', f_r1, "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_dr) = f_r1; + FLD (out_dr) = f_r1; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_st: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_st_d: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_d.f + UINT f_r1; + UINT f_r2; + INT f_simm16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_simm16) = f_simm16; + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stb: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stb_d: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_d.f + UINT f_r1; + UINT f_r2; + INT f_simm16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_simm16) = f_simm16; + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_sth: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_sth_d: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_d.f + UINT f_r1; + UINT f_r2; + INT f_simm16; + + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_simm16) = f_simm16; + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_st_plus: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + FLD (out_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_trap: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_trap.f + UINT f_uimm4; + + f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_uimm4) = f_uimm4; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_unlock: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; + + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (f_r2) = f_r2; + FLD (i_src1) = & CPU (h_gr)[f_r1]; + FLD (i_src2) = & CPU (h_gr)[f_r2]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_clrpsw: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_clrpsw.f + UINT f_uimm8; + + f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); + + /* Record the fields for the semantic handler. */ + FLD (f_uimm8) = f_uimm8; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_setpsw: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_clrpsw.f + UINT f_uimm8; + + f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); + + /* Record the fields for the semantic handler. */ + FLD (f_uimm8) = f_uimm8; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_bset: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_bset.f + UINT f_uimm3; + UINT f_r2; + INT f_simm16; + + f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_simm16) = f_simm16; + FLD (f_r2) = f_r2; + FLD (f_uimm3) = f_uimm3; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bset", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_btst: + { + const IDESC *idesc = &m32rbf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_bset.f + UINT f_uimm3; + UINT f_r2; + + f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_uimm3) = f_uimm3; + FLD (i_sr) = & CPU (h_gr)[f_r2]; + CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst", "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_sr) = f_r2; + } +#endif +#undef FLD + return idesc; + } + }