X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fm32r%2Fm32r.c;h=06e8ba275a4282646371ef455dfc65253fc6c9cc;hb=00923338dec84505addaf9cdeca2e9c844757824;hp=3e5e4aaf7a8aed511fd59caca7fd5c68ed03717f;hpb=7a292a7adf506b866905b06b3024c0fd411c4583;p=deliverable%2Fbinutils-gdb.git diff --git a/sim/m32r/m32r.c b/sim/m32r/m32r.c index 3e5e4aaf7a..06e8ba275a 100644 --- a/sim/m32r/m32r.c +++ b/sim/m32r/m32r.c @@ -1,22 +1,21 @@ /* m32r simulator support code - Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. + Copyright (C) 1996-2015 Free Software Foundation, Inc. Contributed by Cygnus Support. -This file is part of GDB, the GNU debugger. + This file is part of GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. -You should have received a copy of the GNU General Public License along -with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ #define WANT_CPU m32rbf #define WANT_CPU_M32RBF @@ -39,6 +38,7 @@ m32r_decode_gdb_ctrl_regnum (int gdb_regnum) case BPC_REGNUM : return H_CR_BPC; case BBPSW_REGNUM : return H_CR_BBPSW; case BBPC_REGNUM : return H_CR_BBPC; + case EVB_REGNUM : return H_CR_CR5; } abort (); } @@ -48,10 +48,8 @@ m32r_decode_gdb_ctrl_regnum (int gdb_regnum) int m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len) { - int mach = MACH_NUM (CPU_MACH (current_cpu)); - if (rn < 16) - SETTWI (buf, a_m32r_h_gr_get (current_cpu, rn)); + SETTWI (buf, m32rbf_h_gr_get (current_cpu, rn)); else switch (rn) { @@ -62,26 +60,17 @@ m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len case BPC_REGNUM : case BBPSW_REGNUM : case BBPC_REGNUM : - SETTWI (buf, a_m32r_h_cr_get (current_cpu, + SETTWI (buf, m32rbf_h_cr_get (current_cpu, m32r_decode_gdb_ctrl_regnum (rn))); break; case PC_REGNUM : - if (mach == MACH_M32R) - SETTWI (buf, m32rbf_h_pc_get (current_cpu)); - else - SETTWI (buf, m32rxf_h_pc_get (current_cpu)); + SETTWI (buf, m32rbf_h_pc_get (current_cpu)); break; case ACCL_REGNUM : - if (mach == MACH_M32R) - SETTWI (buf, GETLODI (m32rbf_h_accum_get (current_cpu))); - else - SETTWI (buf, GETLODI (m32rxf_h_accum_get (current_cpu))); + SETTWI (buf, GETLODI (m32rbf_h_accum_get (current_cpu))); break; case ACCH_REGNUM : - if (mach == MACH_M32R) - SETTWI (buf, GETHIDI (m32rbf_h_accum_get (current_cpu))); - else - SETTWI (buf, GETHIDI (m32rxf_h_accum_get (current_cpu))); + SETTWI (buf, GETHIDI (m32rbf_h_accum_get (current_cpu))); break; default : return 0; @@ -95,10 +84,8 @@ m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len int m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len) { - int mach = MACH_NUM (CPU_MACH (current_cpu)); - if (rn < 16) - a_m32r_h_gr_set (current_cpu, rn, GETTWI (buf)); + m32rbf_h_gr_set (current_cpu, rn, GETTWI (buf)); else switch (rn) { @@ -109,42 +96,25 @@ m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len case BPC_REGNUM : case BBPSW_REGNUM : case BBPC_REGNUM : - a_m32r_h_cr_set (current_cpu, + m32rbf_h_cr_set (current_cpu, m32r_decode_gdb_ctrl_regnum (rn), GETTWI (buf)); break; case PC_REGNUM : - if (mach == MACH_M32R) - m32rbf_h_pc_set (current_cpu, GETTWI (buf)); - else - m32rxf_h_pc_set (current_cpu, GETTWI (buf)); + m32rbf_h_pc_set (current_cpu, GETTWI (buf)); break; case ACCL_REGNUM : { - DI val; - if (mach == MACH_M32R) - val = m32rbf_h_accum_get (current_cpu); - else - val = m32rxf_h_accum_get (current_cpu); + DI val = m32rbf_h_accum_get (current_cpu); SETLODI (val, GETTWI (buf)); - if (mach == MACH_M32R) - m32rbf_h_accum_set (current_cpu, val); - else - m32rxf_h_accum_set (current_cpu, val); + m32rbf_h_accum_set (current_cpu, val); break; } case ACCH_REGNUM : { - DI val; - if (mach == MACH_M32R) - val = m32rbf_h_accum_get (current_cpu); - else - val = m32rxf_h_accum_get (current_cpu); + DI val = m32rbf_h_accum_get (current_cpu); SETHIDI (val, GETTWI (buf)); - if (mach == MACH_M32R) - m32rbf_h_accum_set (current_cpu, val); - else - m32rxf_h_accum_set (current_cpu, val); + m32rbf_h_accum_set (current_cpu, val); break; } default : @@ -154,84 +124,6 @@ m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len return -1; /*FIXME*/ } -/* Cover fns for mach independent register accesses. */ - -SI -a_m32r_h_gr_get (SIM_CPU *current_cpu, UINT regno) -{ - switch (MACH_NUM (CPU_MACH (current_cpu))) - { -#ifdef HAVE_CPU_M32RBF - case MACH_M32R : - return m32rbf_h_gr_get (current_cpu, regno); -#endif -#ifdef HAVE_CPU_M32RXF - case MACH_M32RX : - return m32rxf_h_gr_get (current_cpu, regno); -#endif - default : - abort (); - } -} - -void -a_m32r_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval) -{ - switch (MACH_NUM (CPU_MACH (current_cpu))) - { -#ifdef HAVE_CPU_M32RBF - case MACH_M32R : - m32rbf_h_gr_set (current_cpu, regno, newval); - break; -#endif -#ifdef HAVE_CPU_M32RXF - case MACH_M32RX : - m32rxf_h_gr_set (current_cpu, regno, newval); - break; -#endif - default : - abort (); - } -} - -USI -a_m32r_h_cr_get (SIM_CPU *current_cpu, UINT regno) -{ - switch (MACH_NUM (CPU_MACH (current_cpu))) - { -#ifdef HAVE_CPU_M32RBF - case MACH_M32R : - return m32rbf_h_cr_get (current_cpu, regno); -#endif -#ifdef HAVE_CPU_M32RXF - case MACH_M32RX : - return m32rxf_h_cr_get (current_cpu, regno); -#endif - default : - abort (); - } -} - -void -a_m32r_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval) -{ - switch (MACH_NUM (CPU_MACH (current_cpu))) - { -#ifdef HAVE_CPU_M32RBF - case MACH_M32R : - m32rbf_h_cr_set (current_cpu, regno, newval); - break; -#endif -#ifdef HAVE_CPU_M32RXF - case MACH_M32RX : - m32rxf_h_cr_set (current_cpu, regno, newval); - break; -#endif - default : - abort (); - } -} - USI m32rbf_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr) {