X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fm32r%2Fmodel.c;h=b77eef24c5c3db74a3630b4417ffb774f69c9061;hb=60db1b8565060f4bd2287b060ea9724c93289982;hp=2e20191c20bf3225272eb3649ae3e7fa53ca49a0;hpb=4744ac1bb0d2f2294c7762577262fdcafb67883b;p=deliverable%2Fbinutils-gdb.git
diff --git a/sim/m32r/model.c b/sim/m32r/model.c
index 2e20191c20..b77eef24c5 100644
--- a/sim/m32r/model.c
+++ b/sim/m32r/model.c
@@ -2,22 +2,22 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+Copyright 1996-2020 Free Software Foundation, Inc.
This file is part of the GNU simulators.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
-You should have received a copy of the GNU General Public License
-along with this program. If not, see .
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, see .
*/
@@ -1643,7 +1643,7 @@ model_m32r_d_neg (SIM_CPU *current_cpu, void *sem_arg)
static int
model_m32r_d_nop (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1685,7 +1685,7 @@ model_m32r_d_not (SIM_CPU *current_cpu, void *sem_arg)
static int
model_m32r_d_rac (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1703,7 +1703,7 @@ model_m32r_d_rac (SIM_CPU *current_cpu, void *sem_arg)
static int
model_m32r_d_rach (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1721,7 +1721,7 @@ model_m32r_d_rach (SIM_CPU *current_cpu, void *sem_arg)
static int
model_m32r_d_rte (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3519,7 +3519,7 @@ model_test_neg (SIM_CPU *current_cpu, void *sem_arg)
static int
model_test_nop (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3551,7 +3551,7 @@ model_test_not (SIM_CPU *current_cpu, void *sem_arg)
static int
model_test_rac (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3567,7 +3567,7 @@ model_test_rac (SIM_CPU *current_cpu, void *sem_arg)
static int
model_test_rach (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3583,7 +3583,7 @@ model_test_rach (SIM_CPU *current_cpu, void *sem_arg)
static int
model_test_rte (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -4297,7 +4297,7 @@ test_model_init (SIM_CPU *cpu)
#define TIMING_DATA(td) 0
#endif
-static const MODEL m32r_models[] =
+static const SIM_MODEL m32r_models[] =
{
{ "m32r/d", & m32r_mach, MODEL_M32R_D, TIMING_DATA (& m32r_d_timing[0]), m32r_d_model_init },
{ "test", & m32r_mach, MODEL_TEST, TIMING_DATA (& test_timing[0]), test_model_init },
@@ -4306,7 +4306,7 @@ static const MODEL m32r_models[] =
/* The properties of this cpu's implementation. */
-static const MACH_IMP_PROPERTIES m32rbf_imp_properties =
+static const SIM_MACH_IMP_PROPERTIES m32rbf_imp_properties =
{
sizeof (SIM_CPU),
#if WITH_SCACHE
@@ -4348,7 +4348,7 @@ m32r_init_cpu (SIM_CPU *cpu)
#endif
}
-const MACH m32r_mach =
+const SIM_MACH m32r_mach =
{
"m32r", "m32r", MACH_M32R,
32, 32, & m32r_models[0], & m32rbf_imp_properties,