X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fm32r%2Fmodelx.c;h=a17493ddb8b9a8b2e0f6bb00960480e0dc17cbcf;hb=1e92785005ce880a5fac9d022f05cdcff91c3091;hp=7ff4ad16041255a899f266270a1164bfb853f148;hpb=eb2346970afecdf18739229ad0d4dbe6aab18723;p=deliverable%2Fbinutils-gdb.git

diff --git a/sim/m32r/modelx.c b/sim/m32r/modelx.c
index 7ff4ad1604..a17493ddb8 100644
--- a/sim/m32r/modelx.c
+++ b/sim/m32r/modelx.c
@@ -2,23 +2,22 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+Copyright 1996-2020 Free Software Foundation, Inc.
 
-This file is part of the GNU Simulators.
+This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, see <http://www.gnu.org/licenses/>.
 
 */
 
@@ -37,7 +36,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 static int
 model_m32rx_add (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -62,7 +61,7 @@ model_m32rx_add (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_add3 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add3.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -85,7 +84,7 @@ model_m32rx_add3 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_and (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -110,7 +109,7 @@ model_m32rx_and (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_and3 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_and3.f
+#define FLD(f) abuf->fields.sfmt_and3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -133,7 +132,7 @@ model_m32rx_and3 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_or (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -158,7 +157,7 @@ model_m32rx_or (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_or3 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_or3.f
+#define FLD(f) abuf->fields.sfmt_and3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -181,7 +180,7 @@ model_m32rx_or3 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_xor (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -206,7 +205,7 @@ model_m32rx_xor (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_xor3 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_and3.f
+#define FLD(f) abuf->fields.sfmt_and3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -229,7 +228,7 @@ model_m32rx_xor3 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_addi (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_addi.f
+#define FLD(f) abuf->fields.sfmt_addi.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -252,7 +251,7 @@ model_m32rx_addi (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_addv (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_addv.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -277,7 +276,7 @@ model_m32rx_addv (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_addv3 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_addv3.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -300,7 +299,7 @@ model_m32rx_addv3 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_addx (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_addx.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -325,7 +324,7 @@ model_m32rx_addx (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_bc8 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
+#define FLD(f) abuf->fields.sfmt_bl8.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -343,7 +342,7 @@ model_m32rx_bc8 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_bc24 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
+#define FLD(f) abuf->fields.sfmt_bl24.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -361,7 +360,7 @@ model_m32rx_bc24 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_beq (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -390,7 +389,7 @@ model_m32rx_beq (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_beqz (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -417,7 +416,7 @@ model_m32rx_beqz (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_bgez (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -444,7 +443,7 @@ model_m32rx_bgez (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_bgtz (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -471,7 +470,7 @@ model_m32rx_bgtz (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_blez (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -498,7 +497,7 @@ model_m32rx_blez (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_bltz (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -525,7 +524,7 @@ model_m32rx_bltz (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_bnez (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -552,7 +551,7 @@ model_m32rx_bnez (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_bl8 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
+#define FLD(f) abuf->fields.sfmt_bl8.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -570,7 +569,7 @@ model_m32rx_bl8 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_bl24 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
+#define FLD(f) abuf->fields.sfmt_bl24.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -588,7 +587,7 @@ model_m32rx_bl24 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_bcl8 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
+#define FLD(f) abuf->fields.sfmt_bl8.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -606,7 +605,7 @@ model_m32rx_bcl8 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_bcl24 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bcl24.f
+#define FLD(f) abuf->fields.sfmt_bl24.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -624,7 +623,7 @@ model_m32rx_bcl24 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
+#define FLD(f) abuf->fields.sfmt_bl8.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -642,7 +641,7 @@ model_m32rx_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
+#define FLD(f) abuf->fields.sfmt_bl24.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -660,7 +659,7 @@ model_m32rx_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_bne (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -689,7 +688,7 @@ model_m32rx_bne (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_bra8 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
+#define FLD(f) abuf->fields.sfmt_bl8.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -707,7 +706,7 @@ model_m32rx_bra8 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_bra24 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
+#define FLD(f) abuf->fields.sfmt_bl24.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -725,7 +724,7 @@ model_m32rx_bra24 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_bncl8 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
+#define FLD(f) abuf->fields.sfmt_bl8.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -743,7 +742,7 @@ model_m32rx_bncl8 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_bncl24 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bcl24.f
+#define FLD(f) abuf->fields.sfmt_bl24.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -761,7 +760,7 @@ model_m32rx_bncl24 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_cmp (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_cmp.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -783,7 +782,7 @@ model_m32rx_cmp (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_cmpi (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_cmpi.f
+#define FLD(f) abuf->fields.sfmt_st_d.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -803,7 +802,7 @@ model_m32rx_cmpi (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_cmpu (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_cmp.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -825,7 +824,7 @@ model_m32rx_cmpu (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_cmpui (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_cmpi.f
+#define FLD(f) abuf->fields.sfmt_st_d.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -845,7 +844,7 @@ model_m32rx_cmpui (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_cmpeq (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_cmp.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -867,7 +866,7 @@ model_m32rx_cmpeq (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_cmpz (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_cmpz.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -887,7 +886,7 @@ model_m32rx_cmpz (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_div (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_div.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -912,7 +911,7 @@ model_m32rx_div (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_divu (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_div.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -937,7 +936,7 @@ model_m32rx_divu (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_rem (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_div.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -962,7 +961,7 @@ model_m32rx_rem (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_remu (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_div.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -987,7 +986,7 @@ model_m32rx_remu (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_divh (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_div.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1012,7 +1011,7 @@ model_m32rx_divh (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_jc (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_jc.f
+#define FLD(f) abuf->fields.sfmt_jl.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1032,7 +1031,7 @@ model_m32rx_jc (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_jnc (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_jc.f
+#define FLD(f) abuf->fields.sfmt_jl.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1052,7 +1051,7 @@ model_m32rx_jnc (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_jl (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_jl.f
+#define FLD(f) abuf->fields.sfmt_jl.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1072,7 +1071,7 @@ model_m32rx_jl (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_jmp (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
+#define FLD(f) abuf->fields.sfmt_jl.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1092,7 +1091,7 @@ model_m32rx_jmp (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_ld (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ld.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1114,7 +1113,7 @@ model_m32rx_ld (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_ld_d (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ld_d.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1136,7 +1135,7 @@ model_m32rx_ld_d (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_ldb (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldb.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1158,7 +1157,7 @@ model_m32rx_ldb (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldb_d.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1180,7 +1179,7 @@ model_m32rx_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_ldh (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldh.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1202,7 +1201,7 @@ model_m32rx_ldh (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldh_d.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1224,7 +1223,7 @@ model_m32rx_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_ldub (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldb.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1246,7 +1245,7 @@ model_m32rx_ldub (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldb_d.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1268,7 +1267,7 @@ model_m32rx_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_lduh (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldh.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1290,7 +1289,7 @@ model_m32rx_lduh (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldh_d.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1312,7 +1311,7 @@ model_m32rx_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ld_plus.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1346,7 +1345,7 @@ model_m32rx_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_ld24 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ld24.f
+#define FLD(f) abuf->fields.sfmt_ld24.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1367,7 +1366,7 @@ model_m32rx_ld24 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldi8.f
+#define FLD(f) abuf->fields.sfmt_addi.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1388,7 +1387,7 @@ model_m32rx_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldi16.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1409,7 +1408,7 @@ model_m32rx_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_lock (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_lock.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1431,7 +1430,7 @@ model_m32rx_lock (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_machi_a (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_machi_a.f
+#define FLD(f) abuf->fields.sfmt_machi_a.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1453,7 +1452,7 @@ model_m32rx_machi_a (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_maclo_a (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_machi_a.f
+#define FLD(f) abuf->fields.sfmt_machi_a.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1475,7 +1474,7 @@ model_m32rx_maclo_a (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_macwhi_a (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_machi_a.f
+#define FLD(f) abuf->fields.sfmt_machi_a.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1497,7 +1496,7 @@ model_m32rx_macwhi_a (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_macwlo_a (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_machi_a.f
+#define FLD(f) abuf->fields.sfmt_machi_a.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1519,7 +1518,7 @@ model_m32rx_macwlo_a (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_mul (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1544,7 +1543,7 @@ model_m32rx_mul (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_mulhi_a (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mulhi_a.f
+#define FLD(f) abuf->fields.sfmt_machi_a.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1566,7 +1565,7 @@ model_m32rx_mulhi_a (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_mullo_a (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mulhi_a.f
+#define FLD(f) abuf->fields.sfmt_machi_a.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1588,7 +1587,7 @@ model_m32rx_mullo_a (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_mulwhi_a (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mulhi_a.f
+#define FLD(f) abuf->fields.sfmt_machi_a.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1610,7 +1609,7 @@ model_m32rx_mulwhi_a (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_mulwlo_a (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mulhi_a.f
+#define FLD(f) abuf->fields.sfmt_machi_a.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1632,7 +1631,7 @@ model_m32rx_mulwlo_a (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_mv (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mv.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1655,7 +1654,7 @@ model_m32rx_mv (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_mvfachi_a (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvfachi_a.f
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1676,7 +1675,7 @@ model_m32rx_mvfachi_a (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_mvfaclo_a (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvfachi_a.f
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1697,7 +1696,7 @@ model_m32rx_mvfaclo_a (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_mvfacmi_a (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvfachi_a.f
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1718,7 +1717,7 @@ model_m32rx_mvfacmi_a (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_mvfc (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvfc.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1739,7 +1738,7 @@ model_m32rx_mvfc (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_mvtachi_a (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvtachi_a.f
+#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1759,7 +1758,7 @@ model_m32rx_mvtachi_a (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_mvtaclo_a (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvtachi_a.f
+#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1779,7 +1778,7 @@ model_m32rx_mvtaclo_a (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_mvtc (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvtc.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1800,7 +1799,7 @@ model_m32rx_mvtc (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_neg (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mv.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1823,7 +1822,7 @@ model_m32rx_neg (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_nop (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_nop.f
+#define FLD(f) abuf->fields.sfmt_empty.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1842,7 +1841,7 @@ model_m32rx_nop (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_not (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mv.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1865,7 +1864,7 @@ model_m32rx_not (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_rac_dsi (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_rac_dsi.f
+#define FLD(f) abuf->fields.sfmt_rac_dsi.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1883,7 +1882,7 @@ model_m32rx_rac_dsi (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_rach_dsi (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_rac_dsi.f
+#define FLD(f) abuf->fields.sfmt_rac_dsi.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1901,7 +1900,7 @@ model_m32rx_rach_dsi (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_rte (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_rte.f
+#define FLD(f) abuf->fields.sfmt_empty.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1920,7 +1919,7 @@ model_m32rx_rte (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_seth (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_seth.f
+#define FLD(f) abuf->fields.sfmt_seth.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1941,7 +1940,7 @@ model_m32rx_seth (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_sll (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1966,7 +1965,7 @@ model_m32rx_sll (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_sll3 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_sll3.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1989,7 +1988,7 @@ model_m32rx_sll3 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_slli (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_slli.f
+#define FLD(f) abuf->fields.sfmt_slli.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2012,7 +2011,7 @@ model_m32rx_slli (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_sra (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2037,7 +2036,7 @@ model_m32rx_sra (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_sra3 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_sll3.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2060,7 +2059,7 @@ model_m32rx_sra3 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_srai (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_slli.f
+#define FLD(f) abuf->fields.sfmt_slli.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2083,7 +2082,7 @@ model_m32rx_srai (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_srl (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2108,7 +2107,7 @@ model_m32rx_srl (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_srl3 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_sll3.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2131,7 +2130,7 @@ model_m32rx_srl3 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_srli (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_slli.f
+#define FLD(f) abuf->fields.sfmt_slli.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2154,7 +2153,7 @@ model_m32rx_srli (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_st (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_st.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2176,7 +2175,7 @@ model_m32rx_st (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_st_d (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_st_d.f
+#define FLD(f) abuf->fields.sfmt_st_d.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2198,7 +2197,7 @@ model_m32rx_st_d (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_stb (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_stb.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2220,7 +2219,7 @@ model_m32rx_stb (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_stb_d (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_stb_d.f
+#define FLD(f) abuf->fields.sfmt_st_d.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2242,7 +2241,7 @@ model_m32rx_stb_d (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_sth (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_sth.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2264,7 +2263,7 @@ model_m32rx_sth (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_sth_d (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_sth_d.f
+#define FLD(f) abuf->fields.sfmt_st_d.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2286,7 +2285,71 @@ model_m32rx_sth_d (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_st_plus (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_st_plus.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = 0;
+    INT in_src2 = 0;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_dr = FLD (in_src2);
+    out_dr = FLD (out_src2);
+    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_sth_plus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = 0;
+    INT in_src2 = 0;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_dr = FLD (in_src2);
+    out_dr = FLD (out_src2);
+    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_stb_plus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2318,7 +2381,7 @@ model_m32rx_st_plus (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_st_minus (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_st_plus.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2350,7 +2413,7 @@ model_m32rx_st_minus (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_sub (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2375,7 +2438,7 @@ model_m32rx_sub (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_subv (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_addv.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2400,7 +2463,7 @@ model_m32rx_subv (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_subx (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_addx.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2425,7 +2488,7 @@ model_m32rx_subx (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_trap (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_trap.f
+#define FLD(f) abuf->fields.sfmt_trap.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2444,7 +2507,7 @@ model_m32rx_trap (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_unlock (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_unlock.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2462,7 +2525,7 @@ model_m32rx_unlock (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_satb (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_satb.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2485,7 +2548,7 @@ model_m32rx_satb (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_sath (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_satb.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2508,7 +2571,7 @@ model_m32rx_sath (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_sat (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_sat.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2531,7 +2594,7 @@ model_m32rx_sat (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_pcmpbz (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_cmpz.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2551,7 +2614,7 @@ model_m32rx_pcmpbz (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_sadd (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_sadd.f
+#define FLD(f) abuf->fields.sfmt_empty.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2569,7 +2632,7 @@ model_m32rx_sadd (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_macwu1 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_macwu1.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2591,7 +2654,7 @@ model_m32rx_macwu1 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_msblo (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_msblo.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2613,7 +2676,7 @@ model_m32rx_msblo (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_mulwu1 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mulwu1.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2635,7 +2698,7 @@ model_m32rx_mulwu1 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_maclh1 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_macwu1.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2657,7 +2720,7 @@ model_m32rx_maclh1 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_sc (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_sc.f
+#define FLD(f) abuf->fields.sfmt_empty.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2676,7 +2739,85 @@ model_m32rx_sc (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32rx_snc (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_sc.f
+#define FLD(f) abuf->fields.sfmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_clrpsw (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clrpsw.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_setpsw (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clrpsw.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_bset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    referenced |= 1 << 0;
+    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_bclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bset.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2686,6 +2827,29 @@ model_m32rx_snc (SIM_CPU *current_cpu, void *sem_arg)
     INT in_sr = -1;
     INT in_dr = -1;
     INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    referenced |= 1 << 0;
+    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_btst (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    referenced |= 1 << 0;
     cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
   }
   return cycles;
@@ -2806,6 +2970,8 @@ static const INSN_TIMING m32rx_timing[] = {
   { M32RXF_INSN_STH, model_m32rx_sth, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } },
   { M32RXF_INSN_STH_D, model_m32rx_sth_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } },
   { M32RXF_INSN_ST_PLUS, model_m32rx_st_plus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
+  { M32RXF_INSN_STH_PLUS, model_m32rx_sth_plus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
+  { M32RXF_INSN_STB_PLUS, model_m32rx_stb_plus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
   { M32RXF_INSN_ST_MINUS, model_m32rx_st_minus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
   { M32RXF_INSN_SUB, model_m32rx_sub, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
   { M32RXF_INSN_SUBV, model_m32rx_subv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
@@ -2823,6 +2989,11 @@ static const INSN_TIMING m32rx_timing[] = {
   { M32RXF_INSN_MACLH1, model_m32rx_maclh1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
   { M32RXF_INSN_SC, model_m32rx_sc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
   { M32RXF_INSN_SNC, model_m32rx_snc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+  { M32RXF_INSN_CLRPSW, model_m32rx_clrpsw, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+  { M32RXF_INSN_SETPSW, model_m32rx_setpsw, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+  { M32RXF_INSN_BSET, model_m32rx_bset, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+  { M32RXF_INSN_BCLR, model_m32rx_bclr, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+  { M32RXF_INSN_BTST, model_m32rx_btst, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
 };
 
 #endif /* WITH_PROFILE_MODEL_P */
@@ -2839,7 +3010,7 @@ m32rx_model_init (SIM_CPU *cpu)
 #define TIMING_DATA(td) 0
 #endif
 
-static const MODEL m32rx_models[] =
+static const SIM_MODEL m32rx_models[] =
 {
   { "m32rx", & m32rx_mach, MODEL_M32RX, TIMING_DATA (& m32rx_timing[0]), m32rx_model_init },
   { 0 }
@@ -2847,7 +3018,7 @@ static const MODEL m32rx_models[] =
 
 /* The properties of this cpu's implementation.  */
 
-static const MACH_IMP_PROPERTIES m32rxf_imp_properties =
+static const SIM_MACH_IMP_PROPERTIES m32rxf_imp_properties =
 {
   sizeof (SIM_CPU),
 #if WITH_SCACHE
@@ -2857,13 +3028,20 @@ static const MACH_IMP_PROPERTIES m32rxf_imp_properties =
 #endif
 };
 
+
+static void
+m32rxf_prepare_run (SIM_CPU *cpu)
+{
+  if (CPU_IDESC (cpu) == NULL)
+    m32rxf_init_idesc_table (cpu);
+}
+
 static const CGEN_INSN *
-m32rxf_opcode (SIM_CPU *cpu, int inum)
+m32rxf_get_idata (SIM_CPU *cpu, int inum)
 {
-  return CPU_IDESC (cpu) [inum].opcode;
+  return CPU_IDESC (cpu) [inum].idata;
 }
 
-/* start-sanitize-m32rx */
 static void
 m32rx_init_cpu (SIM_CPU *cpu)
 {
@@ -2871,8 +3049,8 @@ m32rx_init_cpu (SIM_CPU *cpu)
   CPU_REG_STORE (cpu) = m32rxf_store_register;
   CPU_PC_FETCH (cpu) = m32rxf_h_pc_get;
   CPU_PC_STORE (cpu) = m32rxf_h_pc_set;
-  CPU_OPCODE (cpu) = m32rxf_opcode;
-  CPU_MAX_INSNS (cpu) = M32RXF_INSN_MAX;
+  CPU_GET_IDATA (cpu) = m32rxf_get_idata;
+  CPU_MAX_INSNS (cpu) = M32RXF_INSN__MAX;
   CPU_INSN_NAME (cpu) = cgen_insn_name;
   CPU_FULL_ENGINE_FN (cpu) = m32rxf_engine_run_full;
 #if WITH_FAST
@@ -2880,14 +3058,13 @@ m32rx_init_cpu (SIM_CPU *cpu)
 #else
   CPU_FAST_ENGINE_FN (cpu) = m32rxf_engine_run_full;
 #endif
-  m32rxf_init_idesc_table (cpu);
 }
 
-const MACH m32rx_mach =
+const SIM_MACH m32rx_mach =
 {
-  "m32rx", "m32rx",
+  "m32rx", "m32rx", MACH_M32RX,
   32, 32, & m32rx_models[0], & m32rxf_imp_properties,
-  m32rx_init_cpu
+  m32rx_init_cpu,
+  m32rxf_prepare_run
 };
 
-/* end-sanitize-m32rx */