X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fm32r%2Fmodelx.c;h=a17493ddb8b9a8b2e0f6bb00960480e0dc17cbcf;hb=1e92785005ce880a5fac9d022f05cdcff91c3091;hp=c0388b0892019111c18d187b4ea81b5865b11f42;hpb=4744ac1bb0d2f2294c7762577262fdcafb67883b;p=deliverable%2Fbinutils-gdb.git
diff --git a/sim/m32r/modelx.c b/sim/m32r/modelx.c
index c0388b0892..a17493ddb8 100644
--- a/sim/m32r/modelx.c
+++ b/sim/m32r/modelx.c
@@ -2,22 +2,22 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+Copyright 1996-2020 Free Software Foundation, Inc.
This file is part of the GNU simulators.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
-You should have received a copy of the GNU General Public License
-along with this program. If not, see .
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, see .
*/
@@ -1822,7 +1822,7 @@ model_m32rx_neg (SIM_CPU *current_cpu, void *sem_arg)
static int
model_m32rx_nop (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1900,7 +1900,7 @@ model_m32rx_rach_dsi (SIM_CPU *current_cpu, void *sem_arg)
static int
model_m32rx_rte (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2614,7 +2614,7 @@ model_m32rx_pcmpbz (SIM_CPU *current_cpu, void *sem_arg)
static int
model_m32rx_sadd (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2720,7 +2720,7 @@ model_m32rx_maclh1 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_m32rx_sc (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2739,7 +2739,7 @@ model_m32rx_sc (SIM_CPU *current_cpu, void *sem_arg)
static int
model_m32rx_snc (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3010,7 +3010,7 @@ m32rx_model_init (SIM_CPU *cpu)
#define TIMING_DATA(td) 0
#endif
-static const MODEL m32rx_models[] =
+static const SIM_MODEL m32rx_models[] =
{
{ "m32rx", & m32rx_mach, MODEL_M32RX, TIMING_DATA (& m32rx_timing[0]), m32rx_model_init },
{ 0 }
@@ -3018,7 +3018,7 @@ static const MODEL m32rx_models[] =
/* The properties of this cpu's implementation. */
-static const MACH_IMP_PROPERTIES m32rxf_imp_properties =
+static const SIM_MACH_IMP_PROPERTIES m32rxf_imp_properties =
{
sizeof (SIM_CPU),
#if WITH_SCACHE
@@ -3060,7 +3060,7 @@ m32rx_init_cpu (SIM_CPU *cpu)
#endif
}
-const MACH m32rx_mach =
+const SIM_MACH m32rx_mach =
{
"m32rx", "m32rx", MACH_M32RX,
32, 32, & m32rx_models[0], & m32rxf_imp_properties,