X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fmcore%2Fsim-main.h;h=773ab976e34047a32fd57192489d907d7e6b81ec;hb=17fc27167f678285d2f64040837b8cc41b6a664a;hp=80b467a11722e446bf2a9366fcc80a0edb3faa27;hpb=78e9aa70febc3985a2c88dbc0c7a87d214231c3d;p=deliverable%2Fbinutils-gdb.git

diff --git a/sim/mcore/sim-main.h b/sim/mcore/sim-main.h
index 80b467a117..773ab976e3 100644
--- a/sim/mcore/sim-main.h
+++ b/sim/mcore/sim-main.h
@@ -1,5 +1,5 @@
 /* Simulator for Motorola's MCore processor
-   Copyright (C) 2009-2015 Free Software Foundation, Inc.
+   Copyright (C) 2009-2020 Free Software Foundation, Inc.
 
 This file is part of GDB, the GNU debugger.
 
@@ -21,21 +21,49 @@ along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
 
 #include "sim-basics.h"
 
-typedef address_word sim_cia;
 typedef long int           word;
 typedef unsigned long int  uword;
 
-typedef struct _sim_cpu SIM_CPU;
-
 #include "sim-base.h"
 #include "bfd.h"
 
-#define CIA_GET(cpu)     (cpu)->pc
-#define CIA_SET(cpu,val) (cpu)->pc = (val)
+/* The machine state.
+   This state is maintained in host byte order.  The
+   fetch/store register functions must translate between host
+   byte order and the target processor byte order.
+   Keeping this data in target byte order simplifies the register
+   read/write functions.  Keeping this data in native order improves
+   the performance of the simulator.  Simulation speed is deemed more
+   important.  */
+
+/* The ordering of the mcore_regset structure is matched in the
+   gdb/config/mcore/tm-mcore.h file in the REGISTER_NAMES macro.  */
+struct mcore_regset
+{
+  word gregs[16];	/* primary registers */
+  word alt_gregs[16];	/* alt register file */
+  word cregs[32];	/* control registers */
+  word pc;
+};
+#define LAST_VALID_CREG	32		/* only 0..12 implemented */
+#define NUM_MCORE_REGS	(16 + 16 + LAST_VALID_CREG + 1)
 
 struct _sim_cpu {
 
-  word pc;
+  union
+  {
+    struct mcore_regset regs;
+    /* Used by the fetch/store reg helpers to access registers linearly.  */
+    word asints[NUM_MCORE_REGS];
+  };
+
+  /* Used to switch between gregs/alt_gregs based on the control state.  */
+  word *active_gregs;
+
+  int ticks;
+  int stalls;
+  int cycles;
+  int insts;
 
   sim_cpu_base base;
 };