X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fmips%2FChangeLog;h=ab70c7e5b89d606f61cfb8128c0d148766642961;hb=b0b39eb2de25862b18d574bca791e39c3643c231;hp=43b26cb252fba27b09affe016016373857e8a337;hpb=462cfbc4eb1801c8d81ecff175242a1be8a9b820;p=deliverable%2Fbinutils-gdb.git diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 43b26cb252..ab70c7e5b8 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,513 @@ +start-sanitize-sky +Thu Apr 9 16:38:23 1998 Frank Ch. Eigler + + * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses + instead of QUADWORD. + + * sim-main.h: Removed attempt at allowing 128-bit access. + +end-sanitize-sky +start-sanitize-sky + Wed Apr 8 18:12:13 1998 Frank Ch. Eigler + + * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o. + + * interp.c (decode_coproc): Refer to VU CIA as a "special" + register, not as a "misc" register. Aha. Add activity + assertions after VCALLMS* instructions. + +end-sanitize-sky +start-sanitize-sky + Tue Apr 7 18:32:49 1998 Frank Ch. Eigler + + * interp.c (decode_coproc): Do not apply superfluous E (end) flag + to upper code of generated VU instruction. + +end-sanitize-sky +start-sanitize-sky +Mon Apr 6 19:55:56 1998 Frank Ch. Eigler + + * interp.c (cop_[ls]q): Replaced stub with proper COP2 code. + + * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses + for TARGET_SKY. + + * r5900.igen (SQC2): Thinko. + +end-sanitize-sky +start-sanitize-sky +Sun Apr 5 12:05:44 1998 Frank Ch. Eigler + + * interp.c (*): Adapt code to merged VU device & state structs. + (decode_coproc): Execute COP2 each macroinstruction without + pipelining, by stepping VU to completion state. Adapted to + read_vu_*_reg style of register access. + + * mips.igen ([SL]QC2): Removed these COP2 instructions. + + * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. + + * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. + +end-sanitize-sky +Sat Apr 4 22:39:50 1998 Andrew Cagney + + * Makefile.in (SIM_OBJS): Add sim-main.o. + + * sim-main.h (address_translation, load_memory, store_memory, + cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark + as INLINE_SIM_MAIN. + (pr_addr, pr_uword64): Declare. + (sim-main.c): Include when H_REVEALS_MODULE_P. + + * interp.c (address_translation, load_memory, store_memory, + cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move + from here. + * sim-main.c: To here. Fix compilation problems. + + * configure.in: Enable inlining. + * configure: Re-config. + +Sat Apr 4 20:36:25 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Apr 3 04:32:35 1998 Andrew Cagney + + * mips.igen: Include tx.igen. + * Makefile.in (IGEN_INCLUDE): Add tx.igen. + * tx.igen: New file, contains MADD and MADDU. + + * interp.c (load_memory): When shifting bytes, use LOADDRMASK not + the hardwired constant `7'. + (store_memory): Ditto. + (LOADDRMASK): Move definition to sim-main.h. + + mips.igen (MTC0): Enable for r3900. + (ADDU): Add trace. + + mips.igen (do_load_byte): Delete. + (do_load, do_store, do_load_left, do_load_write, do_store_left, + do_store_right): New functions. + (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use. + + configure.in: Let the tx39 use igen again. + configure: Update. + +Thu Apr 2 10:59:39 1998 Andrew Cagney + + * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity, + not an address sized quantity. Return zero for cache sizes. + +Wed Apr 1 23:47:53 1998 Andrew Cagney + + * mips.igen (r3900): r3900 does not support 64 bit integer + operations. + +start-sanitize-sky +Wed Apr 1 08:20:31 1998 Frank Ch. Eigler + + * mips.igen (SQC2/LQC2): Make bodies sky-target-only also. + +end-sanitize-sky +start-sanitize-sky +Mon Mar 30 18:41:43 1998 Frank Ch. Eigler + + * interp.c (decode_coproc): Continuing COP2 work. + (cop_[ls]q): Make sky-target-only. + + * sim-main.h (COP_[LS]Q): Make sky-target-only. +end-sanitize-sky +Mon Mar 30 14:46:05 1998 Gavin Koch + + * configure.in (mipstx39*-*-*): Use gencode simulator rather + than igen one. + * configure : Rebuild. + +start-sanitize-sky +Sun Mar 29 17:50:11 Frank Ch. Eigler + + * interp.c (decode_coproc): Added a missing TARGET_SKY check + around COP2 implementation skeleton. + +end-sanitize-sky +start-sanitize-sky +Fri Mar 27 16:19:29 1998 Frank Ch. Eigler + + * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. + + * interp.c (sim_{load,store}_register): Use new vu[01]_device + static to access VU registers. + (decode_coproc): Added skeleton of sky COP2 (VU) instruction + decoding. Work in progress. + + * mips.igen (LDCzz, SDCzz): Removed *5900 case for this + overlapping/redundant bit pattern. + (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in + progress. + + * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for + status register. + + * interp.c (cop_lq, cop_sq): New functions for future 128-bit + access to coprocessor registers. + + * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. +end-sanitize-sky +Fri Mar 27 16:15:52 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Mar 27 15:01:50 1998 Andrew Cagney + + * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS. + +Wed Mar 25 16:44:27 1998 Ian Carmichael + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Regenerated to track ../common/aclocal.m4 changes. + +Wed Mar 25 12:35:29 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Mar 25 10:05:46 1998 Andrew Cagney + + * interp.c (Max, Min): Comment out functions. Not yet used. + +start-sanitize-vr4320 +Wed Mar 25 10:04:13 1998 Andrew Cagney + + * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format. + +end-sanitize-vr4320 +Wed Mar 18 12:38:12 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Tue Mar 17 19:05:20 1998 Frank Ch. Eigler + + * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added + configurable settings for stand-alone simulator. + +start-sanitize-sky + * configure.in: Added --with-sim-gpu2 option to specify path of + sky GPU2 library. Triggers -DSKY_GPU2 for sky-gpuif.c, and + links/compiles stand-alone simulator with this library. + + * interp.c (MEM_SIZE): Increased default sky memory size to 16MB. +end-sanitize-sky + * configure.in: Added X11 search, just in case. + + * configure: Regenerated. + +Wed Mar 11 14:09:10 1998 Andrew Cagney + + * interp.c (sim_write, sim_read, load_memory, store_memory): + Replace sim_core_*_map with read_map, write_map, exec_map resp. + +start-sanitize-vr4320 +Tue Mar 10 10:32:22 1998 Gavin Koch + + * vr4320.igen (clz,dclz) : Added. + (dmac): Replaced 99, with LO. + +end-sanitize-vr4320 +start-sanitize-vr5400 +Fri Mar 6 08:30:58 1998 Andrew Cagney + + * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields. + +end-sanitize-vr5400 +start-sanitize-vr4320 +Tue Mar 3 11:56:29 1998 Gavin Koch + + * vr4320.igen: New file. + * Makefile.in (vr4320.igen) : Added. + * configure.in (mips64vr4320-*-*): Added. + * configure : Rebuilt. + * mips.igen : Correct the bfd-names in the mips-ISA model entries. + Add the vr4320 model entry and mark the vr4320 insn as necessary. + +end-sanitize-vr4320 +Tue Mar 3 13:58:43 1998 Andrew Cagney + + * sim-main.h (GETFCC): Return an unsigned value. + +start-sanitize-r5900 + * r5900.igen: Use an unsigned array index variable `i'. + (QFSRV): Ditto for variable bytes. + +end-sanitize-r5900 +Tue Mar 3 13:21:37 1998 Andrew Cagney + + * mips.igen (DIV): Fix check for -1 / MIN_INT. + (DADD): Result destination is RD not RT. + +start-sanitize-r5900 + * r5900.igen (DIV1): Fix check for -1 / MIN_INT. + (DIVU1): Don't check for MIN_INT / -1 as performing unsigned + divide. + +end-sanitize-r5900 +Fri Feb 27 13:49:49 1998 Andrew Cagney + + * sim-main.h (HIACCESS, LOACCESS): Always define. + + * mdmx.igen (Maxi, Mini): Rename Max, Min. + + * interp.c (sim_info): Delete. + +Fri Feb 27 18:41:01 1998 Doug Evans + + * interp.c (DECLARE_OPTION_HANDLER): Use it. + (mips_option_handler): New argument `cpu'. + (sim_open): Update call to sim_add_option_table. + +Wed Feb 25 18:56:22 1998 Andrew Cagney + + * mips.igen (CxC1): Add tracing. + +start-sanitize-r5900 +Wed Feb 25 13:59:03 1998 Andrew Cagney + + * r5900.igen (StoreFP): Delete. + (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3): + New functions. + (rsqrt.s, sqrt.s): Implement. + (r59cond): New function. + (C.COND.S): Call r59cond in assembler line. + (cvt.w.s, cvt.s.w): Implement. + + * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900 + instruction set. + + * sim-main.h: Define an enum of r5900 FCSR bit fields. + +end-sanitize-r5900 +start-sanitize-r5900 +Tue Feb 24 14:44:18 1998 Andrew Cagney + + * r5900.igen: Add tracing to all p* instructions. + +Tue Feb 24 02:47:33 1998 Andrew Cagney + + * interp.c (sim_store_register, sim_fetch_register): Pull swifty + to get gdb talking to re-aranged sim_cpu register structure. + +end-sanitize-r5900 +Fri Feb 20 17:43:21 1998 Andrew Cagney + + * sim-main.h (Max, Min): Declare. + + * interp.c (Max, Min): New functions. + + * mips.igen (BC1): Add tracing. + +start-sanitize-vr5400 +Fri Feb 20 16:27:17 1998 Andrew Cagney + + * mdmx.igen: Tag all functions as requiring either with mdmx or + vr5400 processor. + +end-sanitize-vr5400 +start-sanitize-r5900 +Fri Feb 20 15:55:51 1998 Andrew Cagney + + * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size + to 32. + (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32. + + * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set. + + * r5900.igen: Rewrite. + + * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu + struct. + (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD): + Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1 + +end-sanitize-r5900 +Thu Feb 19 14:50:00 1998 John Metzler + + * interp.c Added memory map for stack in vr4100 + +Thu Feb 19 10:21:21 1998 Gavin Koch + + * interp.c (load_memory): Add missing "break"'s. + +Tue Feb 17 12:45:35 1998 Andrew Cagney + + * interp.c (sim_store_register, sim_fetch_register): Pass in + length parameter. Return -1. + +Tue Feb 10 11:57:40 1998 Ian Carmichael + + * interp.c: Added hardware init hook, fixed warnings. + +Sat Feb 7 17:16:20 1998 Andrew Cagney + + * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL. + +Tue Feb 3 11:36:02 1998 Andrew Cagney + + * interp.c (ifetch16): New function. + + * sim-main.h (IMEM32): Rename IMEM. + (IMEM16_IMMED): Define. + (IMEM16): Define. + (DELAY_SLOT): Update. + + * m16run.c (sim_engine_run): New file. + + * m16.igen: All instructions except LB. + (LB): Call do_load_byte. + * mips.igen (do_load_byte): New function. + (LB): Call do_load_byte. + + * mips.igen: Move spec for insn bit size and high bit from here. + * Makefile.in (tmp-igen, tmp-m16): To here. + + * m16.dc: New file, decode mips16 instructions. + + * Makefile.in (SIM_NO_ALL): Define. + (tmp-m16): Generate both 16 bit and 32 bit simulator engines. + +start-sanitize-tx19 + * m16.igen: Mark all mips16 insns as being part of the tx19 insn + set. + +end-sanitize-tx19 +Tue Feb 3 11:28:00 1998 Andrew Cagney + + * configure.in (mips_fpu_bitsize): For tx39, restrict floating + point unit to 32 bit registers. + * configure: Re-generate. + +Sun Feb 1 15:47:14 1998 Andrew Cagney + + * configure.in (sim_use_gen): Make IGEN the default simulator + generator for generic 32 and 64 bit mips targets. + * configure: Re-generate. + +Sun Feb 1 16:52:37 1998 Andrew Cagney + + * sim-main.h (SizeFGR): Determine from floating-point and not gpr + bitsize. + + * interp.c (sim_fetch_register, sim_store_register): Read/write + FGR from correct location. + (sim_open): Set size of FGR's according to + WITH_TARGET_FLOATING_POINT_BITSIZE. + + * sim-main.h (FGR): Store floating point registers in a separate + array. + +Sun Feb 1 16:47:51 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +start-sanitize-vr5400 + * mdmx.igen: Mark all instructions as 64bit/fp specific. + +end-sanitize-vr5400 +Tue Feb 3 00:10:50 1998 Andrew Cagney + + * interp.c (ColdReset): Call PENDING_INVALIDATE. + + * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK. + + * interp.c (pending_tick): New function. Deliver pending writes. + + * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED, + PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that + it can handle mixed sized quantites and single bits. + +Mon Feb 2 17:43:15 1998 Andrew Cagney + + * interp.c (oengine.h): Do not include when building with IGEN. + (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE. + (sim_info): Ditto for PROCESSOR_64BIT. + (sim_monitor): Replace ut_reg with unsigned_word. + (*): Ditto for t_reg. + (LOADDRMASK): Define. + (sim_open): Remove defunct check that host FP is IEEE compliant, + using software to emulate floating point. + (value_fpr, ...): Always compile, was conditional on HASFPU. + +Sun Feb 1 11:15:29 1998 Andrew Cagney + + * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in + size. + + * interp.c (SD, CPU): Define. + (mips_option_handler): Set flags in each CPU. + (interrupt_event): Assume CPU 0 is the one being iterrupted. + (sim_close): Do not clear STATE, deleted anyway. + (sim_write, sim_read): Assume CPU zero's vm should be used for + data transfers. + (sim_create_inferior): Set the PC for all processors. + (sim_monitor, store_word, load_word, mips16_entry): Add cpu + argument. + (mips16_entry): Pass correct nr of args to store_word, load_word. + (ColdReset): Cold reset all cpu's. + (signal_exception): Pass cpu to sim_monitor & mips16_entry. + (sim_monitor, load_memory, store_memory, signal_exception): Use + `CPU' instead of STATE_CPU. + + + * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with + SD or CPU_. + + * sim-main.h (signal_exception): Add sim_cpu arg. + (SignalException*): Pass both SD and CPU to signal_exception. + * interp.c (signal_exception): Update. + + * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c: + Ditto + (sync_operation, prefetch, cache_op, store_memory, load_memory, + address_translation): Ditto + (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto. + +start-sanitize-vr5400 + * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of + `sd'. + (ByteAlign): Use StoreFPR, pass args in correct order. + +end-sanitize-vr5400 +start-sanitize-r5900 +Sun Feb 1 10:59:55 1998 Andrew Cagney + + * configure.in (sim_igen_filter): For r5900, configure as SMP. + +end-sanitize-r5900 +Sat Jan 31 18:15:41 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Sat Jan 31 14:49:24 1998 Andrew Cagney + +start-sanitize-r5900 + * configure.in (sim_igen_filter): For r5900, use igen. + * configure: Re-generate. + +end-sanitize-r5900 + * interp.c (sim_engine_run): Add `nr_cpus' argument. + + * mips.igen (model): Map processor names onto BFD name. + + * sim-main.h (CPU_CIA): Delete. + (SET_CIA, GET_CIA): Define + +Wed Jan 21 16:16:27 1998 Andrew Cagney + + * sim-main.h (GPR_SET): Define, used by igen when zeroing a + regiser. + + * configure.in (default_endian): Configure a big-endian simulator + by default. + * configure: Re-generate. + Mon Jan 19 22:26:29 1998 Doug Evans * configure: Regenerated to track ../common/aclocal.m4 changes.