X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fmips%2Fconfigure.in;h=3672b66e73a9e51011da02b991c6c3579c1d2ec8;hb=c263362b613c1d25d2aa598512950b13cdf9daed;hp=638c58ced3e952dfaa8b6bc826a9aec94c7fec24;hpb=295dbbe44c182edd4201672e6ed5eda9323cfdf4;p=deliverable%2Fbinutils-gdb.git

diff --git a/sim/mips/configure.in b/sim/mips/configure.in
index 638c58ced3..3672b66e73 100644
--- a/sim/mips/configure.in
+++ b/sim/mips/configure.in
@@ -1,19 +1,190 @@
-dnl Process this file with `autoconf -l ../common' to produce a configure script.
+dnl Process this file with autoconf to produce a configure script.
+sinclude(../common/aclocal.m4)
 AC_PREREQ(2.5)dnl
 AC_INIT(Makefile.in)
 
 SIM_AC_COMMON
 
-# Ensure a reasonable default simulator is constructed:
+dnl Options available in this module
+SIM_AC_OPTION_INLINE()
+SIM_AC_OPTION_ALIGNMENT(NONSTRICT_ALIGNMENT)
+SIM_AC_OPTION_HOSTENDIAN
+SIM_AC_OPTION_WARNINGS
+
+# DEPRECATED
+#
+# Instead of defining a `subtarget' macro, code should be checking
+# the value of {STATE,CPU}_ARCHITECTURE to identify the architecture
+# in question.
+#
+case "${target}" in
+  mips*tx39*)           SIM_SUBTARGET="-DSUBTARGET_R3900=1";;
+  mipsisa32*-*-*)       SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";;
+  mipsisa64*-*-*)       SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";;
+  *)                    SIM_SUBTARGET="";;
+esac
+AC_SUBST(SIM_SUBTARGET)
+
+
+
+#
+# Select the byte order of the target
+#
+mips_endian=
+default_endian=
+case "${target}" in
+  mips64el*-*-*)	mips_endian=LITTLE_ENDIAN ;;
+  mips64vr*el-*-*)      default_endian=LITTLE_ENDIAN ;;
+  mips64*-*-*)          default_endian=BIG_ENDIAN ;;
+  mips16*-*-*)          default_endian=BIG_ENDIAN ;;
+  mipsisa32*-*-*)       default_endian=BIG_ENDIAN ;;
+  mipsisa64*-*-*)       default_endian=BIG_ENDIAN ;;
+  mips*-*-*)            default_endian=BIG_ENDIAN ;;
+  *)                    default_endian=BIG_ENDIAN ;;
+esac
+SIM_AC_OPTION_ENDIAN($mips_endian,$default_endian)
+
+
+
+#
+# Select the bitsize of the target
+#
+mips_addr_bitsize=
+case "${target}" in
+  mips64*-*-*)          mips_bitsize=64 ; mips_msb=63 ;;
+  mips16*-*-*)          mips_bitsize=64 ; mips_msb=63 ;;
+  mipsisa32*-*-*)       mips_bitsize=32 ; mips_msb=31 ;;
+  mipsisa64*-*-*)       mips_bitsize=64 ; mips_msb=63 ;;
+  mips*-*-*)            mips_bitsize=32 ; mips_msb=31 ;;
+  *)                    mips_bitsize=64 ; mips_msb=63 ;;
+esac
+SIM_AC_OPTION_BITSIZE($mips_bitsize,$mips_msb,$mips_addr_bitsize)
+
+
+
+#
+# Select the floating hardware support of the target
+#
+mips_fpu=HARDWARE_FLOATING_POINT
+mips_fpu_bitsize=
+case "${target}" in
+  mips*tx39*)		mips_fpu=HARD_FLOATING_POINT
+			mips_fpu_bitsize=32
+			;;
+  mips64*-*-*)          mips_fpu=HARD_FLOATING_POINT ;;
+  mips16*-*-*)          mips_fpu=HARD_FLOATING_POINT ;;
+  mipsisa32*-*-*)       mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=64 ;;
+  mipsisa64*-*-*)       mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=64 ;;
+  mips*-*-*)            mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=32 ;;
+  *)                    mips_fpu=HARD_FLOATING_POINT ;;
+esac
+SIM_AC_OPTION_FLOAT($mips_fpu,$mips_fpu_bitsize)
+
+
+
+#
+# Select the level of SMP support
+#
+case "${target}" in
+  *)                    mips_smp=0 ;;
+esac
+SIM_AC_OPTION_SMP($mips_smp)
+
+
+
+#
+# Select the IGEN architecture
+#
+sim_gen=IGEN
+sim_igen_machine="-M mipsIV"
+sim_m16_machine="-M mips16"
+sim_igen_filter="32,64,f"
+sim_m16_filter="16"
+case "${target}" in
+  mips*tx39*)		sim_gen=IGEN
+			sim_igen_filter="32,f"
+			sim_igen_machine="-M r3900"
+			;;
+  mips64vr43*-*-*)	sim_gen=IGEN
+			sim_igen_machine="-M mipsIV"
+			;;
+  mips64vr5*-*-*)	sim_gen=IGEN
+			sim_igen_machine="-M vr5000"
+			;;
+  mips64vr41*)		sim_gen=M16
+			sim_igen_machine="-M vr4100"
+			sim_m16_machine="-M vr4100"
+			sim_igen_filter="32,64,f"
+			sim_m16_filter="16"
+                        ;;
+  mips64*-*-*)		sim_igen_filter="32,64,f"
+			sim_gen=IGEN
+			;;
+  mips16*-*-*)		sim_gen=M16
+			sim_igen_filter="32,64,f"
+			sim_m16_filter="16"
+			;;
+  mipsisa32*-*-*)	sim_gen=IGEN
+		        sim_igen_machine="-M mips32"
+			sim_igen_filter="32,f"
+			;;
+  mipsisa64sb1*-*-*)	sim_gen=IGEN
+		        sim_igen_machine="-M mips64,sb1"
+			sim_igen_filter="32,64,f"
+			;;
+  mipsisa64*-*-*)	sim_gen=IGEN
+		        sim_igen_machine="-M mips64,mips3d"
+			sim_igen_filter="32,64,f"
+			;;
+  mips*lsi*)	        sim_gen=M16
+			sim_igen_machine="-M mipsIII,mips16"
+			sim_m16_machine="-M mips16,mipsIII"
+			sim_igen_filter="32,f"
+			sim_m16_filter="16"
+                        ;;
+  mips*-*-*)		sim_gen=IGEN
+			sim_igen_filter="32,f"
+			;;
+esac
+sim_igen_flags="-F ${sim_igen_filter} ${sim_igen_machine} ${sim_igen_smp}"
+sim_m16_flags=" -F ${sim_m16_filter}  ${sim_m16_machine}  ${sim_igen_smp}"
+AC_SUBST(sim_igen_flags)
+AC_SUBST(sim_m16_flags)
+AC_SUBST(sim_gen)
+
+
+#
+# Add simulated hardware devices
+#
+hw_enabled=no
 case "${target}" in
-  mips64*-*-*)          SIMCONF="-mips0 --warnings";;
-  mips16*-*-*)          SIMCONF="-mips0 --warnings";;
-  mips*-*-*)            SIMCONF="-mips2 --warnings";;
-  *)                    SIMCONF="-mips0 --warnings";;
+  mips*tx39*)
+	hw_enabled=yes
+	hw_extra_devices="tx3904cpu tx3904irc tx3904tmr tx3904sio" 
+	mips_extra_objs="dv-sockser.o"
+	SIM_SUBTARGET="$SIM_SUBTARGET -DTARGET_TX3904=1"
+	;;
+  *)
+	mips_extra_objs="" 
+	;;
 esac
-AC_SUBST(SIMCONF)
+SIM_AC_OPTION_HARDWARE($hw_enabled,$hw_devices,$hw_extra_devices)
+AC_SUBST(mips_extra_objs)
+
+
+# Choose simulator engine
+case "${target}" in
+  *)    mips_igen_engine="engine.o"
+	;;
+esac
+AC_SUBST(mips_igen_engine)
+
+
+AC_PATH_X
+mips_extra_libs=""
+AC_SUBST(mips_extra_libs)
 
-AC_CHECK_HEADERS(string.h strings.h stdlib.h)
+AC_CHECK_HEADERS(string.h strings.h stdlib.h stdlib.h)
 AC_CHECK_LIB(m, fabs)
 AC_CHECK_FUNCS(aint anint sqrt)