X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fmips%2Fmicromips.igen;h=bddea52e7bd44caee11a6b8d454de8ff6c84a571;hb=9e790a80160676e7fd3fb8be6cf3c1c77d9ded81;hp=f24220e6ce974fe3547aa201eebf1f8aaad55432;hpb=1d19cae752a7b032b8253feb4fa3b9f1dc162823;p=deliverable%2Fbinutils-gdb.git

diff --git a/sim/mips/micromips.igen b/sim/mips/micromips.igen
index f24220e6ce..bddea52e7b 100644
--- a/sim/mips/micromips.igen
+++ b/sim/mips/micromips.igen
@@ -1,5 +1,5 @@
 // Simulator definition for the micromips ASE.
-// Copyright (C) 2005-2015 Free Software Foundation, Inc.
+// Copyright (C) 2005-2020 Free Software Foundation, Inc.
 // Contributed by Imagination Technologies, Ltd.
 // Written by Andrew Bennett <andrew.bennett@imgtec.com>
 //
@@ -39,6 +39,9 @@
 :compute:::int:IMM_SHIFT_2BIT:IMMEDIATE:(IMMEDIATE << 2)
 
 :function:::address_word:delayslot_micromips:address_word target, address_word nia, int delayslot_instruction_size
+*micromips32:
+*micromips64:
+*micromipsdsp:
 {
   instruction_word delay_insn;
   sim_events_slip (SD, 1);
@@ -52,12 +55,16 @@
 }
 
 :function:::address_word:process_isa_mode:address_word target
+*micromips32:
+*micromips64:
 {
   SD->isa_mode = target & 0x1;
   return (target & (-(1 << 1)));
 }
 
 :function:::address_word:do_micromips_jalr:int rt, int rs, address_word nia, int delayslot_instruction_size
+*micromips32:
+*micromips64:
 {
   GPR[rt] = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS;
   return (process_isa_mode (SD_,
@@ -65,6 +72,8 @@
 }
 
 :function:::address_word:do_micromips_jal:address_word target, address_word nia, int delayslot_instruction_size
+*micromips32:
+*micromips64:
 {
   RA = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS;
   return delayslot_micromips (SD_, target, nia, delayslot_instruction_size);
@@ -72,6 +81,8 @@
 
 
 :function:::unsigned32:compute_movep_src_reg:int reg
+*micromips32:
+*micromips64:
 {
   switch(reg)
     {
@@ -88,6 +99,8 @@
 }
 
 :function:::unsigned32:compute_andi16_imm:int encoded_imm
+*micromips32:
+*micromips64:
 {
   switch (encoded_imm)
     {
@@ -112,6 +125,8 @@
 }
 
 :function:::FP_formats:convert_fmt_micromips:int fmt
+*micromips32:
+*micromips64:
 {
   switch (fmt)
     {
@@ -123,6 +138,8 @@
 }
 
 :function:::FP_formats:convert_fmt_micromips_cvt_d:int fmt
+*micromips32:
+*micromips64:
 {
   switch (fmt)
     {
@@ -135,6 +152,8 @@
 
 
 :function:::FP_formats:convert_fmt_micromips_cvt_s:int fmt
+*micromips32:
+*micromips64:
 {
   switch (fmt)
     {
@@ -845,11 +864,8 @@
   address_word base = GPR[BASE];
   address_word offset = EXTEND12 (IMMEDIATE);
   address_word vaddr = loadstore_ea (SD_, base, offset);
-  address_word paddr;
-  int uncached;
-  if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
-			  isTARGET, isREAL))
-    CacheOp (OP, vaddr, paddr, instruction_0);
+  address_word paddr = vaddr;
+  CacheOp (OP, vaddr, paddr, instruction_0);
 }
 
 
@@ -2255,6 +2271,8 @@
 
 
 :%s::::FMT_MICROMIPS:int fmt
+*micromips32:
+*micromips64:
 {
   switch (fmt)
     {
@@ -2267,6 +2285,8 @@
 
 
 :%s::::FMT_MICROMIPS_CVT_D:int fmt
+*micromips32:
+*micromips64:
 {
   switch (fmt)
     {
@@ -2279,6 +2299,8 @@
 
 
 :%s::::FMT_MICROMIPS_CVT_S:int fmt
+*micromips32:
+*micromips64:
 {
   switch (fmt)
     {