X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fmips%2Fmips.igen;h=39267a0bf1b7c9733fcb81a7fb5792d25fecec0a;hb=06e7837e0fe0681494ebdc4f7aae51ef3f77a5fe;hp=d8d4dfa58cf5f93c8743b883889e3b9a8c10e4a8;hpb=82f728dbb8c6170c01f938b09076fb0992accbf1;p=deliverable%2Fbinutils-gdb.git

diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index d8d4dfa58c..39267a0bf1 100644
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -44,6 +44,8 @@
 :model:::mipsIII:mips4000:
 :model:::mipsIV:mips8000:
 :model:::mipsV:mipsisaV:
+:model:::mips32:mipsisa32:
+:model:::mips64:mipsisa64:
 
 //  Vendor ISAs:
 //
@@ -59,7 +61,16 @@
 //  MIPS Application Specific Extensions (ASEs)
 //
 //  Instructions for the ASEs are in separate .igen files.
+//  ASEs add instructions on to a base ISA.
 :model:::mips16:mips16:			// m16.igen (and m16.dc)
+:model:::mips3d:mips3d:			// mips3d.igen
+:model:::mdmx:mdmx:			// mdmx.igen
+
+//  Vendor Extensions
+//
+//  Instructions specific to these extensions are in separate .igen files.
+//  Extensions add instructions on to a base ISA.
+:model:::sb1:sb1:			// sb1.igen
 
 
 // Pseudo instructions known by IGEN
@@ -117,6 +128,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
 *vr4100:
 *vr5000:
 *r3900:
@@ -124,6 +136,84 @@
   return base + offset;
 }
 
+:function:::address_word:loadstore_ea:address_word base, address_word offset
+*mips64:
+{
+#if 0 /* XXX FIXME: enable this only after some additional testing.  */
+  /* If in user mode and UX is not set, use 32-bit compatibility effective
+     address computations as defined in the MIPS64 Architecture for
+     Programmers Volume III, Revision 0.95, section 4.9.  */
+  if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
+      == (ksu_user << status_KSU_shift))
+    return (address_word)((signed32)base + (signed32)offset);
+#endif
+  return base + offset;
+}
+
+
+// Helper:
+//
+// Check that a 32-bit register value is properly sign-extended.
+// (See NotWordValue in ISA spec.)
+//
+
+:function:::int:not_word_value:unsigned_word value
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+  /* For historical simulator compatibility (until documentation is
+     found that makes these operations unpredictable on some of these
+     architectures), this check never returns true.  */
+  return 0;
+}
+
+:function:::int:not_word_value:unsigned_word value
+*mips32:
+{
+  /* On MIPS32, since registers are 32-bits, there's no check to be done.  */
+  return 0;
+}
+
+:function:::int:not_word_value:unsigned_word value
+*mips64:
+{
+  return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0));
+}
+
+
+// Helper:
+//
+// Handle UNPREDICTABLE operation behaviour.  The goal here is to prevent
+// theoretically portable code which invokes non-portable behaviour from
+// running with no indication of the portability issue.
+// (See definition of UNPREDICTABLE in ISA spec.)
+//
+
+:function:::void:unpredictable:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+}
+
+:function:::void:unpredictable:
+*mips32:
+*mips64:
+{
+  unpredictable_action (CPU, CIA);
+}
+
 
 // Helper:
 //
@@ -167,6 +257,8 @@
 }
 
 :function:::int:check_mt_hilo:hilo_history *history
+*mips32:
+*mips64:
 *r3900:
 {
   signed64 time = sim_events_time (SD);
@@ -182,6 +274,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -234,6 +328,8 @@
 // The r3900 mult and multu insns _can_ be exectuted immediatly after
 // a mf{hi,lo}
 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
+*mips32:
+*mips64:
 *r3900:
 {
   /* FIXME: could record the fact that a stall occured if we want */
@@ -252,6 +348,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -280,16 +378,24 @@
 *vr4100:
 *vr5000:
 {
-  // On mips64, if UserMode check SR:PX & SR:UX bits.
   // The check should be similar to mips64 for any with PX/UX bit equivalents.
 }
 
+:function:::void:check_u64:instruction_word insn
+*mips64:
+{
+#if 0 /* XXX FIXME: enable this only after some additional testing.  */
+  if (UserMode && (SR & (status_UX|status_PX)) == 0)
+    SignalException (ReservedInstruction, insn);
+#endif
+}
+
 
 
 //
 // MIPS Architecture:
 //
-//        CPU Instruction Set (mipsI - mipsV)
+//        CPU Instruction Set (mipsI - mipsV, mips32, mips64)
 //
 
 
@@ -301,10 +407,14 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
+  if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+    Unpredictable ();
   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
   {
     ALU32_BEGIN (GPR[RS]);
@@ -323,10 +433,14 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
+  if (NotWordValue (GPR[RS]))
+    Unpredictable ();
   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
   {
     ALU32_BEGIN (GPR[RS]);
@@ -340,6 +454,8 @@
 
 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 {
+  if (NotWordValue (GPR[rs]))
+    Unpredictable ();
   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
   TRACE_ALU_RESULT (GPR[rt]);
@@ -352,6 +468,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -363,6 +481,8 @@
 
 :function:::void:do_addu:int rs, int rt, int rd
 {
+  if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
+    Unpredictable ();
   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
   TRACE_ALU_RESULT (GPR[rd]);
@@ -375,6 +495,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -398,6 +520,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -414,6 +538,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -432,6 +558,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -453,6 +581,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -477,6 +607,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -499,12 +631,16 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
   check_branch_bug ();
+  if (RS == 31)
+    Unpredictable ();
   RA = (CIA + 8);
   if ((signed_word) GPR[RS] >= 0)
     {
@@ -521,12 +657,16 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
   check_branch_bug ();
+  if (RS == 31)
+    Unpredictable ();
   RA = (CIA + 8);
   /* NOTE: The branch occurs AFTER the next instruction has been
      executed */
@@ -547,6 +687,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -571,6 +713,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -592,6 +736,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -618,6 +764,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -641,6 +789,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -665,6 +815,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -687,12 +839,16 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
   check_branch_bug ();
+  if (RS == 31)
+    Unpredictable ();
   RA = (CIA + 8);
   /* NOTE: The branch occurs AFTER the next instruction has been
      executed */
@@ -711,12 +867,16 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
   check_branch_bug ();
+  if (RS == 31)
+    Unpredictable ();
   RA = (CIA + 8);
   if ((signed_word) GPR[RS] < 0)
     {
@@ -735,6 +895,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -761,6 +923,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -782,6 +946,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -806,6 +972,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -838,11 +1006,60 @@
 
 
 
+011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
+"clo r<RD>, r<RS>"
+*mips32:
+*mips64:
+{
+  unsigned32 temp = GPR[RS];
+  unsigned32 i, mask;
+  if (RT != RD)
+    Unpredictable ();
+  if (NotWordValue (GPR[RS]))
+    Unpredictable ();
+  TRACE_ALU_INPUT1 (GPR[RS]);
+  for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
+    {
+      if ((temp & mask) == 0)
+	break;
+      mask >>= 1;
+    }
+  GPR[RD] = EXTEND32 (i);
+  TRACE_ALU_RESULT (GPR[RD]);
+}
+
+
+
+011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
+"clz r<RD>, r<RS>"
+*mips32:
+*mips64:
+{
+  unsigned32 temp = GPR[RS];
+  unsigned32 i, mask;
+  if (RT != RD)
+    Unpredictable ();
+  if (NotWordValue (GPR[RS]))
+    Unpredictable ();
+  TRACE_ALU_INPUT1 (GPR[RS]);
+  for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
+    {
+      if ((temp & mask) != 0)
+	break;
+      mask >>= 1;
+    }
+  GPR[RD] = EXTEND32 (i);
+  TRACE_ALU_RESULT (GPR[RD]);
+}
+
+
+
 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
 "dadd r<RD>, r<RS>, r<RT>"
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -863,6 +1080,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -890,6 +1108,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -911,6 +1130,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -920,6 +1140,52 @@
 
 
 
+011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
+"dclo r<RD>, r<RS>"
+*mips64:
+{
+  unsigned64 temp = GPR[RS];
+  unsigned32 i;
+  unsigned64 mask;
+  check_u64 (SD_, instruction_0);
+  if (RT != RD)
+    Unpredictable ();
+  TRACE_ALU_INPUT1 (GPR[RS]);
+  for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
+    {
+      if ((temp & mask) == 0)
+	break;
+      mask >>= 1;
+    }
+  GPR[RD] = EXTEND32 (i);
+  TRACE_ALU_RESULT (GPR[RD]);
+}
+
+
+
+011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
+"dclz r<RD>, r<RS>"
+*mips64:
+{
+  unsigned64 temp = GPR[RS];
+  unsigned32 i;
+  unsigned64 mask;
+  check_u64 (SD_, instruction_0);
+  if (RT != RD)
+    Unpredictable ();
+  TRACE_ALU_INPUT1 (GPR[RS]);
+  for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
+    {
+      if ((temp & mask) != 0)
+	break;
+      mask >>= 1;
+    }
+  GPR[RD] = EXTEND32 (i);
+  TRACE_ALU_RESULT (GPR[RD]);
+}
+
+
+
 :function:::void:do_ddiv:int rs, int rt
 {
   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
@@ -955,6 +1221,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -994,6 +1261,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1036,6 +1304,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1073,6 +1343,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1152,6 +1424,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 {
   check_u64 (SD_, instruction_0);
@@ -1179,6 +1452,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 {
   check_u64 (SD_, instruction_0);
@@ -1206,6 +1480,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1219,6 +1494,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1242,6 +1518,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1262,6 +1539,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1275,6 +1553,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1299,6 +1578,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1319,6 +1599,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1332,6 +1613,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1358,6 +1640,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1371,6 +1654,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1397,6 +1681,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1412,6 +1697,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1430,6 +1717,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1449,6 +1738,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1466,6 +1757,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1591,6 +1884,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1606,6 +1901,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1619,6 +1916,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1633,6 +1931,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1648,6 +1948,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1661,6 +1962,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1676,6 +1978,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1691,6 +1995,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1705,6 +2011,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1745,6 +2053,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1781,6 +2090,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1798,6 +2109,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1813,6 +2126,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1828,6 +2143,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1843,6 +2160,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1856,6 +2175,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1864,6 +2184,44 @@
 }
 
 
+
+011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
+"madd r<RS>, r<RT>"
+*mips32:
+*mips64:
+{
+  signed64 temp;
+  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+  if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+    Unpredictable ();
+  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+  temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+          + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
+  LO = EXTEND32 (temp);
+  HI = EXTEND32 (VH4_8 (temp));
+  TRACE_ALU_RESULT2 (HI, LO);
+}
+
+
+
+011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
+"maddu r<RS>, r<RT>"
+*mips32:
+*mips64:
+{
+  unsigned64 temp;
+  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+  if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+    Unpredictable ();
+  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+  temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+          + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
+  LO = EXTEND32 (temp);
+  HI = EXTEND32 (VH4_8 (temp));
+  TRACE_ALU_RESULT2 (HI, LO);
+}
+
+
 :function:::void:do_mfhi:int rd
 {
   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
@@ -1879,6 +2237,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1903,6 +2263,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1916,10 +2278,15 @@
 "movn r<RD>, r<RS>, r<RT>"
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr5000:
 {
   if (GPR[RT] != 0)
-    GPR[RD] = GPR[RS];
+    {
+      GPR[RD] = GPR[RS];
+      TRACE_ALU_RESULT (GPR[RD]);
+    }
 }
 
 
@@ -1928,10 +2295,53 @@
 "movz r<RD>, r<RS>, r<RT>"
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr5000:
 {
   if (GPR[RT] == 0)
-    GPR[RD] = GPR[RS];
+    {
+      GPR[RD] = GPR[RS];
+      TRACE_ALU_RESULT (GPR[RD]);
+    }
+}
+
+
+
+011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
+"msub r<RS>, r<RT>"
+*mips32:
+*mips64:
+{
+  signed64 temp;
+  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+  if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+    Unpredictable ();
+  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+  temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+          - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
+  LO = EXTEND32 (temp);
+  HI = EXTEND32 (VH4_8 (temp));
+  TRACE_ALU_RESULT2 (HI, LO);
+}
+
+
+
+011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
+"msubu r<RS>, r<RT>"
+*mips32:
+*mips64:
+{
+  unsigned64 temp;
+  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+  if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+    Unpredictable ();
+  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+  temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+          - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
+  LO = EXTEND32 (temp);
+  HI = EXTEND32 (VH4_8 (temp));
+  TRACE_ALU_RESULT2 (HI, LO);
 }
 
 
@@ -1943,6 +2353,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1960,6 +2372,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1970,10 +2384,29 @@
 
 
 
+011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
+"mul r<RD>, r<RS>, r<RT>"
+*mips32:
+*mips64:
+{
+  signed64 prod;
+  if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+    Unpredictable ();
+  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+  prod = (((signed64)(signed32) GPR[RS])
+          * ((signed64)(signed32) GPR[RT]));
+  GPR[RD] = EXTEND32 (VL4_8 (prod));
+  TRACE_ALU_RESULT (GPR[RD]);
+}
+
+
+
 :function:::void:do_mult:int rs, int rt, int rd
 {
   signed64 prod;
   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+  if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
+    Unpredictable ();
   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
   prod = (((signed64)(signed32) GPR[rs])
 	  * ((signed64)(signed32) GPR[rt]));
@@ -1991,6 +2424,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 {
   do_mult (SD_, RS, RT, 0);
@@ -2011,6 +2446,8 @@
 {
   unsigned64 prod;
   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+  if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
+    Unpredictable ();
   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
   prod = (((unsigned64)(unsigned32) GPR[rs])
 	  * ((unsigned64)(unsigned32) GPR[rt]));
@@ -2028,6 +2465,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 {
   do_multu (SD_, RS, RT, 0);
@@ -2057,6 +2496,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2079,6 +2520,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2102,6 +2545,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2114,6 +2559,8 @@
 "pref <HINT>, <OFFSET>(r<BASE>)"
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr5000:
 {
   address_word base = GPR[BASE];
@@ -2227,6 +2674,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2241,6 +2690,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -2282,6 +2733,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -2319,6 +2771,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -2333,6 +2786,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -2345,6 +2800,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -2358,6 +2814,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -2373,6 +2830,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2389,7 +2848,7 @@
   TRACE_ALU_RESULT (GPR[rd]);
 }
 
-000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
+000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
 "nop":RD == 0 && RT == 0 && SHIFT == 0
 "sll r<RD>, r<RT>, <SHIFT>"
 *mipsI:
@@ -2407,6 +2866,19 @@
     do_sll (SD_, RT, RD, SHIFT);
 }
 
+000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
+"nop":RD == 0 && RT == 0 && SHIFT == 0
+"ssnop":RD == 0 && RT == 0 && SHIFT == 1
+"sll r<RD>, r<RT>, <SHIFT>"
+*mips32:
+*mips64:
+{
+  /* Skip shift for NOP and SSNOP, so that there won't be lots of
+     extraneous trace output.  */
+  if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
+    do_sll (SD_, RT, RD, SHIFT);
+}
+
 
 :function:::void:do_sllv:int rs, int rt, int rd
 {
@@ -2424,6 +2896,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2446,6 +2920,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2468,6 +2944,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2490,6 +2968,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2513,6 +2993,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2524,6 +3006,8 @@
 :function:::void:do_sra:int rt, int rd, int shift
 {
   signed32 temp = (signed32) GPR[rt] >> shift;
+  if (NotWordValue (GPR[rt]))
+    Unpredictable ();
   TRACE_ALU_INPUT2 (GPR[rt], shift);
   GPR[rd] = EXTEND32 (temp);
   TRACE_ALU_RESULT (GPR[rd]);
@@ -2536,6 +3020,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2549,6 +3035,8 @@
 {
   int s = MASKED (GPR[rs], 4, 0);
   signed32 temp = (signed32) GPR[rt] >> s;
+  if (NotWordValue (GPR[rt]))
+    Unpredictable ();
   TRACE_ALU_INPUT2 (GPR[rt], s);
   GPR[rd] = EXTEND32 (temp);
   TRACE_ALU_RESULT (GPR[rd]);
@@ -2561,6 +3049,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2573,6 +3063,8 @@
 :function:::void:do_srl:int rt, int rd, int shift
 {
   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
+  if (NotWordValue (GPR[rt]))
+    Unpredictable ();
   TRACE_ALU_INPUT2 (GPR[rt], shift);
   GPR[rd] = EXTEND32 (temp);
   TRACE_ALU_RESULT (GPR[rd]);
@@ -2585,6 +3077,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2597,6 +3091,8 @@
 {
   int s = MASKED (GPR[rs], 4, 0);
   unsigned32 temp = (unsigned32) GPR[rt] >> s;
+  if (NotWordValue (GPR[rt]))
+    Unpredictable ();
   TRACE_ALU_INPUT2 (GPR[rt], s);
   GPR[rd] = EXTEND32 (temp);
   TRACE_ALU_RESULT (GPR[rd]);
@@ -2609,6 +3105,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2624,10 +3122,14 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
+  if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+    Unpredictable ();
   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
   {
     ALU32_BEGIN (GPR[RS]);
@@ -2640,6 +3142,8 @@
 
 :function:::void:do_subu:int rs, int rt, int rd
 {
+  if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
+    Unpredictable ();
   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
   TRACE_ALU_RESULT (GPR[rd]);
@@ -2652,6 +3156,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2667,6 +3173,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *r3900:
 *vr5000:
@@ -2682,6 +3190,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2697,6 +3207,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2712,6 +3224,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2727,6 +3241,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2742,6 +3258,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2756,6 +3274,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -2770,6 +3290,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -2784,6 +3306,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -2798,6 +3322,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -2812,6 +3338,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -2826,6 +3354,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -2840,6 +3370,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -2854,6 +3386,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -2868,6 +3402,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -2882,6 +3418,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -2896,6 +3434,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -2905,11 +3445,13 @@
 
 
 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
-"tne r<RS>, <IMMEDIATE>"
+"tnei r<RS>, <IMMEDIATE>"
 *mipsII:
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -2932,6 +3474,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2954,6 +3498,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2977,16 +3523,7 @@
     case fmt_double: return "d";
     case fmt_word: return "w";
     case fmt_long: return "l";
-    default: return "?";
-    }
-}
-
-:%s::::X:int x
-{
-  switch (x)
-    {
-    case 0: return "f";
-    case 1: return "t";
+    case fmt_ps: return "ps";
     default: return "?";
     }
 }
@@ -3045,6 +3582,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3059,17 +3598,25 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
-*mipsV:
+*mips32:
 *vr4100:
 *vr5000:
 *r3900:
 {
   /* None of these ISAs support Paired Single, so just fall back to
      the single/double check.  */
-  /* XXX FIXME: not true for mipsV, but we don't support .ps insns yet.  */
   check_fmt (SD_, fmt, insn);
 }
 
+:function:::void:check_fmt_p:int fmt, instruction_word insn
+*mipsV:
+*mips64:
+{
+  if ((fmt != fmt_single) && (fmt != fmt_double)
+      && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
+    SignalException (ReservedInstruction, insn);
+}
+
 
 // Helper:
 //
@@ -3083,6 +3630,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3092,6 +3641,77 @@
 }
 
 
+// Helper:
+//
+// Load a double word FP value using 2 32-bit memory cycles a la MIPS II
+// or MIPS32.  do_load cannot be used instead because it returns an
+// unsigned_word, which is limited to the size of the machine's registers.
+//
+
+:function:::unsigned64:do_load_double:address_word base, address_word offset
+*mipsII:
+*mips32:
+{
+  int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
+  address_word vaddr;
+  address_word paddr;
+  int uncached;
+  unsigned64 memval;
+  unsigned64 v;
+
+  vaddr = loadstore_ea (SD_, base, offset);
+  if ((vaddr & AccessLength_DOUBLEWORD) != 0)
+    {
+      SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
+		       AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
+		       sim_core_unaligned_signal);
+    }
+  AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
+		      isREAL);
+  LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
+	      isDATA, isREAL);
+  v = (unsigned64)memval;
+  LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
+	      isDATA, isREAL);
+  return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
+}
+
+
+// Helper:
+//
+// Store a double word FP value using 2 32-bit memory cycles a la MIPS II
+// or MIPS32.  do_load cannot be used instead because it returns an
+// unsigned_word, which is limited to the size of the machine's registers.
+//
+
+:function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
+*mipsII:
+*mips32:
+{
+  int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
+  address_word vaddr;
+  address_word paddr;
+  int uncached;
+  unsigned64 memval;
+
+  vaddr = loadstore_ea (SD_, base, offset);
+  if ((vaddr & AccessLength_DOUBLEWORD) != 0)
+    {
+      SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
+		       AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
+		       sim_core_unaligned_signal);
+    }
+  AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
+		      isREAL);
+  memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
+  StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
+	       isREAL);
+  memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
+  StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
+	       isREAL);
+}
+
+
 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
 "abs.%s<FMT> f<FD>, f<FS>"
 *mipsI:
@@ -3099,6 +3719,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3106,7 +3728,7 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt_p (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt,AbsoluteValue(ValueFPR(FS,fmt),fmt));
+  StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt));
 }
 
 
@@ -3118,6 +3740,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3125,10 +3749,36 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt_p (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt,Add(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
+  StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
 }
 
 
+010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:64,f::ALNV.PS
+"alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
+*mipsV:
+*mips64:
+{
+  unsigned64 fs;
+  unsigned64 ft;
+  unsigned64 fd;
+  check_fpu (SD_);
+  check_u64 (SD_, instruction_0);
+  fs = ValueFPR (FS, fmt_ps);
+  if ((GPR[RS] & 0x3) != 0)
+    Unpredictable ();
+  if ((GPR[RS] & 0x4) == 0)
+    fd = fs;
+  else
+    {
+      ft = ValueFPR (FT, fmt_ps);
+      if (BigEndianCPU)
+	fd = PackPS (PSLower (fs), PSUpper (ft));
+      else
+	fd = PackPS (PSLower (ft), PSUpper (fs));
+    }
+  StoreFPR (FD, fmt_ps, fd);
+}
+
 
 // BC1F
 // BC1FL
@@ -3167,6 +3817,8 @@
 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 #*vr4100:
 *vr5000:
 *r3900:
@@ -3186,45 +3838,6 @@
 }
 
 
-
-
-
-
-// C.EQ.S
-// C.EQ.D
-// ...
-
-:function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
-{
-  int less;
-  int equal;
-  int unordered;
-  int condition;
-  unsigned64 ofs = ValueFPR (fs, fmt);
-  unsigned64 oft = ValueFPR (ft, fmt);
-  if (NaN (ofs, fmt) || NaN (oft, fmt))
-    {
-      if (FCSR & FP_ENABLE (IO))
-	{
-	  FCSR |= FP_CAUSE (IO);
-	  SignalExceptionFPE ();
-	}
-      less = 0;
-      equal = 0;
-      unordered = 1;
-    }
-  else
-    {
-      less = Less (ofs, oft, fmt);
-      equal = Equal (ofs, oft, fmt);
-      unordered = 0;
-    }
-  condition = (((cond & (1 << 2)) && less)
-	       || ((cond & (1 << 1)) && equal)
-	       || ((cond & (1 << 0)) && unordered));
-  SETFCC (cc, condition);
-}
-
 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
 *mipsI:
@@ -3234,7 +3847,8 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt_p (SD_, fmt, instruction_0);
-  do_c_cond_fmt (SD_, fmt, FT, FS, 0, COND, instruction_0);
+  Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
+  TRACE_ALU_RESULT (ValueFCR (31));
 }
 
 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
@@ -3242,6 +3856,8 @@
 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3249,7 +3865,8 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt_p (SD_, fmt, instruction_0);
-  do_c_cond_fmt (SD_, fmt, FT, FS, CC, COND, instruction_0);
+  Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
+  TRACE_ALU_RESULT (ValueFCR (31));
 }
 
 
@@ -3258,6 +3875,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3265,15 +3883,19 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(FS,fmt),fmt,fmt_long));
+  StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
+	    fmt_long));
 }
 
 
 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
+"ceil.w.%s<FMT> f<FD>, f<FS>"
 *mipsII:
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3281,82 +3903,97 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(FS,fmt),fmt,fmt_word));
+  StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
+	    fmt_word));
 }
 
 
-// CFC1
-// CTC1
-010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32,f::CxC1
-"c%s<X>c1 r<RT>, f<FS>"
+010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
+"cfc1 r<RT>, f<FS>"
 *mipsI:
 *mipsII:
 *mipsIII:
 {
   check_fpu (SD_);
-  if (X)
-    {
-      if (FS == 0)
-	PENDING_FILL(FCR0IDX,VL4_8(GPR[RT]));
-      else if (FS == 31)
-	PENDING_FILL(FCR31IDX,VL4_8(GPR[RT]));
-      /* else NOP */
-      PENDING_SCHED(FCSR, FCR31 & (1<<23), 1, 23);
-    }
-  else
-    { /* control from */
-      if (FS == 0)
- 	PENDING_FILL(RT, EXTEND32 (FCR0));
-      else if (FS == 31)
- 	PENDING_FILL(RT, EXTEND32 (FCR31));
-      /* else NOP */
-    }
+  if (FS == 0)
+    PENDING_FILL (RT, EXTEND32 (FCR0));
+  else if (FS == 31)
+    PENDING_FILL (RT, EXTEND32 (FCR31));
+  /* else NOP */
 }
-010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32,f::CxC1
-"c%s<X>c1 r<RT>, f<FS>"
+
+010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
+"cfc1 r<RT>, f<FS>"
 *mipsIV:
-*mipsV:
 *vr4100:
 *vr5000:
 *r3900:
 {
   check_fpu (SD_);
-  if (X)
+  if (FS == 0 || FS == 31)
     {
-      /* control to */
-      TRACE_ALU_INPUT1 (GPR[RT]);
-      if (FS == 0)
-	{
-	  FCR0 = VL4_8(GPR[RT]);
-	  TRACE_ALU_RESULT (FCR0);
-	}
-      else if (FS == 31)
-	{
-	  FCR31 = VL4_8(GPR[RT]);
-	  SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
-	  TRACE_ALU_RESULT (FCR31);
-	}
-      else
-	{
-	  TRACE_ALU_RESULT0 ();
-	}
-      /* else NOP */
+      unsigned_word  fcr = ValueFCR (FS);
+      TRACE_ALU_INPUT1 (fcr);
+      GPR[RT] = fcr;
     }
-  else
-    { /* control from */
-      if (FS == 0)
-	{
-	  TRACE_ALU_INPUT1 (FCR0);
-	  GPR[RT] = EXTEND32 (FCR0);
-	}
-      else if (FS == 31)
-	{
-	  TRACE_ALU_INPUT1 (FCR31);
-	  GPR[RT] = EXTEND32 (FCR31);
-	}
-      TRACE_ALU_RESULT (GPR[RT]);
-      /* else NOP */
+  /* else NOP */
+  TRACE_ALU_RESULT (GPR[RT]);
+}
+
+010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
+"cfc1 r<RT>, f<FS>"
+*mipsV:
+*mips32:
+*mips64:
+{
+  check_fpu (SD_);
+  if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
+    {
+      unsigned_word  fcr = ValueFCR (FS);
+      TRACE_ALU_INPUT1 (fcr);
+      GPR[RT] = fcr;
     }
+  /* else NOP */
+  TRACE_ALU_RESULT (GPR[RT]);
+}
+
+010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
+"ctc1 r<RT>, f<FS>"
+*mipsI:
+*mipsII:
+*mipsIII:
+{
+  check_fpu (SD_);
+  if (FS == 31)
+    PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
+  /* else NOP */
+}
+
+010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
+"ctc1 r<RT>, f<FS>"
+*mipsIV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+  check_fpu (SD_);
+  TRACE_ALU_INPUT1 (GPR[RT]);
+  if (FS == 31)
+    StoreFCR (FS, GPR[RT]);
+  /* else NOP */
+}
+
+010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
+"ctc1 r<RT>, f<FS>"
+*mipsV:
+*mips32:
+*mips64:
+{
+  check_fpu (SD_);
+  TRACE_ALU_INPUT1 (GPR[RT]);
+  if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
+      StoreFCR (FS, GPR[RT]);
+  /* else NOP */
 }
 
 
@@ -3370,18 +4007,18 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   int fmt = FMT;
   check_fpu (SD_);
-  {
-    if ((fmt == fmt_double) | 0)
-      SignalException (ReservedInstruction, instruction_0);
-    else
-      StoreFPR(FD,fmt_double,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_double));
-  }
+  if ((fmt == fmt_double) | 0)
+    SignalException (ReservedInstruction, instruction_0);
+  StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
+	    fmt_double));
 }
 
 
@@ -3390,65 +4027,98 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   int fmt = FMT;
   check_fpu (SD_);
-  {
-    if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
-      SignalException (ReservedInstruction, instruction_0);
-    else
-      StoreFPR(FD,fmt_long,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_long));
-  }
+  if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
+    SignalException (ReservedInstruction, instruction_0);
+  StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
+	    fmt_long));
+}
+
+
+010001,10,000,5.FT,5.FS,5.FD,100110:COP1:64,f::CVT.PS.S
+"cvt.ps.s f<FD>, f<FS>, f<FT>"
+*mipsV:
+*mips64:
+{
+  check_fpu (SD_);
+  check_u64 (SD_, instruction_0);
+  StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single),
+				ValueFPR (FT, fmt_single)));
 }
 
 
 //
 // FIXME: Does not correctly differentiate between mips*
 //
-010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
+010001,10,3.FMT!6,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
 "cvt.s.%s<FMT> f<FD>, f<FS>"
 *mipsI:
 *mipsII:
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   int fmt = FMT;
   check_fpu (SD_);
-  {
-    if ((fmt == fmt_single) | 0)
-      SignalException (ReservedInstruction, instruction_0);
-    else
-      StoreFPR(FD,fmt_single,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_single));
-  }
+  if ((fmt == fmt_single) | 0)
+    SignalException (ReservedInstruction, instruction_0);
+  StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
+	    fmt_single));
 }
 
 
-010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
+010001,10,110,00000,5.FS,5.FD,101000:COP1:64,f::CVT.S.PL
+"cvt.s.pl f<FD>, f<FS>"
+*mipsV:
+*mips64:
+{
+  check_fpu (SD_);
+  check_u64 (SD_, instruction_0);
+  StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps)));
+}
+
+
+010001,10,110,00000,5.FS,5.FD,100000:COP1:64,f::CVT.S.PU
+"cvt.s.pu f<FD>, f<FS>"
+*mipsV:
+*mips64:
+{
+  check_fpu (SD_);
+  check_u64 (SD_, instruction_0);
+  StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps)));
+}
+
+
+010001,10,3.FMT!6,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
 "cvt.w.%s<FMT> f<FD>, f<FS>"
 *mipsI:
 *mipsII:
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   int fmt = FMT;
   check_fpu (SD_);
-  {
-    if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
-      SignalException (ReservedInstruction, instruction_0);
-    else
-      StoreFPR(FD,fmt_word,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_word));
-  }
+  if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
+    SignalException (ReservedInstruction, instruction_0);
+  StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
+	    fmt_word));
 }
 
 
@@ -3459,6 +4129,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3466,76 +4138,84 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt,Divide(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
+  StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
 }
 
 
-// DMFC1
-// DMTC1
-010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64,f::DMxC1
-"dm%s<X>c1 r<RT>, f<FS>"
+010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
+"dmfc1 r<RT>, f<FS>"
 *mipsIII:
 {
+  unsigned64 v;
   check_fpu (SD_);
   check_u64 (SD_, instruction_0);
-  if (X)
-    {
-      if (SizeFGR() == 64)
-	PENDING_FILL((FS + FGRIDX),GPR[RT]);
-      else if ((FS & 0x1) == 0)
-	{
-	  PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
-	  PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
-	}
-    }
+  if (SizeFGR () == 64)
+    v = FGR[FS];
+  else if ((FS & 0x1) == 0)
+    v = SET64HI (FGR[FS+1]) | FGR[FS];
   else
-    {
-      if (SizeFGR() == 64)
-	PENDING_FILL(RT,FGR[FS]);
-      else if ((FS & 0x1) == 0)
-	PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
-      else
-	{
-	  if (STATE_VERBOSE_P(SD))
-	    sim_io_eprintf (SD,
-	      "Warning: PC 0x%lx: semantic_DMxC1_COP1Sa 32-bit use of odd FPR number\n",
-	      (long) CIA);
-	  PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
-	}
-    }
+    v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
+  PENDING_FILL (RT, v);
+  TRACE_ALU_RESULT (v);
 }
-010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64,f::DMxC1
-"dm%s<X>c1 r<RT>, f<FS>"
+
+010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
+"dmfc1 r<RT>, f<FS>"
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   check_fpu (SD_);
   check_u64 (SD_, instruction_0);
-  if (X)
-    {
-      if (SizeFGR() == 64)
-	StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
-      else if ((FS & 0x1) == 0)
-	StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
-    }
+  if (SizeFGR () == 64)
+    GPR[RT] = FGR[FS];
+  else if ((FS & 0x1) == 0)
+    GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
   else
+    GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
+  TRACE_ALU_RESULT (GPR[RT]);
+}
+
+
+010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
+"dmtc1 r<RT>, f<FS>"
+*mipsIII:
+{
+  unsigned64 v;
+  check_fpu (SD_);
+  check_u64 (SD_, instruction_0);
+  if (SizeFGR () == 64)
+    PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
+  else if ((FS & 0x1) == 0)
     {
-      if (SizeFGR() == 64)
-	GPR[RT] = FGR[FS];
-      else if ((FS & 0x1) == 0)
-	GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
-      else
-	{
-	  if (STATE_VERBOSE_P(SD))
-	    sim_io_eprintf (SD,
-	      "Warning: PC 0x%lx: DMxC1 32-bit use of odd FPR number\n",
-			    (long) CIA);
-	  GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
-	}
+      PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
+      PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
     }
+  else
+    Unpredictable ();
+  TRACE_FP_RESULT (GPR[RT]);
+}
+
+010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
+"dmtc1 r<RT>, f<FS>"
+*mipsIV:
+*mipsV:
+*mips64:
+*vr4100:
+*vr5000:
+*r3900:
+{
+  check_fpu (SD_);
+  check_u64 (SD_, instruction_0);
+  if (SizeFGR () == 64)
+    StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
+  else if ((FS & 0x1) == 0)
+    StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
+  else
+    Unpredictable ();
 }
 
 
@@ -3544,6 +4224,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3551,7 +4232,8 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(FS,fmt),fmt,fmt_long));
+  StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
+	    fmt_long));
 }
 
 
@@ -3561,6 +4243,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3568,16 +4252,27 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(FS,fmt),fmt,fmt_word));
+  StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
+	    fmt_word));
 }
 
 
-110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1
+110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
 *mipsII:
+*mips32:
+{
+  check_fpu (SD_);
+  COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
+}
+
+
+110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
+"ldc1 f<FT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3591,6 +4286,7 @@
 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
 *mipsIV:
 *mipsV:
+*mips64:
 *vr5000:
 {
   check_fpu (SD_);
@@ -3607,6 +4303,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3620,6 +4318,7 @@
 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
 *mipsIV:
 *mipsV:
+*mips64:
 *vr5000:
 {
   check_fpu (SD_);
@@ -3629,75 +4328,48 @@
 
 
 
-//
-// FIXME: Not correct for mips*
-//
-010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
-"madd.d f<FD>, f<FR>, f<FS>, f<FT>"
-*mipsIV:
-*mipsV:
-*vr5000:
-{
-  check_fpu (SD_);
-  {
-    StoreFPR(FD,fmt_double,Add(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double));
-  }
-}
-
-
-010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
-"madd.s f<FD>, f<FR>, f<FS>, f<FT>"
+010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT:COP1X:64,f::MADD.fmt
+"madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
 *mipsV:
+*mips64:
 *vr5000:
 {
+  int fmt = FMT;
   check_fpu (SD_);
-  {
-    StoreFPR(FD,fmt_single,Add(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single));
-  }
+  check_u64 (SD_, instruction_0);
+  check_fmt_p (SD_, fmt, instruction_0); 
+  StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
+				  ValueFPR (FR, fmt), fmt));
 }
 
 
-// MFC1
-// MTC1
-010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32,f::MxC1
-"m%s<X>c1 r<RT>, f<FS>"
+010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
+"mfc1 r<RT>, f<FS>"
 *mipsI:
 *mipsII:
 *mipsIII:
 {
+  unsigned64 v;
   check_fpu (SD_);
-  if (X)
-    { /*MTC1*/
-      if (SizeFGR() == 64)
-	{
-	  if (STATE_VERBOSE_P(SD))
-	    sim_io_eprintf (SD,
-			    "Warning:  PC 0x%lx: MTC1 not DMTC1 with 64 bit regs\n",
-			    (long) CIA);
-	  PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
-	}
-      else
-	PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
-    }
-  else /*MFC1*/
-    PENDING_FILL (RT, EXTEND32 (FGR[FS]));
+  v = EXTEND32 (FGR[FS]);
+  PENDING_FILL (RT, v);
+  TRACE_ALU_RESULT (v);
 }
-010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32,f::MxC1
-"m%s<X>c1 r<RT>, f<FS>"
+  
+010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
+"mfc1 r<RT>, f<FS>"
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
-{
-  int fs = FS;
+{ 
   check_fpu (SD_);
-  if (X)
-    /*MTC1*/
-    StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
-  else /*MFC1*/
-    GPR[RT] = EXTEND32 (FGR[FS]);
+  GPR[RT] = EXTEND32 (FGR[FS]);
+  TRACE_ALU_RESULT (GPR[RT]);
 }
 
 
@@ -3708,6 +4380,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3715,7 +4389,7 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt_p (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt,ValueFPR(FS,fmt));
+  StoreFPR (FD, fmt, ValueFPR (FS, fmt));
 }
 
 
@@ -3725,6 +4399,8 @@
 "mov%s<TF> r<RD>, r<RS>, <CC>"
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr5000:
 {
   check_fpu (SD_);
@@ -3739,16 +4415,28 @@
 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr5000:
 {
   int fmt = FMT;
   check_fpu (SD_);
-  {
-   if (GETFCC(CC) == TF)
-     StoreFPR (FD, fmt, ValueFPR (FS, fmt));
-   else
-     StoreFPR (FD, fmt, ValueFPR (FD, fmt));
-  }
+  if (fmt != fmt_ps)
+    {
+      if (GETFCC(CC) == TF)
+	StoreFPR (FD, fmt, ValueFPR (FS, fmt));
+      else
+	StoreFPR (FD, fmt, ValueFPR (FD, fmt));   /* set fmt */
+    }
+  else
+    {
+      unsigned64 fd;
+      fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD,
+				      fmt_ps)),
+		   PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD,
+				      fmt_ps)));
+      StoreFPR (FD, fmt_ps, fd);
+    }
 }
 
 
@@ -3756,6 +4444,8 @@
 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr5000:
 {
   check_fpu (SD_);
@@ -3777,6 +4467,8 @@
 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr5000:
 {
   check_fpu (SD_);
@@ -3787,33 +4479,51 @@
 }
 
 
-// MSUB.fmt
-010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32,f::MSUB.D
-"msub.d f<FD>, f<FR>, f<FS>, f<FT>"
+010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT:COP1X:64,f::MSUB.fmt
+"msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
 *mipsV:
+*mips64:
 *vr5000:
 {
+  int fmt = FMT;
   check_fpu (SD_);
-  StoreFPR(FD,fmt_double,Sub(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double));
+  check_u64 (SD_, instruction_0);
+  check_fmt_p (SD_, fmt, instruction_0);
+  StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
+				  ValueFPR (FR, fmt), fmt));
 }
 
 
-// MSUB.fmt
-010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32,f::MSUB.S
-"msub.s f<FD>, f<FR>, f<FS>, f<FT>"
+010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
+"mtc1 r<RT>, f<FS>"
+*mipsI:
+*mipsII:
+*mipsIII:
+{ 
+  check_fpu (SD_);
+  if (SizeFGR () == 64)
+    PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
+  else
+    PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
+  TRACE_FP_RESULT (GPR[RT]);
+} 
+
+010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
+"mtc1 r<RT>, f<FS>"
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
+*vr4100:
 *vr5000:
+*r3900:
 {
-  check_fpu (SD_);
-  StoreFPR(FD,fmt_single,Sub(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single));
+  check_fpu (SD_); 
+  StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
 }
 
 
-// MTC1 see MxC1
-
-
 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
 *mipsI:
@@ -3821,6 +4531,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3828,7 +4540,7 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt_p (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt,Multiply(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
+  StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
 }
 
 
@@ -3839,6 +4551,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3846,55 +4560,63 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt_p (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt,Negate(ValueFPR(FS,fmt),fmt));
+  StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt));
 }
 
 
-// NMADD.fmt
-010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32,f::NMADD.D
-"nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
+010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT:COP1X:64,f::NMADD.fmt
+"nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
 *mipsV:
+*mips64:
 *vr5000:
 {
+  int fmt = FMT;
   check_fpu (SD_);
-  StoreFPR(FD,fmt_double,Negate(Add(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double),fmt_double));
+  check_u64 (SD_, instruction_0);
+  check_fmt_p (SD_, fmt, instruction_0);
+  StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
+				     ValueFPR (FR, fmt), fmt));
 }
 
 
-// NMADD.fmt
-010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32,f::NMADD.S
-"nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
+010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT:COP1X:64,f::NMSUB.fmt
+"nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
 *mipsV:
+*mips64:
 *vr5000:
 {
+  int fmt = FMT;
   check_fpu (SD_);
-  StoreFPR(FD,fmt_single,Negate(Add(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single),fmt_single));
+  check_u64 (SD_, instruction_0);
+  check_fmt_p (SD_, fmt, instruction_0);
+  StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
+				     ValueFPR (FR, fmt), fmt));
 }
 
 
-// NMSUB.fmt
-010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32,f::NMSUB.D
-"nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
-*mipsIV:
+010001,10,110,5.FT,5.FS,5.FD,101100:COP1:64,f::PLL.PS
+"pll.ps f<FD>, f<FS>, f<FT>"
 *mipsV:
-*vr5000:
+*mips64:
 {
   check_fpu (SD_);
-  StoreFPR(FD,fmt_double,Negate(Sub(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double),fmt_double));
+  check_u64 (SD_, instruction_0);
+  StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
+				PSLower (ValueFPR (FT, fmt_ps))));
 }
 
 
-// NMSUB.fmt
-010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32,f::NMSUB.S
-"nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
-*mipsIV:
+010001,10,110,5.FT,5.FS,5.FD,101101:COP1:64,f::PLU.PS
+"plu.ps f<FD>, f<FS>, f<FT>"
 *mipsV:
-*vr5000:
+*mips64:
 {
   check_fpu (SD_);
-  StoreFPR(FD,fmt_single,Negate(Sub(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single),fmt_single));
+  check_u64 (SD_, instruction_0);
+  StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
+				PSUpper (ValueFPR (FT, fmt_ps))));
 }
 
 
@@ -3902,6 +4624,7 @@
 "prefx <HINT>, r<INDEX>(r<BASE>)"
 *mipsIV:
 *mipsV:
+*mips64:
 *vr5000:
 {
   address_word base = GPR[BASE];
@@ -3915,16 +4638,42 @@
   }
 }
 
+
+010001,10,110,5.FT,5.FS,5.FD,101110:COP1:64,f::PUL.PS
+"pul.ps f<FD>, f<FS>, f<FT>"
+*mipsV:
+*mips64:
+{
+  check_fpu (SD_);
+  check_u64 (SD_, instruction_0);
+  StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
+				PSLower (ValueFPR (FT, fmt_ps))));
+}
+
+
+010001,10,110,5.FT,5.FS,5.FD,101111:COP1:64,f::PUU.PS
+"puu.ps f<FD>, f<FS>, f<FT>"
+*mipsV:
+*mips64:
+{
+  check_fpu (SD_);
+  check_u64 (SD_, instruction_0);
+  StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
+				PSUpper (ValueFPR (FT, fmt_ps))));
+}
+
+
 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
 "recip.%s<FMT> f<FD>, f<FS>"
 *mipsIV:
 *mipsV:
+*mips64:
 *vr5000:
 {
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt,Recip(ValueFPR(FS,fmt),fmt));
+  StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
 }
 
 
@@ -3933,6 +4682,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3940,7 +4690,8 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(FS,fmt),fmt,fmt_long));
+  StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
+	    fmt_long));
 }
 
 
@@ -3950,6 +4701,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3957,29 +4710,41 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(FS,fmt),fmt,fmt_word));
+  StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
+	    fmt_word));
 }
 
 
 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
+"rsqrt.%s<FMT> f<FD>, f<FS>"
 *mipsIV:
 *mipsV:
-"rsqrt.%s<FMT> f<FD>, f<FS>"
+*mips64:
 *vr5000:
 {
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt,Recip(SquareRoot(ValueFPR(FS,fmt),fmt),fmt));
+  StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
 }
 
 
-111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1
+111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
 *mipsII:
+*mips32:
+{
+  check_fpu (SD_);
+  do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
+}
+
+
+111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
+"sdc1 f<FT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3993,6 +4758,7 @@
 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
 *mipsIV:
 *mipsV:
+*mips64:
 *vr5000:
 {
   check_fpu (SD_);
@@ -4007,6 +4773,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -4014,7 +4782,7 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt,(SquareRoot(ValueFPR(FS,fmt),fmt)));
+  StoreFPR (FD, fmt,  (SquareRoot (ValueFPR (FS, fmt), fmt)));
 }
 
 
@@ -4025,6 +4793,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -4032,7 +4802,7 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt_p (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt,Sub(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
+  StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
 }
 
 
@@ -4044,6 +4814,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -4083,6 +4855,7 @@
 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
 *mipsIV:
 *mipsV:
+*mips64:
 *vr5000:
 {
 
@@ -4123,6 +4896,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -4130,7 +4904,8 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(FS,fmt),fmt,fmt_long));
+  StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
+	    fmt_long));
 }
 
 
@@ -4140,6 +4915,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -4147,7 +4924,8 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(FS,fmt),fmt,fmt_word));
+  StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
+	    fmt_word));
 }
 
 
@@ -4165,6 +4943,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 
@@ -4184,6 +4964,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 
@@ -4195,6 +4977,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 
 
@@ -4205,6 +4989,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 
@@ -4214,6 +5000,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -4246,6 +5034,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 {
   check_u64 (SD_, instruction_0);
   DecodeCoproc (instruction_0);
@@ -4257,6 +5046,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 {
   check_u64 (SD_, instruction_0);
   DecodeCoproc (instruction_0);
@@ -4270,6 +5060,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 
@@ -4279,6 +5070,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -4304,6 +5097,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -4320,6 +5115,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -4350,6 +5147,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *r3900:
 {
@@ -4365,6 +5164,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 
@@ -4376,6 +5177,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 
@@ -4387,6 +5190,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 
@@ -4398,11 +5203,16 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 
 
 :include:::m16.igen
+:include:::mdmx.igen
+:include:::mips3d.igen
+:include:::sb1.igen
 :include:::tx.igen
 :include:::vr.igen