X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fmips%2Fmips.igen;h=4e895a10af2cbc224c0a233fa4308016fbdd5085;hb=d18ea9c2b8718a95042a2704f4568100cfdd828d;hp=646b78af4d2e56e9fe2b8c7ff9df5707193c72aa;hpb=63be8febf762353b62e794963fdc65f1280a7498;p=deliverable%2Fbinutils-gdb.git diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index 646b78af4d..4e895a10af 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -1,3 +1,5 @@ +// -*- C -*- +// // ::= // { "+" } // ":" @@ -12,14 +14,14 @@ // IGEN config - mips16 -:option:16::insn-bit-size:16 -:option:16::hi-bit-nr:15 +// :option:16::insn-bit-size:16 +// :option:16::hi-bit-nr:15 :option:16::insn-specifying-widths:true :option:16::gen-delayed-branch:false // IGEN config - mips32/64.. -:option:32::insn-bit-size:32 -:option:32::hi-bit-nr:31 +// :option:32::insn-bit-size:32 +// :option:32::hi-bit-nr:31 :option:32::insn-specifying-widths:true :option:32::gen-delayed-branch:false @@ -28,778 +30,1259 @@ // :option:::multi-sim:true -// Models known by this simulator -:model:::mipsI:mipsI: -:model:::mipsII:mipsII: -:model:::mipsIII:mipsIII: -:model:::mipsIV:mipsIV: -:model:::mips16:mips16: -// start-sanitize-r5900 -:model:::r5900:r5900: -// end-sanitize-r5900 -:model:::r3900:r3900: -// start-sanitize-tx19 -:model:::tx19:tx19: -// end-sanitize-tx19 -// start-sanitize-vr5400 -:model:::vr5400:vr5400: -// end-sanitize-vr5400 +// Models known by this simulator are defined below. +// +// When placing models in the instruction descriptions, please place +// them one per line, in the order given here. + +// MIPS ISAs: +// +// Instructions and related functions for these models are included in +// this file. +:model:::mipsI:mips3000: +:model:::mipsII:mips6000: +:model:::mipsIII:mips4000: +:model:::mipsIV:mips8000: +:model:::mipsV:mipsisaV: +:model:::mips32:mipsisa32: +:model:::mips64:mipsisa64: + +// Vendor ISAs: +// +// Standard MIPS ISA instructions used for these models are listed here, +// as are functions needed by those standard instructions. Instructions +// which are model-dependent and which are not in the standard MIPS ISAs +// (or which pre-date or use different encodings than the standard +// instructions) are (for the most part) in separate .igen files. +:model:::vr4100:mips4100: // vr.igen +:model:::vr5000:mips5000: +:model:::r3900:mips3900: // tx.igen + +// MIPS Application Specific Extensions (ASEs) +// +// Instructions for the ASEs are in separate .igen files. +// ASEs add instructions on to a base ISA. +:model:::mips16:mips16: // m16.igen (and m16.dc) +:model:::mdmx:mdmx: // mdmx.igen +// Vendor Extensions +// +// Instructions specific to these extensions are in separate .igen files. +// Extensions add instructions on to a base ISA. +:model:::sb1:sb1: // sb1.igen // Pseudo instructions known by IGEN :internal::::illegal: { - sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n", - (unsigned long) CIA); - sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGILL); + SignalException (ReservedInstruction, 0); +} + + +// Pseudo instructions known by interp.c +// For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK +000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD +"rsvd " +{ + SignalException (ReservedInstruction, instruction_0); +} + + + +// Helper: +// +// Simulate a 32 bit delayslot instruction +// + +:function:::address_word:delayslot32:address_word target +{ + instruction_word delay_insn; + sim_events_slip (SD, 1); + DSPC = CIA; + CIA = CIA + 4; /* NOTE not mips16 */ + STATE |= simDELAYSLOT; + delay_insn = IMEM32 (CIA); /* NOTE not mips16 */ + ENGINE_ISSUE_PREFIX_HOOK(); + idecode_issue (CPU_, delay_insn, (CIA)); + STATE &= ~simDELAYSLOT; + return target; +} + +:function:::address_word:nullify_next_insn32: +{ + sim_events_slip (SD, 1); + dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction"); + return CIA + 8; +} + + +// Helper: +// +// Calculate an effective address given a base and an offset. +// + +:function:::address_word:loadstore_ea:address_word base, address_word offset +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*vr4100: +*vr5000: +*r3900: +{ + return base + offset; +} + +:function:::address_word:loadstore_ea:address_word base, address_word offset +*mips64: +{ +#if 0 /* XXX FIXME: enable this only after some additional testing. */ + /* If in user mode and UX is not set, use 32-bit compatibility effective + address computations as defined in the MIPS64 Architecture for + Programmers Volume III, Revision 0.95, section 4.9. */ + if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX)) + == (ksu_user << status_KSU_shift)) + return (address_word)((signed32)base + (signed32)offset); +#endif + return base + offset; +} + + +// Helper: +// +// Check that a 32-bit register value is properly sign-extended. +// (See NotWordValue in ISA spec.) +// + +:function:::int:not_word_value:unsigned_word value +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*vr4100: +*vr5000: +*r3900: +{ + /* For historical simulator compatibility (until documentation is + found that makes these operations unpredictable on some of these + architectures), this check never returns true. */ + return 0; +} + +:function:::int:not_word_value:unsigned_word value +*mips32: +{ + /* On MIPS32, since registers are 32-bits, there's no check to be done. */ + return 0; +} + +:function:::int:not_word_value:unsigned_word value +*mips64: +{ + return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0)); +} + + +// Helper: +// +// Handle UNPREDICTABLE operation behaviour. The goal here is to prevent +// theoretically portable code which invokes non-portable behaviour from +// running with no indication of the portability issue. +// (See definition of UNPREDICTABLE in ISA spec.) +// + +:function:::void:unpredictable: +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*vr4100: +*vr5000: +*r3900: +{ +} + +:function:::void:unpredictable: +*mips32: +*mips64: +{ + unpredictable_action (CPU, CIA); +} + + +// Helper: +// +// Check that an access to a HI/LO register meets timing requirements +// +// The following requirements exist: +// +// - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read +// - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read +// - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update +// corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}. +// + +:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new +{ + if (history->mf.timestamp + 3 > time) + { + sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n", + itable[MY_INDEX].name, + new, (long) CIA, + (long) history->mf.cia); + return 0; + } + return 1; +} + +:function:::int:check_mt_hilo:hilo_history *history +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*vr4100: +*vr5000: +{ + signed64 time = sim_events_time (SD); + int ok = check_mf_cycles (SD_, history, time, "MT"); + history->mt.timestamp = time; + history->mt.cia = CIA; + return ok; +} + +:function:::int:check_mt_hilo:hilo_history *history +*mips32: +*mips64: +*r3900: +{ + signed64 time = sim_events_time (SD); + history->mt.timestamp = time; + history->mt.cia = CIA; + return 1; +} + + +:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: +*r3900: +{ + signed64 time = sim_events_time (SD); + int ok = 1; + if (peer != NULL + && peer->mt.timestamp > history->op.timestamp + && history->mt.timestamp < history->op.timestamp + && ! (history->mf.timestamp > history->op.timestamp + && history->mf.timestamp < peer->mt.timestamp) + && ! (peer->mf.timestamp > history->op.timestamp + && peer->mf.timestamp < peer->mt.timestamp)) + { + /* The peer has been written to since the last OP yet we have + not */ + sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n", + itable[MY_INDEX].name, + (long) CIA, + (long) history->op.cia, + (long) peer->mt.cia); + ok = 0; + } + history->mf.timestamp = time; + history->mf.cia = CIA; + return ok; +} + + + +:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*vr4100: +*vr5000: +{ + signed64 time = sim_events_time (SD); + int ok = (check_mf_cycles (SD_, hi, time, "OP") + && check_mf_cycles (SD_, lo, time, "OP")); + hi->op.timestamp = time; + lo->op.timestamp = time; + hi->op.cia = CIA; + lo->op.cia = CIA; + return ok; +} + +// The r3900 mult and multu insns _can_ be exectuted immediatly after +// a mf{hi,lo} +:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo +*mips32: +*mips64: +*r3900: +{ + /* FIXME: could record the fact that a stall occured if we want */ + signed64 time = sim_events_time (SD); + hi->op.timestamp = time; + lo->op.timestamp = time; + hi->op.cia = CIA; + lo->op.cia = CIA; + return 1; +} + + +:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: +*r3900: +{ + signed64 time = sim_events_time (SD); + int ok = (check_mf_cycles (SD_, hi, time, "OP") + && check_mf_cycles (SD_, lo, time, "OP")); + hi->op.timestamp = time; + lo->op.timestamp = time; + hi->op.cia = CIA; + lo->op.cia = CIA; + return ok; +} + + +// Helper: +// +// Check that the 64-bit instruction can currently be used, and signal +// a ReservedInstruction exception if not. +// + +:function:::void:check_u64:instruction_word insn +*mipsIII: +*mipsIV: +*mipsV: +*vr4100: +*vr5000: +{ + // The check should be similar to mips64 for any with PX/UX bit equivalents. } +:function:::void:check_u64:instruction_word insn +*mips64: +{ +#if 0 /* XXX FIXME: enable this only after some additional testing. */ + if (UserMode && (SR & (status_UX|status_PX)) == 0) + SignalException (ReservedInstruction, insn); +#endif +} // // MIPS Architecture: // -// CPU Instruction Set (mipsI - mipsIV) +// CPU Instruction Set (mipsI - mipsV, mips32, mips64) // + 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD "add r, r, r" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - ALU32_BEGIN (GPR[RS]); - ALU32_ADD (GPR[RT]); - ALU32_END (GPR[RD]); + if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + { + ALU32_BEGIN (GPR[RS]); + ALU32_ADD (GPR[RT]); + ALU32_END (GPR[RD]); /* This checks for overflow. */ + } + TRACE_ALU_RESULT (GPR[RD]); } + 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI -"addi r, r, IMMEDIATE" +"addi r, r, " *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - ALU32_BEGIN (GPR[RS]); - ALU32_ADD (EXTEND16 (IMMEDIATE)); - ALU32_END (GPR[RT]); + if (NotWordValue (GPR[RS])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE)); + { + ALU32_BEGIN (GPR[RS]); + ALU32_ADD (EXTEND16 (IMMEDIATE)); + ALU32_END (GPR[RT]); /* This checks for overflow. */ + } + TRACE_ALU_RESULT (GPR[RT]); } + +:function:::void:do_addiu:int rs, int rt, unsigned16 immediate +{ + if (NotWordValue (GPR[rs])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); + GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate)); + TRACE_ALU_RESULT (GPR[rt]); +} + 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU -"add r, r, IMMEDIATE" +"addiu r, r, " *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - signed32 temp = GPR[RS] + EXTEND16 (IMMEDIATE); - GPR[RT] = EXTEND32 (temp); + do_addiu (SD_, RS, RT, IMMEDIATE); } + +:function:::void:do_addu:int rs, int rt, int rd +{ + if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]); + TRACE_ALU_RESULT (GPR[rd]); +} + 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU +"addu r, r, r" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - signed32 temp = GPR[RS] + GPR[RT]; - GPR[RD] = EXTEND32 (temp); + do_addu (SD_, RS, RT, RD); } + +:function:::void:do_and:int rs, int rt, int rd +{ + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + GPR[rd] = GPR[rs] & GPR[rt]; + TRACE_ALU_RESULT (GPR[rd]); +} + 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND "and r, r, r" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - GPR[RD] = GPR[RS] & GPR[RT]; + do_and (SD_, RS, RT, RD); } + 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI -"and r, r, IMMEDIATE" +"andi r, r, %#lx" *mipsI: *mipsII: *mipsIII: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsIV: +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { + TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE); GPR[RT] = GPR[RS] & IMMEDIATE; + TRACE_ALU_RESULT (GPR[RT]); } + 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ -"beq r, r, OFFSET" +"beq r, r, " *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { address_word offset = EXTEND16 (OFFSET) << 2; - if (GPR[RS] == GPR[RT]) - DELAY_SLOT (PC + offset); + check_branch_bug (); + if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) + { + mark_branch_bug (NIA+offset); + DELAY_SLOT (NIA + offset); + } } + 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL "beql r, r, " *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { address_word offset = EXTEND16 (OFFSET) << 2; - if (GPR[RS] == GPR[RT]) - DELAY_SLOT (PC + offset); + check_branch_bug (); + if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) + { + mark_branch_bug (NIA+offset); + DELAY_SLOT (NIA + offset); + } else NULLIFY_NEXT_INSTRUCTION (); } + 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ "bgez r, " *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { address_word offset = EXTEND16 (OFFSET) << 2; - if (GPR[RS] >= 0) - DELAY_SLOT (PC + offset); + check_branch_bug (); + if ((signed_word) GPR[RS] >= 0) + { + mark_branch_bug (NIA+offset); + DELAY_SLOT (NIA + offset); + } } + 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL "bgezal r, " *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { address_word offset = EXTEND16 (OFFSET) << 2; + check_branch_bug (); + if (RS == 31) + Unpredictable (); RA = (CIA + 8); - if (GPR[RS] >= 0) - DELAY_SLOT (PC + offset); + if ((signed_word) GPR[RS] >= 0) + { + mark_branch_bug (NIA+offset); + DELAY_SLOT (NIA + offset); + } } + 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL "bgezall r, " *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { address_word offset = EXTEND16 (OFFSET) << 2; + check_branch_bug (); + if (RS == 31) + Unpredictable (); RA = (CIA + 8); /* NOTE: The branch occurs AFTER the next instruction has been executed */ - if (GPR[RS] >= 0) - DELAY_SLOT (PC + offset); + if ((signed_word) GPR[RS] >= 0) + { + mark_branch_bug (NIA+offset); + DELAY_SLOT (NIA + offset); + } else NULLIFY_NEXT_INSTRUCTION (); } + 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL "bgezl r, " *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { address_word offset = EXTEND16 (OFFSET) << 2; - if (GPR[RS] >= 0) - DELAY_SLOT (PC + offset); + check_branch_bug (); + if ((signed_word) GPR[RS] >= 0) + { + mark_branch_bug (NIA+offset); + DELAY_SLOT (NIA + offset); + } else NULLIFY_NEXT_INSTRUCTION (); } + 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ "bgtz r, " *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { address_word offset = EXTEND16 (OFFSET) << 2; - if (GPR[RS] > 0) - DELAY_SLOT (PC + offset); + check_branch_bug (); + if ((signed_word) GPR[RS] > 0) + { + mark_branch_bug (NIA+offset); + DELAY_SLOT (NIA + offset); + } } + 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL "bgtzl r, " *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { address_word offset = EXTEND16 (OFFSET) << 2; + check_branch_bug (); /* NOTE: The branch occurs AFTER the next instruction has been executed */ - if (GPR[RS] > 0) - DELAY_SLOT (PC + offset); + if ((signed_word) GPR[RS] > 0) + { + mark_branch_bug (NIA+offset); + DELAY_SLOT (NIA + offset); + } else NULLIFY_NEXT_INSTRUCTION (); } + 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ "blez r, " *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { address_word offset = EXTEND16 (OFFSET) << 2; + check_branch_bug (); /* NOTE: The branch occurs AFTER the next instruction has been executed */ - if (GPR[RS] <= 0) - DELAY_SLOT (PC + offset); + if ((signed_word) GPR[RS] <= 0) + { + mark_branch_bug (NIA+offset); + DELAY_SLOT (NIA + offset); + } } + 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL "bgezl r, " *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { address_word offset = EXTEND16 (OFFSET) << 2; - if (GPR[RS] <= 0) - DELAY_SLOT (PC + offset); + check_branch_bug (); + if ((signed_word) GPR[RS] <= 0) + { + mark_branch_bug (NIA+offset); + DELAY_SLOT (NIA + offset); + } else NULLIFY_NEXT_INSTRUCTION (); } + 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ "bltz r, " *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { address_word offset = EXTEND16 (OFFSET) << 2; - if (GPR[RS] < 0) - DELAY_SLOT (PC + offset); + check_branch_bug (); + if ((signed_word) GPR[RS] < 0) + { + mark_branch_bug (NIA+offset); + DELAY_SLOT (NIA + offset); + } } + 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL "bltzal r, " *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { address_word offset = EXTEND16 (OFFSET) << 2; + check_branch_bug (); + if (RS == 31) + Unpredictable (); RA = (CIA + 8); /* NOTE: The branch occurs AFTER the next instruction has been executed */ - if (GPR[RS] < 0) - DELAY_SLOT (PC + offset); + if ((signed_word) GPR[RS] < 0) + { + mark_branch_bug (NIA+offset); + DELAY_SLOT (NIA + offset); + } } + 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL "bltzall r, " *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { address_word offset = EXTEND16 (OFFSET) << 2; + check_branch_bug (); + if (RS == 31) + Unpredictable (); RA = (CIA + 8); - if (GPR[RS] < 0) - DELAY_SLOT (PC + offset); + if ((signed_word) GPR[RS] < 0) + { + mark_branch_bug (NIA+offset); + DELAY_SLOT (NIA + offset); + } else NULLIFY_NEXT_INSTRUCTION (); } + 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL "bltzl r, " *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { address_word offset = EXTEND16 (OFFSET) << 2; + check_branch_bug (); /* NOTE: The branch occurs AFTER the next instruction has been executed */ - if (GPR[RS] < 0) - DELAY_SLOT (PC + offset); + if ((signed_word) GPR[RS] < 0) + { + mark_branch_bug (NIA+offset); + DELAY_SLOT (NIA + offset); + } else NULLIFY_NEXT_INSTRUCTION (); } + 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE "bne r, r, " *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { address_word offset = EXTEND16 (OFFSET) << 2; - if (GPR[RS] != GPR[RT]) - DELAY_SLOT (PC + offset); + check_branch_bug (); + if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) + { + mark_branch_bug (NIA+offset); + DELAY_SLOT (NIA + offset); + } } + 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL "bnel r, r, " *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { address_word offset = EXTEND16 (OFFSET) << 2; - if (GPR[RS] != GPR[RT]) - DELAY_SLOT (PC + offset); + check_branch_bug (); + if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) + { + mark_branch_bug (NIA+offset); + DELAY_SLOT (NIA + offset); + } else NULLIFY_NEXT_INSTRUCTION (); } + 000000,20.CODE,001101:SPECIAL:32::BREAK -"break" +"break %#lx" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - SignalException(BreakPoint, instruction_0); + /* Check for some break instruction which are reserved for use by the simulator. */ + unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK; + if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) || + break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK)) + { + sim_engine_halt (SD, CPU, NULL, cia, + sim_exited, (unsigned int)(A0 & 0xFFFFFFFF)); + } + else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) || + break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK)) + { + if (STATE & simDELAYSLOT) + PC = cia - 4; /* reference the branch instruction */ + else + PC = cia; + SignalException (BreakPoint, instruction_0); + } + + else + { + /* If we get this far, we're not an instruction reserved by the sim. Raise + the exception. */ + SignalException (BreakPoint, instruction_0); + } } -0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz -"cop " -*mipsI: -*mipsII: -*mipsIII: -*mipsIV: -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 + +011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO +"clo r, r" +*mips32: +*mips64: { - DecodeCoproc (instruction_0); + unsigned32 temp = GPR[RS]; + unsigned32 i, mask; + if (RT != RD) + Unpredictable (); + if (NotWordValue (GPR[RS])) + Unpredictable (); + TRACE_ALU_INPUT1 (GPR[RS]); + for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i) + { + if ((temp & mask) == 0) + break; + mask >>= 1; + } + GPR[RD] = EXTEND32 (i); + TRACE_ALU_RESULT (GPR[RD]); +} + + + +011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ +"clz r, r" +*mips32: +*mips64: +{ + unsigned32 temp = GPR[RS]; + unsigned32 i, mask; + if (RT != RD) + Unpredictable (); + if (NotWordValue (GPR[RS])) + Unpredictable (); + TRACE_ALU_INPUT1 (GPR[RS]); + for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i) + { + if ((temp & mask) != 0) + break; + mask >>= 1; + } + GPR[RD] = EXTEND32 (i); + TRACE_ALU_RESULT (GPR[RD]); } + 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD "dadd r, r, r" *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: +*vr5000: { - ALU64_BEGIN (GPR[RS]); - ALU64_ADD (GPR[RT]); - ALU64_END (GPR[RT]); + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + { + ALU64_BEGIN (GPR[RS]); + ALU64_ADD (GPR[RT]); + ALU64_END (GPR[RD]); /* This checks for overflow. */ + } + TRACE_ALU_RESULT (GPR[RD]); } + 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI "daddi r, r, " *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: +*vr5000: { - ALU64_BEGIN (GPR[RS]); - ALU64_ADD (EXTEND16 (IMMEDIATE)); - ALU64_END (GPR[RT]); + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE)); + { + ALU64_BEGIN (GPR[RS]); + ALU64_ADD (EXTEND16 (IMMEDIATE)); + ALU64_END (GPR[RT]); /* This checks for overflow. */ + } + TRACE_ALU_RESULT (GPR[RT]); } + +:function:::void:do_daddiu:int rs, int rt, unsigned16 immediate +{ + TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); + GPR[rt] = GPR[rs] + EXTEND16 (immediate); + TRACE_ALU_RESULT (GPR[rt]); +} + 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU -"daddu r, r, " +"daddiu r, r, " *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: +*vr5000: { - GPR[RT] = GPR[RS] + EXTEND16 (IMMEDIATE); + check_u64 (SD_, instruction_0); + do_daddiu (SD_, RS, RT, IMMEDIATE); } + +:function:::void:do_daddu:int rs, int rt, int rd +{ + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + GPR[rd] = GPR[rs] + GPR[rt]; + TRACE_ALU_RESULT (GPR[rd]); +} + 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU "daddu r, r, r" *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: +*vr5000: { - GPR[RD] = GPR[RS] + GPR[RT]; + check_u64 (SD_, instruction_0); + do_daddu (SD_, RS, RT, RD); } -000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV -"ddiv r, r" -*mipsIII: -*mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 + +011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO +"dclo r, r" +*mips64: { - CHECKHILO ("Division"); - { - signed64 n = GPR[RS]; - signed64 d = GPR[RT]; - if (d == 0) - { - LO = SIGNED64 (0x8000000000000000); - HI = 0; - } + unsigned64 temp = GPR[RS]; + unsigned32 i; + unsigned64 mask; + check_u64 (SD_, instruction_0); + if (RT != RD) + Unpredictable (); + TRACE_ALU_INPUT1 (GPR[RS]); + for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i) + { + if ((temp & mask) == 0) + break; + mask >>= 1; + } + GPR[RD] = EXTEND32 (i); + TRACE_ALU_RESULT (GPR[RD]); +} + + + +011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ +"dclz r, r" +*mips64: +{ + unsigned64 temp = GPR[RS]; + unsigned32 i; + unsigned64 mask; + check_u64 (SD_, instruction_0); + if (RT != RD) + Unpredictable (); + TRACE_ALU_INPUT1 (GPR[RS]); + for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i) + { + if ((temp & mask) != 0) + break; + mask >>= 1; + } + GPR[RD] = EXTEND32 (i); + TRACE_ALU_RESULT (GPR[RD]); +} + + + +:function:::void:do_ddiv:int rs, int rt +{ + check_div_hilo (SD_, HIHISTORY, LOHISTORY); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + { + signed64 n = GPR[rs]; + signed64 d = GPR[rt]; + signed64 hi; + signed64 lo; + if (d == 0) + { + lo = SIGNED64 (0x8000000000000000); + hi = 0; + } else if (d == -1 && n == SIGNED64 (0x8000000000000000)) { - LO = SIGNED64 (0x8000000000000000); - HI = 0; + lo = SIGNED64 (0x8000000000000000); + hi = 0; } else { - LO = (n / d); - HI = (n % d); + lo = (n / d); + hi = (n % d); } + HI = hi; + LO = lo; } + TRACE_ALU_RESULT2 (HI, LO); } - - -000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU -"ddivu r, r" +000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV +"ddiv r, r" *mipsIII: *mipsIV: -*r3900: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 -{ - CHECKHILO ("Division"); +*mipsV: +*mips64: +*vr4100: +*vr5000: +{ + check_u64 (SD_, instruction_0); + do_ddiv (SD_, RS, RT); +} + + + +:function:::void:do_ddivu:int rs, int rt +{ + check_div_hilo (SD_, HIHISTORY, LOHISTORY); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); { - unsigned64 n = GPR[RS]; - unsigned64 d = GPR[RT]; + unsigned64 n = GPR[rs]; + unsigned64 d = GPR[rt]; + unsigned64 hi; + unsigned64 lo; if (d == 0) { - LO = SIGNED64 (0x8000000000000000); - HI = 0; + lo = SIGNED64 (0x8000000000000000); + hi = 0; } else { - LO = (n / d); - HI = (n % d); + lo = (n / d); + hi = (n % d); } + HI = hi; + LO = lo; } + TRACE_ALU_RESULT2 (HI, LO); } - -000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV -"div r, r" -*mipsI: -*mipsII: +000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU +"ddivu r, r" *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: +*vr5000: { - CHECKHILO("Division"); + check_u64 (SD_, instruction_0); + do_ddivu (SD_, RS, RT); +} + + + +:function:::void:do_div:int rs, int rt +{ + check_div_hilo (SD_, HIHISTORY, LOHISTORY); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); { - signed32 n = GPR[RS]; - signed32 d = GPR[RT]; + signed32 n = GPR[rs]; + signed32 d = GPR[rt]; if (d == 0) { LO = EXTEND32 (0x80000000); HI = EXTEND32 (0); } - else if (d == -1 && d == 0x80000000) + else if (n == SIGNED32 (0x80000000) && d == -1) { LO = EXTEND32 (0x80000000); HI = EXTEND32 (0); @@ -810,362 +1293,399 @@ HI = EXTEND32 (n % d); } } + TRACE_ALU_RESULT2 (HI, LO); } - -000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU -"divu r, r" +000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV +"div r, r" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - CHECKHILO ("Division"); + do_div (SD_, RS, RT); +} + + + +:function:::void:do_divu:int rs, int rt +{ + check_div_hilo (SD_, HIHISTORY, LOHISTORY); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); { - unsigned32 n = GPR[RS]; - unsigned32 d = GPR[RT]; + unsigned32 n = GPR[rs]; + unsigned32 d = GPR[rt]; if (d == 0) { LO = EXTEND32 (0x80000000); HI = EXTEND32 (0); } - else - { - LO = EXTEND32 (n / d); - HI = EXTEND32 (n % d); - } + else + { + LO = EXTEND32 (n / d); + HI = EXTEND32 (n % d); + } } + TRACE_ALU_RESULT2 (HI, LO); +} + +000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU +"divu r, r" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: +*r3900: +{ + do_divu (SD_, RS, RT); } -000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT + +:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p +{ + unsigned64 lo; + unsigned64 hi; + unsigned64 m00; + unsigned64 m01; + unsigned64 m10; + unsigned64 m11; + unsigned64 mid; + int sign; + unsigned64 op1 = GPR[rs]; + unsigned64 op2 = GPR[rt]; + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + /* make signed multiply unsigned */ + sign = 0; + if (signed_p) + { + if (op1 < 0) + { + op1 = - op1; + ++sign; + } + if (op2 < 0) + { + op2 = - op2; + ++sign; + } + } + /* multiply out the 4 sub products */ + m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2)); + m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2)); + m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2)); + m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2)); + /* add the products */ + mid = ((unsigned64) VH4_8 (m00) + + (unsigned64) VL4_8 (m10) + + (unsigned64) VL4_8 (m01)); + lo = U8_4 (mid, m00); + hi = (m11 + + (unsigned64) VH4_8 (mid) + + (unsigned64) VH4_8 (m01) + + (unsigned64) VH4_8 (m10)); + /* fix the sign */ + if (sign & 1) + { + lo = -lo; + if (lo == 0) + hi = -hi; + else + hi = -hi - 1; + } + /* save the result HI/LO (and a gpr) */ + LO = lo; + HI = hi; + if (rd != 0) + GPR[rd] = lo; + TRACE_ALU_RESULT2 (HI, LO); +} + +:function:::void:do_dmult:int rs, int rt, int rd +{ + do_dmultx (SD_, rs, rt, rd, 1); +} + +000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT "dmult r, r" *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: { - CHECKHILO ("Multiplication"); - { - signed64 op1 = GPR[RS]; - signed64 op2 = GPR[RT]; - unsigned64 lo; - unsigned64 hi; - unsigned64 m00; - unsigned64 m01; - unsigned64 m10; - unsigned64 m11; - unsigned64 mid; - int sign = 0; - /* make it unsigned */ - if (op1 < 0) - { - op1 = - op1; - ++sign; - } - if (op2 < 0) - { - op2 = - op2; - ++sign; - } - /* multuply out the 4 sub products */ - m00 = (VL4_8 (op1) * VL4_8 (op2)); - m10 = (VH4_8 (op1) * VL4_8 (op2)); - m01 = (VL4_8 (op1) * VH4_8 (op2)); - m11 = (VH4_8 (op1) * VH4_8 (op2)); - /* add the products */ - mid = VH4_8 (m00) + VL4_8 (m10) + VL4_8 (m01); - lo = U8_4 (mid, m00); - hi = m11 + VH4_8 (mid) + VH4_8 (m01) + VH4_8 (m10); - /* save the result */ - if (sign & 1) - { - LO = -lo; - if (lo == 0) - HI = -hi; - else - HI = -hi - 1; - } - else - { - LO = lo; - HI = hi; - } - } + check_u64 (SD_, instruction_0); + do_dmult (SD_, RS, RT, 0); +} + +000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT +"dmult r, r":RD == 0 +"dmult r, r, r" +*vr5000: +{ + check_u64 (SD_, instruction_0); + do_dmult (SD_, RS, RT, RD); } -000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU + +:function:::void:do_dmultu:int rs, int rt, int rd +{ + do_dmultx (SD_, rs, rt, rd, 0); +} + +000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU "dmultu r, r" *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: { - CHECKHILO ("Multiplication"); - { - signed64 op1 = GPR[RS]; - signed64 op2 = GPR[RT]; - unsigned64 lo; - unsigned64 hi; - unsigned64 m00; - unsigned64 m01; - unsigned64 m10; - unsigned64 m11; - unsigned64 mid; - /* multuply out the 4 sub products */ - m00 = (VL4_8 (op1) * VL4_8 (op2)); - m10 = (VH4_8 (op1) * VL4_8 (op2)); - m01 = (VL4_8 (op1) * VH4_8 (op2)); - m11 = (VH4_8 (op1) * VH4_8 (op2)); - /* add the products */ - mid = VH4_8 (m00) + VL4_8 (m10) + VL4_8 (m01); - lo = U8_4 (mid, m00); - hi = m11 + VH4_8 (mid) + VH4_8 (m01) + VH4_8 (m10); - /* save the result */ - LO = lo; - HI = hi; - } + check_u64 (SD_, instruction_0); + do_dmultu (SD_, RS, RT, 0); +} + +000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU +"dmultu r, r, r":RD == 0 +"dmultu r, r" +*vr5000: +{ + check_u64 (SD_, instruction_0); + do_dmultu (SD_, RS, RT, RD); } +:function:::void:do_dsll:int rt, int rd, int shift +{ + TRACE_ALU_INPUT2 (GPR[rt], shift); + GPR[rd] = GPR[rt] << shift; + TRACE_ALU_RESULT (GPR[rd]); +} -00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL +000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL "dsll r, r, " *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: +*vr5000: { - int s = SHIFT; - GPR[RD] = GPR[RT] << s; + check_u64 (SD_, instruction_0); + do_dsll (SD_, RT, RD, SHIFT); } -00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32 +000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32 "dsll32 r, r, " *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: +*vr5000: { int s = 32 + SHIFT; + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT2 (GPR[RT], s); GPR[RD] = GPR[RT] << s; + TRACE_ALU_RESULT (GPR[RD]); } +:function:::void:do_dsllv:int rs, int rt, int rd +{ + int s = MASKED64 (GPR[rs], 5, 0); + TRACE_ALU_INPUT2 (GPR[rt], s); + GPR[rd] = GPR[rt] << s; + TRACE_ALU_RESULT (GPR[rd]); +} -000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV +000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV "dsllv r, r, r" *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: +*vr5000: { - int s = MASKED64 (GPR[RS], 5, 0); - GPR[RD] = GPR[RT] << s; + check_u64 (SD_, instruction_0); + do_dsllv (SD_, RS, RT, RD); +} + +:function:::void:do_dsra:int rt, int rd, int shift +{ + TRACE_ALU_INPUT2 (GPR[rt], shift); + GPR[rd] = ((signed64) GPR[rt]) >> shift; + TRACE_ALU_RESULT (GPR[rd]); } -00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA +000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA "dsra r, r, " *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: +*vr5000: { - int s = SHIFT; - GPR[RD] = ((signed64) GPR[RT]) >> s; + check_u64 (SD_, instruction_0); + do_dsra (SD_, RT, RD, SHIFT); } -00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32 -"dsra32 r, r, " +000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32 +"dsra32 r, r, " *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: +*vr5000: { int s = 32 + SHIFT; + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT2 (GPR[RT], s); GPR[RD] = ((signed64) GPR[RT]) >> s; + TRACE_ALU_RESULT (GPR[RD]); } -000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV -"dsra32 r, r, r" +:function:::void:do_dsrav:int rs, int rt, int rd +{ + int s = MASKED64 (GPR[rs], 5, 0); + TRACE_ALU_INPUT2 (GPR[rt], s); + GPR[rd] = ((signed64) GPR[rt]) >> s; + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV +"dsrav r, r, r" *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: +*vr5000: { - int s = MASKED64 (GPR[RS], 5, 0); - GPR[RD] = ((signed64) GPR[RT]) >> s; + check_u64 (SD_, instruction_0); + do_dsrav (SD_, RS, RT, RD); +} + +:function:::void:do_dsrl:int rt, int rd, int shift +{ + TRACE_ALU_INPUT2 (GPR[rt], shift); + GPR[rd] = (unsigned64) GPR[rt] >> shift; + TRACE_ALU_RESULT (GPR[rd]); } -00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL -"dsrav r, r, " +000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL +"dsrl r, r, " *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: +*vr5000: { - int s = SHIFT; - GPR[RD] = (unsigned64) GPR[RT] >> s; + check_u64 (SD_, instruction_0); + do_dsrl (SD_, RT, RD, SHIFT); } -00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32 +000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32 "dsrl32 r, r, " *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: +*vr5000: { int s = 32 + SHIFT; + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT2 (GPR[RT], s); GPR[RD] = (unsigned64) GPR[RT] >> s; + TRACE_ALU_RESULT (GPR[RD]); } -000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV -"dsrl32 r, r, r" +:function:::void:do_dsrlv:int rs, int rt, int rd +{ + int s = MASKED64 (GPR[rs], 5, 0); + TRACE_ALU_INPUT2 (GPR[rt], s); + GPR[rd] = (unsigned64) GPR[rt] >> s; + TRACE_ALU_RESULT (GPR[rd]); +} + + + +000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV +"dsrlv r, r, r" *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: +*vr5000: { - int s = MASKED64 (GPR[RS], 5, 0); - GPR[RD] = (unsigned64) GPR[RT] >> s; + check_u64 (SD_, instruction_0); + do_dsrlv (SD_, RS, RT, RD); } -000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB +000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB "dsub r, r, r" *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: +*vr5000: { - ALU64_BEGIN (GPR[RS]); - ALU64_SUB (GPR[RT]); - ALU64_END (GPR[RD]); + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + { + ALU64_BEGIN (GPR[RS]); + ALU64_SUB (GPR[RT]); + ALU64_END (GPR[RD]); /* This checks for overflow. */ + } + TRACE_ALU_RESULT (GPR[RD]); } -000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU +:function:::void:do_dsubu:int rs, int rt, int rd +{ + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + GPR[rd] = GPR[rs] - GPR[rt]; + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU "dsubu r, r, r" *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: +*vr5000: { - GPR[RD] = GPR[RS] - GPR[RT]; + check_u64 (SD_, instruction_0); + do_dsubu (SD_, RS, RT, RD); } @@ -1175,16 +1695,12 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { /* NOTE: The region used is that of the delay slot NIA and NOT the current instruction */ @@ -1199,16 +1715,12 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { /* NOTE: The region used is that of the delay slot and NOT the current instruction */ @@ -1217,24 +1729,19 @@ DELAY_SLOT (region | (INSTR_INDEX << 2)); } - -000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR +000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR "jalr r":RD == 31 "jalr r, r" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { address_word temp = GPR[RS]; GPR[RD] = CIA + 8; @@ -1242,69 +1749,147 @@ } -000000,5.RS,000000000000000001000:SPECIAL:32::JR +000000,5.RS,000000000000000,001000:SPECIAL:32::JR "jr r" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { DELAY_SLOT (GPR[RS]); } +:function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset +{ + address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); + address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0); + address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); + unsigned int byte; + address_word paddr; + int uncached; + unsigned64 memval; + address_word vaddr; + + vaddr = loadstore_ea (SD_, base, offset); + if ((vaddr & access) != 0) + { + SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal); + } + AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL); + paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); + LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL); + byte = ((vaddr & mask) ^ bigendiancpu); + return (memval >> (8 * byte)); +} + +:function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt +{ + address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); + address_word reverseendian = (ReverseEndian ? -1 : 0); + address_word bigendiancpu = (BigEndianCPU ? -1 : 0); + unsigned int byte; + unsigned int word; + address_word paddr; + int uncached; + unsigned64 memval; + address_word vaddr; + int nr_lhs_bits; + int nr_rhs_bits; + unsigned_word lhs_mask; + unsigned_word temp; + + vaddr = loadstore_ea (SD_, base, offset); + AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL); + paddr = (paddr ^ (reverseendian & mask)); + if (BigEndianMem == 0) + paddr = paddr & ~access; + + /* compute where within the word/mem we are */ + byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */ + word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */ + nr_lhs_bits = 8 * byte + 8; + nr_rhs_bits = 8 * access - 8 * byte; + /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */ + + /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n", + (long) ((unsigned64) vaddr >> 32), (long) vaddr, + (long) ((unsigned64) paddr >> 32), (long) paddr, + word, byte, nr_lhs_bits, nr_rhs_bits); */ + + LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL); + if (word == 0) + { + /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */ + temp = (memval << nr_rhs_bits); + } + else + { + /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */ + temp = (memval >> nr_lhs_bits); + } + lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits); + rt = (rt & ~lhs_mask) | (temp & lhs_mask); + + /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n", + (long) ((unsigned64) memval >> 32), (long) memval, + (long) ((unsigned64) temp >> 32), (long) temp, + (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask, + (long) (rt >> 32), (long) rt); */ + return rt; +} + +:function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt +{ + address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); + address_word reverseendian = (ReverseEndian ? -1 : 0); + address_word bigendiancpu = (BigEndianCPU ? -1 : 0); + unsigned int byte; + address_word paddr; + int uncached; + unsigned64 memval; + address_word vaddr; + + vaddr = loadstore_ea (SD_, base, offset); + AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL); + /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */ + paddr = (paddr ^ (reverseendian & mask)); + if (BigEndianMem != 0) + paddr = paddr & ~access; + byte = ((vaddr & mask) ^ (bigendiancpu & mask)); + /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */ + LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL); + /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n", + (long) paddr, byte, (long) paddr, (long) memval); */ + { + unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0); + rt &= ~screen; + rt |= (memval >> (8 * byte)) & screen; + } + return rt; +} + + 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB "lb r, (r)" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - int destreg = ((instruction >> 16) & 0x0000001F); - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((uword64)op1 + offset); - address_word paddr; - int uncached; - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - uword64 memval = 0; - uword64 memval1 = 0; - uword64 mask = 0x7; - unsigned int shift = 0; - unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); - unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); - LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL); - byte = ((vaddr & mask) ^ (bigend << shift)); - GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8)); - } - } - } + GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET))); } @@ -1314,42 +1899,14 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - int destreg = ((instruction >> 16) & 0x0000001F); - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int shift = 0; - unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); - unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); - LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL); - byte = ((vaddr & mask) ^ (bigend << shift)); - GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF)); - } - } - } + GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)); } @@ -1357,38 +1914,13 @@ "ld r, (r)" *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: +*vr5000: { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - int destreg = ((instruction >> 16) & 0x0000001F); - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 7) != 0) - SignalExceptionAddressLoad(); - else - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); - GPR[destreg] = memval; - } - } - } + check_u64 (SD_, instruction_0); + GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET))); } @@ -1397,82 +1929,30 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - int destreg = ((instruction >> 16) & 0x0000001F); - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 7) != 0) - SignalExceptionAddressLoad(); - else - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); - COP_LD(((instruction >> 26) & 0x3),destreg,memval);; - } - } - } + COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET))); } + + 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL "ldl r, (r)" *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: +*vr5000: { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - int destreg = ((instruction >> 16) & 0x0000001F); - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 7; - unsigned int reverse = (ReverseEndian ? mask : 0); - unsigned int bigend = (BigEndianCPU ? mask : 0); - int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); - byte = ((vaddr & mask) ^ bigend); - if (!BigEndianMem) - paddr &= ~mask; - LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL); - GPR[destreg] = ((memval << ((7 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((7 - byte) * 8)) - 1))); - } - } - } + check_u64 (SD_, instruction_0); + GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); } @@ -1480,50 +1960,13 @@ "ldr r, (r)" *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: +*vr5000: { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - int destreg = ((instruction >> 16) & 0x0000001F); - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 7; - unsigned int reverse = (ReverseEndian ? mask : 0); - unsigned int bigend = (BigEndianCPU ? mask : 0); - int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); - byte = ((vaddr & mask) ^ bigend); - if (BigEndianMem) - paddr &= ~mask; - LoadMemory(&memval,&memval1,uncached,(7 - byte),paddr,vaddr,isDATA,isREAL); - { - unsigned64 srcmask; - if (byte == 0) - srcmask = 0; - else - srcmask = ((unsigned64)-1 << (8 * (8 - byte))); - GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte))); - } - } - } - } + check_u64 (SD_, instruction_0); + GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); } @@ -1533,45 +1976,14 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - int destreg = ((instruction >> 16) & 0x0000001F); - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 1) != 0) - SignalExceptionAddressLoad(); - else - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int shift = 1; - unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); - unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); - LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL); - byte = ((vaddr & mask) ^ (bigend << shift)); - GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16)); - } - } - } + GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET))); } @@ -1581,45 +1993,14 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - int destreg = ((instruction >> 16) & 0x0000001F); - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 1) != 0) - SignalExceptionAddressLoad(); - else - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int shift = 1; - unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); - unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); - LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL); - byte = ((vaddr & mask) ^ (bigend << shift)); - GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF)); - } - } - } + GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)); } @@ -1628,27 +2009,22 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - int destreg = ((instruction >> 16) & 0x0000001F); - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; + address_word base = GPR[BASE]; + address_word offset = EXTEND16 (OFFSET); { - address_word vaddr = ((unsigned64)op1 + offset); + address_word vaddr = loadstore_ea (SD_, base, offset); address_word paddr; int uncached; if ((vaddr & 3) != 0) - SignalExceptionAddressLoad(); + { + SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal); + } else { if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) @@ -1663,7 +2039,7 @@ paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); byte = ((vaddr & mask) ^ (bigend << shift)); - GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32)); + GPR[RT] = EXTEND32 (memval >> (8 * byte)); LLBIT = 1; } } @@ -1675,27 +2051,22 @@ "lld r, (r)" *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: +*vr5000: { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - int destreg = ((instruction >> 16) & 0x0000001F); - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; + address_word base = GPR[BASE]; + address_word offset = EXTEND16 (OFFSET); + check_u64 (SD_, instruction_0); { - address_word vaddr = ((unsigned64)op1 + offset); + address_word vaddr = loadstore_ea (SD_, base, offset); address_word paddr; int uncached; if ((vaddr & 7) != 0) - SignalExceptionAddressLoad(); + { + SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal); + } else { if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) @@ -1703,7 +2074,7 @@ unsigned64 memval = 0; unsigned64 memval1 = 0; LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); - GPR[destreg] = memval; + GPR[RT] = memval; LLBIT = 1; } } @@ -1712,23 +2083,21 @@ 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI -"lui r, " +"lui r, %#lx" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { + TRACE_ALU_INPUT1 (IMMEDIATE); GPR[RT] = EXTEND32 (IMMEDIATE << 16); + TRACE_ALU_RESULT (GPR[RT]); } @@ -1738,45 +2107,14 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - int destreg = ((instruction >> 16) & 0x0000001F); - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 3) != 0) - SignalExceptionAddressLoad(); - else - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int shift = 2; - unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); - unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); - LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); - byte = ((vaddr & mask) ^ (bigend << shift)); - GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32)); - } - } - } + GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET))); } @@ -1786,45 +2124,14 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - int destreg = ((instruction >> 16) & 0x0000001F); - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 3) != 0) - SignalExceptionAddressLoad(); - else - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int shift = 2; - unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); - unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); - LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); - byte = ((vaddr & mask) ^ (bigend << shift)); - COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF)); - } - } - } + COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET))); } @@ -1834,47 +2141,14 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - int destreg = ((instruction >> 16) & 0x0000001F); - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 3; - unsigned int reverse = (ReverseEndian ? mask : 0); - unsigned int bigend = (BigEndianCPU ? mask : 0); - int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); - byte = ((vaddr & mask) ^ bigend); - if (!BigEndianMem) - paddr &= ~mask; - LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL); - if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) { - memval >>= 32; - } - GPR[destreg] = ((memval << ((3 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((3 - byte) * 8)) - 1))); - GPR[destreg] = SIGNEXTEND(GPR[destreg],32); - } - } - } + GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT])); } @@ -1884,408 +2158,528 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - int destreg = ((instruction >> 16) & 0x0000001F); - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 3; - unsigned int reverse = (ReverseEndian ? mask : 0); - unsigned int bigend = (BigEndianCPU ? mask : 0); - int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); - byte = ((vaddr & mask) ^ bigend); - if (BigEndianMem) - paddr &= ~mask; - LoadMemory(&memval,&memval1,uncached,(3 - byte),paddr,vaddr,isDATA,isREAL); - if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) { - memval >>= 32; - } - { - unsigned64 srcmask; - if (byte == 0) - srcmask = 0; - else - srcmask = ((unsigned64)-1 << (8 * (4 - byte))); - GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte))); - } - GPR[destreg] = SIGNEXTEND(GPR[destreg],32); - } - } - } + GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT])); } -100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU +100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU "lwu r, (r)" *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: +*vr5000: { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - int destreg = ((instruction >> 16) & 0x0000001F); - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 3) != 0) - SignalExceptionAddressLoad(); - else - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int shift = 2; - unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); - unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); - LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); - byte = ((vaddr & mask) ^ (bigend << shift)); - GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF)); - } - } - } + check_u64 (SD_, instruction_0); + GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)); +} + + + +011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD +"madd r, r" +*mips32: +*mips64: +{ + signed64 temp; + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) + + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS]))); + LO = EXTEND32 (temp); + HI = EXTEND32 (VH4_8 (temp)); + TRACE_ALU_RESULT2 (HI, LO); +} + + + +011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU +"maddu r, r" +*mips32: +*mips64: +{ + unsigned64 temp; + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) + + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT]))); + LO = EXTEND32 (temp); + HI = EXTEND32 (VH4_8 (temp)); + TRACE_ALU_RESULT2 (HI, LO); } +:function:::void:do_mfhi:int rd +{ + check_mf_hilo (SD_, HIHISTORY, LOHISTORY); + TRACE_ALU_INPUT1 (HI); + GPR[rd] = HI; + TRACE_ALU_RESULT (GPR[rd]); +} + 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI "mfhi r" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - GPR[RD] = HI; - HIACCESS = 3; + do_mfhi (SD_, RD); } + +:function:::void:do_mflo:int rd +{ + check_mf_hilo (SD_, LOHISTORY, HIHISTORY); + TRACE_ALU_INPUT1 (LO); + GPR[rd] = LO; + TRACE_ALU_RESULT (GPR[rd]); +} + 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO "mflo r" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - GPR[RD] = LO; - LOACCESS = 3; /* 3rd instruction will be safe */ + do_mflo (SD_, RD); } -000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN + +000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN "movn r, r, r" *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr5000: { if (GPR[RT] != 0) - GPR[RD] = GPR[RS]; + { + GPR[RD] = GPR[RS]; + TRACE_ALU_RESULT (GPR[RD]); + } } -000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ + +000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ "movz r, r, r" *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr5000: { if (GPR[RT] == 0) - GPR[RD] = GPR[RS]; + { + GPR[RD] = GPR[RS]; + TRACE_ALU_RESULT (GPR[RD]); + } +} + + + +011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB +"msub r, r" +*mips32: +*mips64: +{ + signed64 temp; + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) + - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS]))); + LO = EXTEND32 (temp); + HI = EXTEND32 (VH4_8 (temp)); + TRACE_ALU_RESULT2 (HI, LO); +} + + + +011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU +"msubu r, r" +*mips32: +*mips64: +{ + unsigned64 temp; + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) + - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT]))); + LO = EXTEND32 (temp); + HI = EXTEND32 (VH4_8 (temp)); + TRACE_ALU_RESULT2 (HI, LO); } + 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI "mthi r" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - if (HIACCESS != 0) - sim_io_eprintf (sd, "MT (move-to) over-writing HI register value\n"); + check_mt_hilo (SD_, HIHISTORY); HI = GPR[RS]; - HIACCESS = 3; /* 3rd instruction will be safe */ } -000000,5.RS,000000000000000010011:SPECIAL:32::MTLO + +000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO "mtlo r" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - if (LOACCESS != 0) - sim_io_eprintf (sd, "MT (move-to) over-writing LO register value\n"); + check_mt_hilo (SD_, LOHISTORY); LO = GPR[RS]; - LOACCESS = 3; /* 3rd instruction will be safe */ } -000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT + +011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL +"mul r, r, r" +*mips32: +*mips64: +{ + signed64 prod; + if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + prod = (((signed64)(signed32) GPR[RS]) + * ((signed64)(signed32) GPR[RT])); + GPR[RD] = EXTEND32 (VL4_8 (prod)); + TRACE_ALU_RESULT (GPR[RD]); +} + + + +:function:::void:do_mult:int rs, int rt, int rd +{ + signed64 prod; + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + prod = (((signed64)(signed32) GPR[rs]) + * ((signed64)(signed32) GPR[rt])); + LO = EXTEND32 (VL4_8 (prod)); + HI = EXTEND32 (VH4_8 (prod)); + if (rd != 0) + GPR[rd] = LO; + TRACE_ALU_RESULT2 (HI, LO); +} + +000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT "mult r, r" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +{ + do_mult (SD_, RS, RT, 0); +} + + +000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT +"mult r, r":RD == 0 +"mult r, r, r" +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - signed64 prod; - CHECKHILO ("Multiplication"); - prod = (((signed64)(signed32) GPR[RS]) - * ((signed64)(signed32) GPR[RT])); + do_mult (SD_, RS, RT, RD); +} + + +:function:::void:do_multu:int rs, int rt, int rd +{ + unsigned64 prod; + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + prod = (((unsigned64)(unsigned32) GPR[rs]) + * ((unsigned64)(unsigned32) GPR[rt])); LO = EXTEND32 (VL4_8 (prod)); HI = EXTEND32 (VH4_8 (prod)); + if (rd != 0) + GPR[rd] = LO; + TRACE_ALU_RESULT2 (HI, LO); } - -000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU +000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU "multu r, r" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +{ + do_multu (SD_, RS, RT, 0); +} + +000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU +"multu r, r":RD == 0 +"multu r, r, r" +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned64 prod; - CHECKHILO ("Multiplication"); - prod = (((unsigned64)(unsigned32) GPR[RS]) - * ((unsigned64)(unsigned32) GPR[RT])); - LO = EXTEND32 (VL4_8 (prod)); - HI = EXTEND32 (VH4_8 (prod)); + do_multu (SD_, RS, RT, RD); } +:function:::void:do_nor:int rs, int rt, int rd +{ + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + GPR[rd] = ~ (GPR[rs] | GPR[rt]); + TRACE_ALU_RESULT (GPR[rd]); +} + 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR "nor r, r, r" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - GPR[RD] = ~ (GPR[RS] | GPR[RT]); + do_nor (SD_, RS, RT, RD); } +:function:::void:do_or:int rs, int rt, int rd +{ + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + GPR[rd] = (GPR[rs] | GPR[rt]); + TRACE_ALU_RESULT (GPR[rd]); +} + 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR "or r, r, r" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - GPR[RD] = (GPR[RS] | GPR[RT]); + do_or (SD_, RS, RT, RD); } + +:function:::void:do_ori:int rs, int rt, unsigned immediate +{ + TRACE_ALU_INPUT2 (GPR[rs], immediate); + GPR[rt] = (GPR[rs] | immediate); + TRACE_ALU_RESULT (GPR[rt]); +} + 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI -"ori r, r, " +"ori r, r, %#lx" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - GPR[RT] = (GPR[RS] | IMMEDIATE); + do_ori (SD_, RS, RT, IMMEDIATE); } -110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF +110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF +"pref , (r)" *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr5000: { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - int hint = ((instruction >> 16) & 0x0000001F); - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; + address_word base = GPR[BASE]; + address_word offset = EXTEND16 (OFFSET); { - address_word vaddr = ((unsigned64)op1 + offset); + address_word vaddr = loadstore_ea (SD_, base, offset); address_word paddr; int uncached; { if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - Prefetch(uncached,paddr,vaddr,isDATA,hint); + Prefetch(uncached,paddr,vaddr,isDATA,HINT); } } } + +:function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word +{ + address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); + address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0); + address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); + unsigned int byte; + address_word paddr; + int uncached; + unsigned64 memval; + address_word vaddr; + + vaddr = loadstore_ea (SD_, base, offset); + if ((vaddr & access) != 0) + { + SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal); + } + AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL); + paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); + byte = ((vaddr & mask) ^ bigendiancpu); + memval = (word << (8 * byte)); + StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL); +} + +:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt +{ + address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); + address_word reverseendian = (ReverseEndian ? -1 : 0); + address_word bigendiancpu = (BigEndianCPU ? -1 : 0); + unsigned int byte; + unsigned int word; + address_word paddr; + int uncached; + unsigned64 memval; + address_word vaddr; + int nr_lhs_bits; + int nr_rhs_bits; + + vaddr = loadstore_ea (SD_, base, offset); + AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL); + paddr = (paddr ^ (reverseendian & mask)); + if (BigEndianMem == 0) + paddr = paddr & ~access; + + /* compute where within the word/mem we are */ + byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */ + word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */ + nr_lhs_bits = 8 * byte + 8; + nr_rhs_bits = 8 * access - 8 * byte; + /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */ + /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n", + (long) ((unsigned64) vaddr >> 32), (long) vaddr, + (long) ((unsigned64) paddr >> 32), (long) paddr, + word, byte, nr_lhs_bits, nr_rhs_bits); */ + + if (word == 0) + { + memval = (rt >> nr_rhs_bits); + } + else + { + memval = (rt << nr_lhs_bits); + } + /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n", + (long) ((unsigned64) rt >> 32), (long) rt, + (long) ((unsigned64) memval >> 32), (long) memval); */ + StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL); +} + +:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt +{ + address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); + address_word reverseendian = (ReverseEndian ? -1 : 0); + address_word bigendiancpu = (BigEndianCPU ? -1 : 0); + unsigned int byte; + address_word paddr; + int uncached; + unsigned64 memval; + address_word vaddr; + + vaddr = loadstore_ea (SD_, base, offset); + AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL); + paddr = (paddr ^ (reverseendian & mask)); + if (BigEndianMem != 0) + paddr &= ~access; + byte = ((vaddr & mask) ^ (bigendiancpu & mask)); + memval = (rt << (byte * 8)); + StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL); +} + + 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB "sb r, (r)" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - { - if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int shift = 0; - unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); - unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); - byte = ((vaddr & mask) ^ (bigend << shift)); - memval = ((unsigned64) op2 << (8 * byte)); - { - StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL); - } - } - } - } + do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); } @@ -2294,27 +2688,23 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: { unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; + address_word base = GPR[BASE]; + address_word offset = EXTEND16 (OFFSET); { - address_word vaddr = ((unsigned64)op1 + offset); + address_word vaddr = loadstore_ea (SD_, base, offset); address_word paddr; int uncached; if ((vaddr & 3) != 0) - SignalExceptionAddressStore(); + { + SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal); + } else { if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) @@ -2325,12 +2715,12 @@ unsigned int byte; paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); - memval = ((unsigned64) op2 << (8 * byte)); + memval = ((unsigned64) GPR[RT] << (8 * byte)); if (LLBIT) { StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); } - GPR[(instruction >> 16) & 0x0000001F] = LLBIT; + GPR[RT] = LLBIT; } } } @@ -2341,39 +2731,34 @@ "scd r, (r)" *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: +*vr5000: { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; + address_word base = GPR[BASE]; + address_word offset = EXTEND16 (OFFSET); + check_u64 (SD_, instruction_0); { - address_word vaddr = ((unsigned64)op1 + offset); + address_word vaddr = loadstore_ea (SD_, base, offset); address_word paddr; int uncached; if ((vaddr & 7) != 0) - SignalExceptionAddressStore(); + { + SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal); + } else { if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) { unsigned64 memval = 0; unsigned64 memval1 = 0; - memval = op2; + memval = GPR[RT]; if (LLBIT) { StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); } - GPR[(instruction >> 16) & 0x0000001F] = LLBIT; + GPR[RT] = LLBIT; } } } @@ -2384,40 +2769,13 @@ "sd r, (r)" *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: +*vr5000: { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 7) != 0) - SignalExceptionAddressStore(); - else - { - if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - memval = op2; - { - StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); - } - } - } - } + check_u64 (SD_, instruction_0); + do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); } @@ -2426,40 +2784,13 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - int destreg = ((instruction >> 16) & 0x0000001F); - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 7) != 0) - SignalExceptionAddressStore(); - else - { - if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - memval = (unsigned64)COP_SD(((instruction >> 26) & 0x3),destreg); - { - StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); - } - } - } - } + do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT)); } @@ -2467,43 +2798,13 @@ "sdl r, (r)" *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: +*vr5000: { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - { - if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 7; - unsigned int reverse = (ReverseEndian ? mask : 0); - unsigned int bigend = (BigEndianCPU ? mask : 0); - int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); - byte = ((vaddr & mask) ^ bigend); - if (!BigEndianMem) - paddr &= ~mask; - memval = (op2 >> (8 * (7 - byte))); - StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL); - } - } - } + check_u64 (SD_, instruction_0); + do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); } @@ -2511,43 +2812,13 @@ "sdr r, (r)" *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips64: +*vr4100: +*vr5000: { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - { - if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 7; - unsigned int reverse = (ReverseEndian ? mask : 0); - unsigned int bigend = (BigEndianCPU ? mask : 0); - int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); - byte = ((vaddr & mask) ^ bigend); - if (!BigEndianMem) - paddr &= ~mask; - memval = ((unsigned64) op2 << (byte * 8)); - StoreMemory(uncached,(AccessLength_DOUBLEWORD - byte),memval,memval1,paddr,vaddr,isREAL); - } - } - } + check_u64 (SD_, instruction_0); + do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); } @@ -2557,359 +2828,357 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 1) != 0) - SignalExceptionAddressStore(); - else - { - if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int shift = 1; - unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); - unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); - byte = ((vaddr & mask) ^ (bigend << shift)); - memval = ((unsigned64) op2 << (8 * byte)); - { - StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL); - } - } - } - } + do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); } -00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL +:function:::void:do_sll:int rt, int rd, int shift +{ + unsigned32 temp = (GPR[rt] << shift); + TRACE_ALU_INPUT2 (GPR[rt], shift); + GPR[rd] = EXTEND32 (temp); + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa +"nop":RD == 0 && RT == 0 && SHIFT == 0 "sll r, r, " *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - int s = SHIFT; - unsigned32 temp = (GPR[RT] << s); - GPR[RD] = EXTEND32 (temp); + /* Skip shift for NOP, so that there won't be lots of extraneous + trace output. */ + if (RD != 0 || RT != 0 || SHIFT != 0) + do_sll (SD_, RT, RD, SHIFT); +} + +000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb +"nop":RD == 0 && RT == 0 && SHIFT == 0 +"ssnop":RD == 0 && RT == 0 && SHIFT == 1 +"sll r, r, " +*mips32: +*mips64: +{ + /* Skip shift for NOP and SSNOP, so that there won't be lots of + extraneous trace output. */ + if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1)) + do_sll (SD_, RT, RD, SHIFT); } -000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV +:function:::void:do_sllv:int rs, int rt, int rd +{ + int s = MASKED (GPR[rs], 4, 0); + unsigned32 temp = (GPR[rt] << s); + TRACE_ALU_INPUT2 (GPR[rt], s); + GPR[rd] = EXTEND32 (temp); + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV "sllv r, r, r" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - int s = MASKED (GPR[RS], 4, 0); - unsigned32 temp = (GPR[RT] << s); - GPR[RD] = EXTEND32 (temp); + do_sllv (SD_, RS, RT, RD); } -000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT +:function:::void:do_slt:int rs, int rt, int rd +{ + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]); + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT "slt r, r, r" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - GPR[RD] = (GPR[RS] < GPR[RT]); + do_slt (SD_, RS, RT, RD); } +:function:::void:do_slti:int rs, int rt, unsigned16 immediate +{ + TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); + GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate)); + TRACE_ALU_RESULT (GPR[rt]); +} + 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI "slti r, r, " *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - GPR[RT] = (GPR[RS] < EXTEND16 (IMMEDIATE)); + do_slti (SD_, RS, RT, IMMEDIATE); } +:function:::void:do_sltiu:int rs, int rt, unsigned16 immediate +{ + TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); + GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate)); + TRACE_ALU_RESULT (GPR[rt]); +} + 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU "sltiu r, r, " *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - GPR[RT] = ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE)); + do_sltiu (SD_, RS, RT, IMMEDIATE); +} + + + +:function:::void:do_sltu:int rs, int rt, int rd +{ + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]); + TRACE_ALU_RESULT (GPR[rd]); } -000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU +000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU "sltu r, r, r" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - GPR[RD] = ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]); + do_sltu (SD_, RS, RT, RD); } +:function:::void:do_sra:int rt, int rd, int shift +{ + signed32 temp = (signed32) GPR[rt] >> shift; + if (NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rt], shift); + GPR[rd] = EXTEND32 (temp); + TRACE_ALU_RESULT (GPR[rd]); +} + 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA "sra r, r, " *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - int s = SHIFT; - signed32 temp = (signed32) GPR[RT] >> s; - GPR[RD] = EXTEND32 (temp); + do_sra (SD_, RT, RD, SHIFT); } -000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV + +:function:::void:do_srav:int rs, int rt, int rd +{ + int s = MASKED (GPR[rs], 4, 0); + signed32 temp = (signed32) GPR[rt] >> s; + if (NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rt], s); + GPR[rd] = EXTEND32 (temp); + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV "srav r, r, r" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - int s = MASKED (GPR[RS], 4, 0); - signed32 temp = (signed32) GPR[RT] >> s; - GPR[RD] = EXTEND32 (temp); + do_srav (SD_, RS, RT, RD); } + +:function:::void:do_srl:int rt, int rd, int shift +{ + unsigned32 temp = (unsigned32) GPR[rt] >> shift; + if (NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rt], shift); + GPR[rd] = EXTEND32 (temp); + TRACE_ALU_RESULT (GPR[rd]); +} + 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL "srl r, r, " *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - int s = SHIFT; - unsigned32 temp = (unsigned32) GPR[RT] >> s; - GPR[RD] = EXTEND32 (temp); + do_srl (SD_, RT, RD, SHIFT); } -000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV +:function:::void:do_srlv:int rs, int rt, int rd +{ + int s = MASKED (GPR[rs], 4, 0); + unsigned32 temp = (unsigned32) GPR[rt] >> s; + if (NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rt], s); + GPR[rd] = EXTEND32 (temp); + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV "srlv r, r, r" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - int s = MASKED (GPR[RS], 4, 0); - unsigned32 temp = (unsigned32) GPR[RT] >> s; - GPR[RD] = EXTEND32 (temp); + do_srlv (SD_, RS, RT, RD); } -000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB +000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB "sub r, r, r" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - ALU32_BEGIN (GPR[RS]); - ALU32_SUB (GPR[RT]); - ALU32_END (GPR[RD]); + if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + { + ALU32_BEGIN (GPR[RS]); + ALU32_SUB (GPR[RT]); + ALU32_END (GPR[RD]); /* This checks for overflow. */ + } + TRACE_ALU_RESULT (GPR[RD]); } -000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU -"subu r, r, r" -*mipsI: -*mipsII: -*mipsIII: -*mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +:function:::void:do_subu:int rs, int rt, int rd { - GPR[RD] = EXTEND32 (GPR[RS] - GPR[RT]); + if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]); + TRACE_ALU_RESULT (GPR[rd]); } - -101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW -"sw r, (r)" +000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU +"subu r, r, r" *mipsI: -*mipsII: -*mipsIII: -*mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 -{ - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 3) != 0) - SignalExceptionAddressStore(); - else - { - if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); - byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); - memval = ((unsigned64) op2 << (8 * byte)); - { - StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); - } - } - } - } +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: +*r3900: +{ + do_subu (SD_, RS, RT, RD); +} + + +101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW +"sw r, (r)" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips64: +*vr4100: +*r3900: +*vr5000: +{ + do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); } @@ -2919,44 +3188,14 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - int destreg = ((instruction >> 16) & 0x0000001F); - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - if ((vaddr & 3) != 0) - SignalExceptionAddressStore(); - else - { - if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); - byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); - memval = (((unsigned64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte)); - { - StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); - } - } - } - } + do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT)); } @@ -2966,46 +3205,14 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - { - if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 3; - unsigned int reverse = (ReverseEndian ? mask : 0); - unsigned int bigend = (BigEndianCPU ? mask : 0); - int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); - byte = ((vaddr & mask) ^ bigend); - if (!BigEndianMem) - paddr &= ~mask; - memval = (op2 >> (8 * (3 - byte))); - if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) { - memval <<= 32; - } - StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL); - } - } - } + do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); } @@ -3015,88 +3222,48 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((unsigned64)op1 + offset); - address_word paddr; - int uncached; - { - if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 3; - unsigned int reverse = (ReverseEndian ? mask : 0); - unsigned int bigend = (BigEndianCPU ? mask : 0); - int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); - byte = ((vaddr & mask) ^ bigend); - if (!BigEndianMem) - paddr &= ~mask; - memval = ((unsigned64) op2 << (byte * 8)); - if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) { - memval <<= 32; - } - StoreMemory(uncached,(AccessLength_WORD - byte),memval,memval1,paddr,vaddr,isREAL); - } - } - } + do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); } -000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC +000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC "sync":STYPE == 0 "sync " *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { SyncOperation (STYPE); } 000000,20.CODE,001100:SPECIAL:32::SYSCALL -"syscall " +"syscall %#lx" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - SignalException(SystemCall, instruction_0); + SignalException (SystemCall, instruction_0); } @@ -3105,19 +3272,14 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: { - if (GPR[RS] == GPR[RT]) - SignalException(Trap, instruction_0); + if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) + SignalException (Trap, instruction_0); } @@ -3126,19 +3288,14 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: { - if (GPR[RS] == EXTEND16 (IMMEDIATE)) - SignalException(Trap, instruction_0); + if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE)) + SignalException (Trap, instruction_0); } @@ -3147,19 +3304,14 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: { - if (GPR[RS] >= GPR[RT]) - SignalException(Trap, instruction_0); + if ((signed_word) GPR[RS] >= (signed_word) GPR[RT]) + SignalException (Trap, instruction_0); } @@ -3168,19 +3320,14 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: { - if (GPR[RS] >= EXTEND16 (IMMEDIATE)) - SignalException(Trap, instruction_0); + if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE)) + SignalException (Trap, instruction_0); } @@ -3189,19 +3336,14 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: { if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE)) - SignalException(Trap, instruction_0); + SignalException (Trap, instruction_0); } @@ -3210,19 +3352,14 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: { if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT]) - SignalException(Trap, instruction_0); + SignalException (Trap, instruction_0); } @@ -3231,19 +3368,14 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: { - if (GPR[RS] < GPR[RT]) - SignalException(Trap, instruction_0); + if ((signed_word) GPR[RS] < (signed_word) GPR[RT]) + SignalException (Trap, instruction_0); } @@ -3252,19 +3384,14 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: { - if (GPR[RS] < EXTEND16 (IMMEDIATE)) - SignalException(Trap, instruction_0); + if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE)) + SignalException (Trap, instruction_0); } @@ -3273,19 +3400,14 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: { if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE)) - SignalException(Trap, instruction_0); + SignalException (Trap, instruction_0); } @@ -3294,19 +3416,14 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: { if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]) - SignalException(Trap, instruction_0); + SignalException (Trap, instruction_0); } @@ -3315,82 +3432,78 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: { - if (GPR[RS] != GPR[RT]) - SignalException(Trap, instruction_0); + if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) + SignalException (Trap, instruction_0); } 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI -"tne r, " +"tnei r, " *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 -*r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: { - if (GPR[RS] != EXTEND16 (IMMEDIATE)) - SignalException(Trap, instruction_0); + if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE)) + SignalException (Trap, instruction_0); } -000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR +:function:::void:do_xor:int rs, int rt, int rd +{ + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + GPR[rd] = GPR[rs] ^ GPR[rt]; + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR "xor r, r, r" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - GPR[RD] = GPR[RS] ^ GPR[RT]; + do_xor (SD_, RS, RT, RD); } +:function:::void:do_xori:int rs, int rt, unsigned16 immediate +{ + TRACE_ALU_INPUT2 (GPR[rs], immediate); + GPR[rt] = GPR[rs] ^ immediate; + TRACE_ALU_RESULT (GPR[rt]); +} + 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI -"xori r, r, " +"xori r, r, %#lx" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - GPR[RT] = GPR[RS] ^ IMMEDIATE; + do_xori (SD_, RS, RT, IMMEDIATE); } @@ -3454,782 +3567,745 @@ } +// Helpers: +// +// Check that the given FPU format is usable, and signal a +// ReservedInstruction exception if not. +// + +// check_fmt checks that the format is single or double. +:function:::void:check_fmt:int fmt, instruction_word insn +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: +*r3900: +{ + if ((fmt != fmt_single) && (fmt != fmt_double)) + SignalException (ReservedInstruction, insn); +} + +// check_fmt_p checks that the format is single, double, or paired single. +:function:::void:check_fmt_p:int fmt, instruction_word insn +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mips32: +*vr4100: +*vr5000: +*r3900: +{ + /* None of these ISAs support Paired Single, so just fall back to + the single/double check. */ + check_fmt (SD_, fmt, insn); +} + +:function:::void:check_fmt_p:int fmt, instruction_word insn +*mipsV: +*mips64: +{ +#if 0 /* XXX FIXME: FP code doesn't yet support paired single ops. */ + if ((fmt != fmt_single) && (fmt != fmt_double) + && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0))) + SignalException (ReservedInstruction, insn); +#else + check_fmt (SD_, fmt, insn); +#endif +} + + +// Helper: +// +// Check that the FPU is currently usable, and signal a CoProcessorUnusable +// exception if not. +// + +:function:::void:check_fpu: +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: +*r3900: +{ + if (! COP_Usable (1)) + SignalExceptionCoProcessorUnusable (1); +} + + 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt "abs.%s f, f" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int format = ((instruction >> 21) & 0x00000007); - { - if ((format != fmt_single) && (format != fmt_double)) - SignalException(ReservedInstruction,instruction); - else - StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format)); - } + int fmt = FMT; + check_fpu (SD_); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt)); } - -010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD +010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt "add.%s f, f, f" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int ft = ((instruction >> 16) & 0x0000001F); - int format = ((instruction >> 21) & 0x00000007); - { - if ((format != fmt_single) && (format != fmt_double)) - SignalException(ReservedInstruction, instruction); - else - StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format)); - } + int fmt = FMT; + check_fpu (SD_); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt)); } -// -// FIXME: This does not correctly resolve mipsI-mipsIV differences. -// + // BC1F // BC1FL // BC1T // BC1TL -010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1 -"bc1%s%s ":CC == 0 -"bc1%s%s , " + +010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a +"bc1%s%s " *mipsI: *mipsII: *mipsIII: +{ + check_fpu (SD_); + check_branch_bug (); + TRACE_BRANCH_INPUT (PREVCOC1()); + if (PREVCOC1() == TF) + { + address_word dest = NIA + (EXTEND16 (OFFSET) << 2); + TRACE_BRANCH_RESULT (dest); + mark_branch_bug (dest); + DELAY_SLOT (dest); + } + else if (ND) + { + TRACE_BRANCH_RESULT (0); + NULLIFY_NEXT_INSTRUCTION (); + } + else + { + TRACE_BRANCH_RESULT (NIA); + } +} + +010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b +"bc1%s%s ":CC == 0 +"bc1%s%s , " *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +#*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)(((instruction >> 0) & 0x0000FFFF) << 2),18); - int boolean = ((instruction >> 16) & 0x00000001); - int likely = ((instruction >> 17) & 0x00000001); - int condition_code = ((instruction >> 18) & 0x00000007); - { - if (condition_code != 0) - SignalException(ReservedInstruction,instruction); - else { - int condition = (PREVCOC1() == boolean); - /* NOTE: The branch occurs AFTER the next instruction has been executed */ - if (condition) { - DELAY_SLOT (PC + offset); - } - else if (likely) { - NULLIFY_NEXT_INSTRUCTION (); - } + check_fpu (SD_); + check_branch_bug (); + if (GETFCC(CC) == TF) + { + address_word dest = NIA + (EXTEND16 (OFFSET) << 2); + mark_branch_bug (dest); + DELAY_SLOT (dest); + } + else if (ND) + { + NULLIFY_NEXT_INSTRUCTION (); } - } } -// -// FIXME: This does not correctly differentiate between mips* -// -010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt -"c.%s.%s f, f":CC == 0 -"c.%s.%s , f, f" +010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta +"c.%s.%s f, f" *mipsI: *mipsII: *mipsIII: +{ + int fmt = FMT; + check_fpu (SD_); + check_fmt_p (SD_, fmt, instruction_0); + Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0); + TRACE_ALU_RESULT (ValueFCR (31)); +} + +010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb +"c.%s.%s f, f":CC == 0 +"c.%s.%s , f, f" *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - int cmpflags = ((instruction >> 0) & 0x0000000F); - int condition_code = ((instruction >> 8) & 0x00000007); - int fs = ((instruction >> 11) & 0x0000001F); - int ft = ((instruction >> 16) & 0x0000001F); - int format = ((instruction >> 21) & 0x00000007); - if (condition_code != 0) - { - SignalException(ReservedInstruction,instruction); - } - else - { - if ((format != fmt_single) && (format != fmt_double)) - SignalException(ReservedInstruction,instruction); - else { - if (condition_code != 0) - SignalException(ReservedInstruction,instruction); - else - { - int ignore = 0; - int less = 0; - int equal = 0; - int unordered = 1; - unsigned64 ofs = ValueFPR(fs,format); - unsigned64 oft = ValueFPR(ft,format); - if (NaN(ofs,format) || NaN(oft,format)) { - if (FCSR & FP_ENABLE(IO)) { - FCSR |= FP_CAUSE(IO); - SignalExceptionFPE(); - ignore = 1; - } - } else { - less = Less(ofs,oft,format); - equal = Equal(ofs,oft,format); - unordered = 0; - } - if (!ignore) { - int condition = (((cmpflags & (1 << 2)) && less) || ((cmpflags & (1 << 1)) && equal) || ((cmpflags & (1 << 0)) && unordered)); - SETFCC(condition_code,condition); - } - } - } - } + int fmt = FMT; + check_fpu (SD_); + check_fmt_p (SD_, fmt, instruction_0); + Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC); + TRACE_ALU_RESULT (ValueFCR (31)); } -010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt +010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt "ceil.l.%s f, f" *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int format = ((instruction >> 21) & 0x00000007); - { - if ((format != fmt_single) && (format != fmt_double)) - SignalException(ReservedInstruction,instruction); - else - StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long)); - } + int fmt = FMT; + check_fpu (SD_); + check_fmt (SD_, fmt, instruction_0); + StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt, + fmt_long)); } -010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W +010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W +"ceil.w.%s f, f" *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int format = ((instruction >> 21) & 0x00000007); - { - if ((format != fmt_single) && (format != fmt_double)) - SignalException(ReservedInstruction,instruction); - else - StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word)); - } + int fmt = FMT; + check_fpu (SD_); + check_fmt (SD_, fmt, instruction_0); + StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt, + fmt_word)); } -// CFC1 -// CTC1 -01000100,x,10,kkkkk,vvvvv,00000000000:COP1S:32::CxC1 +010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a +"cfc1 r, f" *mipsI: *mipsII: *mipsIII: +{ + check_fpu (SD_); + if (FS == 0) + PENDING_FILL (RT, EXTEND32 (FCR0)); + else if (FS == 31) + PENDING_FILL (RT, EXTEND32 (FCR31)); + /* else NOP */ +} + +010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b +"cfc1 r, f" *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - int fs = ((instruction >> 11) & 0x0000001F); - int ft = ((instruction >> 16) & 0x0000001F); - int to = ((instruction >> 23) & 0x00000001); - { - if (to) { - if (fs == 0) { - PENDING_FILL((fs + FCR0IDX),VL4_8(GPR[ft])); - } else if (fs == 31) { - PENDING_FILL((fs + FCR31IDX),VL4_8(GPR[ft])); - } /* else NOP */ - PENDING_FILL(COCIDX,0); /* special case */ - } else { /* control from */ - if (fs == 0) { - PENDING_FILL(ft,SIGNEXTEND(FCR0,32)); - } else if (fs == 31) { - PENDING_FILL(ft,SIGNEXTEND(FCR31,32)); - } /* else NOP */ + check_fpu (SD_); + if (FS == 0 || FS == 31) + { + unsigned_word fcr = ValueFCR (FS); + TRACE_ALU_INPUT1 (fcr); + GPR[RT] = fcr; } - } + /* else NOP */ + TRACE_ALU_RESULT (GPR[RT]); +} + +010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c +"cfc1 r, f" +*mipsV: +*mips32: +*mips64: +{ + check_fpu (SD_); + if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31) + { + unsigned_word fcr = ValueFCR (FS); + TRACE_ALU_INPUT1 (fcr); + GPR[RT] = fcr; + } + /* else NOP */ + TRACE_ALU_RESULT (GPR[RT]); +} + +010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a +"ctc1 r, f" +*mipsI: +*mipsII: +*mipsIII: +{ + check_fpu (SD_); + if (FS == 31) + PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT])); + /* else NOP */ +} + +010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b +"ctc1 r, f" +*mipsIV: +*vr4100: +*vr5000: +*r3900: +{ + check_fpu (SD_); + TRACE_ALU_INPUT1 (GPR[RT]); + if (FS == 31) + StoreFCR (FS, GPR[RT]); + /* else NOP */ +} + +010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c +"ctc1 r, f" +*mipsV: +*mips32: +*mips64: +{ + check_fpu (SD_); + TRACE_ALU_INPUT1 (GPR[RT]); + if (FS == 25 || FS == 26 || FS == 28 || FS == 31) + StoreFCR (FS, GPR[RT]); + /* else NOP */ } // // FIXME: Does not correctly differentiate between mips* // -010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt +010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt "cvt.d.%s f, f" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int format = ((instruction >> 21) & 0x00000007); - { - if ((format == fmt_double) | 0) - SignalException(ReservedInstruction,instruction); - else - StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double)); - } + int fmt = FMT; + check_fpu (SD_); + if ((fmt == fmt_double) | 0) + SignalException (ReservedInstruction, instruction_0); + StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt, + fmt_double)); } -010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt +010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt "cvt.l.%s f, f" *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int format = ((instruction >> 21) & 0x00000007); - { - if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word))) - SignalException(ReservedInstruction,instruction); - else - StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long)); - } + int fmt = FMT; + check_fpu (SD_); + if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word))) + SignalException (ReservedInstruction, instruction_0); + StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt, + fmt_long)); } // // FIXME: Does not correctly differentiate between mips* // -010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt +010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt "cvt.s.%s f, f" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int format = ((instruction >> 21) & 0x00000007); - { - if ((format == fmt_single) | 0) - SignalException(ReservedInstruction,instruction); - else - StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single)); - } + int fmt = FMT; + check_fpu (SD_); + if ((fmt == fmt_single) | 0) + SignalException (ReservedInstruction, instruction_0); + StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt, + fmt_single)); } -010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt +010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt "cvt.w.%s f, f" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int format = ((instruction >> 21) & 0x00000007); - { - if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word))) - SignalException(ReservedInstruction,instruction); - else - StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word)); - } + int fmt = FMT; + check_fpu (SD_); + if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word))) + SignalException (ReservedInstruction, instruction_0); + StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt, + fmt_word)); } -010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt +010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt "div.%s f, f, f" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int ft = ((instruction >> 16) & 0x0000001F); - int format = ((instruction >> 21) & 0x00000007); - { - if ((format != fmt_single) && (format != fmt_double)) - SignalException(ReservedInstruction,instruction); - else - StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format)); - } + int fmt = FMT; + check_fpu (SD_); + check_fmt (SD_, fmt, instruction_0); + StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt)); } -// DMFC1 -// DMTC1 -01000100,x,01,5.FT,vvvvv,00000000000:COP1S:64::DMxC1 +010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a +"dmfc1 r, f" *mipsIII: +{ + unsigned64 v; + check_fpu (SD_); + check_u64 (SD_, instruction_0); + if (SizeFGR () == 64) + v = FGR[FS]; + else if ((FS & 0x1) == 0) + v = SET64HI (FGR[FS+1]) | FGR[FS]; + else + v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0; + PENDING_FILL (RT, v); + TRACE_ALU_RESULT (v); +} + +010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b +"dmfc1 r, f" *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - int fs = ((instruction >> 11) & 0x0000001F); - int ft = ((instruction >> 16) & 0x0000001F); - int to = ((instruction >> 23) & 0x00000001); - { - if (to) { - if (SizeFGR() == 64) { - PENDING_FILL((fs + FGRIDX),GPR[ft]); - } else - if ((fs & 0x1) == 0) - { - PENDING_FILL(((fs + 1) + FGRIDX),VH4_8(GPR[ft])); - PENDING_FILL((fs + FGRIDX),VL4_8(GPR[ft])); - } - } else { - if (SizeFGR() == 64) { - PENDING_FILL(ft,FGR[fs]); - } else - if ((fs & 0x1) == 0) { - PENDING_FILL(ft,(SET64HI(FGR[fs+1]) | FGR[fs])); - } else { - PENDING_FILL(ft,SET64HI(0xDEADC0DE) | 0xBAD0BAD0); - } + check_fpu (SD_); + check_u64 (SD_, instruction_0); + if (SizeFGR () == 64) + GPR[RT] = FGR[FS]; + else if ((FS & 0x1) == 0) + GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS]; + else + GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0; + TRACE_ALU_RESULT (GPR[RT]); +} + + +010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a +"dmtc1 r, f" +*mipsIII: +{ + unsigned64 v; + check_fpu (SD_); + check_u64 (SD_, instruction_0); + if (SizeFGR () == 64) + PENDING_FILL ((FS + FGR_BASE), GPR[RT]); + else if ((FS & 0x1) == 0) + { + PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT])); + PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT])); } - } + else + Unpredictable (); + TRACE_FP_RESULT (GPR[RT]); +} + +010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b +"dmtc1 r, f" +*mipsIV: +*mipsV: +*mips64: +*vr4100: +*vr5000: +*r3900: +{ + check_fpu (SD_); + check_u64 (SD_, instruction_0); + if (SizeFGR () == 64) + StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]); + else if ((FS & 0x1) == 0) + StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]); + else + Unpredictable (); } -010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt +010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt "floor.l.%s f, f" *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int format = ((instruction >> 21) & 0x00000007); - { - if ((format != fmt_single) && (format != fmt_double)) - SignalException(ReservedInstruction,instruction); - else - StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long)); - } + int fmt = FMT; + check_fpu (SD_); + check_fmt (SD_, fmt, instruction_0); + StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt, + fmt_long)); } -010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt +010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt "floor.w.%s f, f" *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int format = ((instruction >> 21) & 0x00000007); - { - if ((format != fmt_single) && (format != fmt_double)) - SignalException(ReservedInstruction,instruction); - else - StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word)); - } + int fmt = FMT; + check_fpu (SD_); + check_fmt (SD_, fmt, instruction_0); + StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt, + fmt_word)); +} + + +110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1 +"ldc1 f, (r)" +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: +*r3900: +{ + check_fpu (SD_); + COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET))); } -// LDC1 -110101,5.BASE,5.FT,16.OFFSET:COP1:32::LDC1 - - -010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1 +010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1 "ldxc1 f, r(r)" *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips64: +*vr5000: { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((unsigned64)op1 + op2); - address_word paddr; - int uncached; - if ((vaddr & 7) != 0) - SignalExceptionAddressLoad(); - else - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); - COP_LD(1,destreg,memval);; - } - } - } + check_fpu (SD_); + check_u64 (SD_, instruction_0); + COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX])); } -// LWC1 -110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1 - -010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1 -"lwxc1 f, r(r)" +110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1 +"lwc1 f, (r)" +*mipsI: +*mipsII: +*mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: +*r3900: { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((unsigned64)op1 + op2); - address_word paddr; - int uncached; - if ((vaddr & 3) != 0) - SignalExceptionAddressLoad(); - else - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int shift = 2; - unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); - unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); - LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); - byte = ((vaddr & mask) ^ (bigend << shift)); - COP_LW(1,destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF)); - } - } - } + check_fpu (SD_); + COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET))); } - -// -// FIXME: Not correct for mips* -// -010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32::MADD.D -"madd.d f, f, f, f" +010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1 +"lwxc1 f, r(r)" *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips64: +*vr5000: { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int ft = ((instruction >> 16) & 0x0000001F); - int fr = ((instruction >> 21) & 0x0000001F); - { - StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double)); - } + check_fpu (SD_); + check_u64 (SD_, instruction_0); + COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX])); } -010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32::MADD.S -"madd.s f, f, f, f" + +010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT:COP1X:64,f::MADD.fmt +"madd.%s f, f, f, f" *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips64: +*vr5000: { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int ft = ((instruction >> 16) & 0x0000001F); - int fr = ((instruction >> 21) & 0x0000001F); - { - StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single)); - } + int fmt = FMT; + check_fpu (SD_); + check_u64 (SD_, instruction_0); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt), + ValueFPR (FR, fmt), fmt)); } -// MFC1 -010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1 -"mc1 r, f" +010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a +"mfc1 r, f" *mipsI: *mipsII: *mipsIII: +{ + unsigned64 v; + check_fpu (SD_); + v = EXTEND32 (FGR[FS]); + PENDING_FILL (RT, v); + TRACE_ALU_RESULT (v); +} + +010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b +"mfc1 r, f" *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 -{ - unsigned32 instruction = instruction_0; - int fs = ((instruction >> 11) & 0x0000001F); - int ft = ((instruction >> 16) & 0x0000001F); - int to = ((instruction >> 23) & 0x00000001); - { - if (to) { - if (SizeFGR() == 64) { - PENDING_FILL ((fs + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[ft]))); - } else { - PENDING_FILL ((fs + FGRIDX), VL4_8(GPR[ft])); - } - } else { - PENDING_FILL (ft, SIGNEXTEND(FGR[fs],32)); - } - } +{ + check_fpu (SD_); + GPR[RT] = EXTEND32 (FGR[FS]); + TRACE_ALU_RESULT (GPR[RT]); } -010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt +010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt "mov.%s f, f" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int format = ((instruction >> 21) & 0x00000007); - { - StoreFPR(destreg,format,ValueFPR(fs,format)); - } + int fmt = FMT; + check_fpu (SD_); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (FD, fmt, ValueFPR (FS, fmt)); } // MOVF -000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf +// MOVT +000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf "mov%s r, r, " *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr5000: { + check_fpu (SD_); if (GETFCC(CC) == TF) GPR[RD] = GPR[RS]; } // MOVF.fmt -010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt +// MOVT.fmt +010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt "mov%s.%s f, f, " *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr5000: { - unsigned32 instruction = instruction_0; - int format = ((instruction >> 21) & 0x00000007); + int fmt = FMT; + check_fpu (SD_); { if (GETFCC(CC) == TF) - StoreFPR (FD, format, ValueFPR (FS, format)); + StoreFPR (FD, fmt, ValueFPR (FS, fmt)); else - StoreFPR (FD, format, ValueFPR (FD, format)); + StoreFPR (FD, fmt, ValueFPR (FD, fmt)); } } -010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt +010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt +"movn.%s f, f, r" *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr5000: { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int format = ((instruction >> 21) & 0x00000007); - { - StoreFPR(destreg,format,ValueFPR(fs,format)); - } + check_fpu (SD_); + if (GPR[RT] != 0) + StoreFPR (FD, FMT, ValueFPR (FS, FMT)); + else + StoreFPR (FD, FMT, ValueFPR (FD, FMT)); } @@ -4240,448 +4316,357 @@ -010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt +010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt "movz.%s f, f, r" *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr5000: { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int format = ((instruction >> 21) & 0x00000007); - { - StoreFPR(destreg,format,ValueFPR(fs,format)); - } + check_fpu (SD_); + if (GPR[RT] == 0) + StoreFPR (FD, FMT, ValueFPR (FS, FMT)); + else + StoreFPR (FD, FMT, ValueFPR (FD, FMT)); } -// MSUB.fmt -010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D -"msub.d f, f, f, f" +010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT:COP1X:64,f::MSUB.fmt +"msub.%s f, f, f, f" *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips64: +*vr5000: { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int ft = ((instruction >> 16) & 0x0000001F); - int fr = ((instruction >> 21) & 0x0000001F); - { - StoreFPR(destreg,fmt_double,(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double)); - } + int fmt = FMT; + check_fpu (SD_); + check_u64 (SD_, instruction_0); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), + ValueFPR (FR, fmt), fmt)); } -// MSUB.fmt -010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S -"msub.s f, f, f, f" +010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a +"mtc1 r, f" +*mipsI: +*mipsII: +*mipsIII: +{ + check_fpu (SD_); + if (SizeFGR () == 64) + PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT]))); + else + PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT])); + TRACE_FP_RESULT (GPR[RT]); +} + +010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b +"mtc1 r, f" *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: +*r3900: { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int ft = ((instruction >> 16) & 0x0000001F); - int fr = ((instruction >> 21) & 0x0000001F); - { - StoreFPR(destreg,fmt_single,(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single)); - } + check_fpu (SD_); + StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT])); } -// MTC1 see MxC1 - - -010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt +010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt "mul.%s f, f, f" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int ft = ((instruction >> 16) & 0x0000001F); - int format = ((instruction >> 21) & 0x00000007); - { - if ((format != fmt_single) && (format != fmt_double)) - SignalException(ReservedInstruction,instruction); - else - StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format)); - } + int fmt = FMT; + check_fpu (SD_); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt)); } -010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt +010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt "neg.%s f, f" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int format = ((instruction >> 21) & 0x00000007); - { - if ((format != fmt_single) && (format != fmt_double)) - SignalException(ReservedInstruction,instruction); - else - StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format)); - } -} - - -// NMADD.fmt -010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D -"nmadd.d f, f, f, f" -*mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -{ - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int ft = ((instruction >> 16) & 0x0000001F); - int fr = ((instruction >> 21) & 0x0000001F); - { - StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double)); - } -} - - -// NMADD.fmt -010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S -"nmadd.s f, f, f, f" -*mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int ft = ((instruction >> 16) & 0x0000001F); - int fr = ((instruction >> 21) & 0x0000001F); - { - StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single)); - } + int fmt = FMT; + check_fpu (SD_); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt)); } -// NMSUB.fmt -010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D -"nmsub.d f, f, f, f" +010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT:COP1X:64,f::NMADD.fmt +"nmadd.%s f, f, f, f" *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 +*mipsV: +*mips64: +*vr5000: { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int ft = ((instruction >> 16) & 0x0000001F); - int fr = ((instruction >> 21) & 0x0000001F); - { - StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double)); - } + int fmt = FMT; + check_fpu (SD_); + check_u64 (SD_, instruction_0); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt), + ValueFPR (FR, fmt), fmt)); } -// NMSUB.fmt -010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S -"nmsub.s f, f, f, f" +010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT:COP1X:64,f::NMSUB.fmt +"nmsub.%s f, f, f, f" *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 +*mipsV: +*mips64: +*vr5000: { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int ft = ((instruction >> 16) & 0x0000001F); - int fr = ((instruction >> 21) & 0x0000001F); - { - StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single)); - } + int fmt = FMT; + check_fpu (SD_); + check_u64 (SD_, instruction_0); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), + ValueFPR (FR, fmt), fmt)); } -010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX +010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX "prefx , r(r)" *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 +*mipsV: +*mips64: +*vr5000: { - unsigned32 instruction = instruction_0; - int fs = ((instruction >> 11) & 0x0000001F); - signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; + address_word base = GPR[BASE]; + address_word index = GPR[INDEX]; { - address_word vaddr = ((unsigned64)op1 + (unsigned64)op2); + address_word vaddr = loadstore_ea (SD_, base, index); address_word paddr; int uncached; if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - Prefetch(uncached,paddr,vaddr,isDATA,fs); + Prefetch(uncached,paddr,vaddr,isDATA,HINT); } } -010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt -*mipsIV: +010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt "recip.%s f, f" -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 +*mipsIV: +*mipsV: +*mips64: +*vr5000: { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int format = ((instruction >> 21) & 0x00000007); - { - if ((format != fmt_single) && (format != fmt_double)) - SignalException(ReservedInstruction,instruction); - else - StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format)); - } + int fmt = FMT; + check_fpu (SD_); + check_fmt (SD_, fmt, instruction_0); + StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt)); } -010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt +010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt "round.l.%s f, f" *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int format = ((instruction >> 21) & 0x00000007); - { - if ((format != fmt_single) && (format != fmt_double)) - SignalException(ReservedInstruction,instruction); - else - StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long)); - } + int fmt = FMT; + check_fpu (SD_); + check_fmt (SD_, fmt, instruction_0); + StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt, + fmt_long)); } -010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt +010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt "round.w.%s f, f" *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int format = ((instruction >> 21) & 0x00000007); - { - if ((format != fmt_single) && (format != fmt_double)) - SignalException(ReservedInstruction,instruction); - else - StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word)); - } + int fmt = FMT; + check_fpu (SD_); + check_fmt (SD_, fmt, instruction_0); + StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt, + fmt_word)); } -010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt -*mipsIV: +010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt "rsqrt.%s f, f" -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 +*mipsIV: +*mipsV: +*mips64: +*vr5000: { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int format = ((instruction >> 21) & 0x00000007); - { - if ((format != fmt_single) && (format != fmt_double)) - SignalException(ReservedInstruction,instruction); - else - StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format)); - } + int fmt = FMT; + check_fpu (SD_); + check_fmt (SD_, fmt, instruction_0); + StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt)); } -// SDC1 +111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1 +"sdc1 f, (r)" +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: +*r3900: +{ + check_fpu (SD_); + do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT)); +} -010011,5.RS,5.RT,vvvvv,00000001001:COP1X:64::SDXC1 +010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1 +"sdxc1 f, r(r)" *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips64: +*vr5000: { - unsigned32 instruction = instruction_0; - int fs = ((instruction >> 11) & 0x0000001F); - signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; - { - address_word vaddr = ((unsigned64)op1 + op2); - address_word paddr; - int uncached; - if ((vaddr & 7) != 0) - SignalExceptionAddressStore(); - else - { - if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - memval = (unsigned64)COP_SD(1,fs); - { - StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); - } - } - } - } + check_fpu (SD_); + check_u64 (SD_, instruction_0); + do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS)); } -010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt +010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt "sqrt.%s f, f" *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int format = ((instruction >> 21) & 0x00000007); - { - if ((format != fmt_single) && (format != fmt_double)) - SignalException(ReservedInstruction,instruction); - else - StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format))); - } + int fmt = FMT; + check_fpu (SD_); + check_fmt (SD_, fmt, instruction_0); + StoreFPR (FD, fmt, (SquareRoot (ValueFPR (FS, fmt), fmt))); } -010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt +010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt "sub.%s f, f, f" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int ft = ((instruction >> 16) & 0x0000001F); - int format = ((instruction >> 21) & 0x00000007); + int fmt = FMT; + check_fpu (SD_); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt)); +} + + + +111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1 +"swc1 f, (r)" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: +*r3900: +{ + address_word base = GPR[BASE]; + address_word offset = EXTEND16 (OFFSET); + check_fpu (SD_); { - if ((format != fmt_single) && (format != fmt_double)) - SignalException(ReservedInstruction,instruction); + address_word vaddr = loadstore_ea (SD_, base, offset); + address_word paddr; + int uncached; + if ((vaddr & 3) != 0) + { + SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal); + } else - StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format)); + { + if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) + { + uword64 memval = 0; + uword64 memval1 = 0; + uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); + address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0); + address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0); + unsigned int byte; + paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); + byte = ((vaddr & mask) ^ bigendiancpu); + memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte)); + StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); + } + } } } -// SWC1 - - -010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1 +010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1 "swxc1 f, r(r)" *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips64: +*vr5000: { - unsigned32 instruction = instruction_0; - int fs = ((instruction >> 11) & 0x0000001F); - signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; + + address_word base = GPR[BASE]; + address_word index = GPR[INDEX]; + check_fpu (SD_); + check_u64 (SD_, instruction_0); { - address_word vaddr = ((unsigned64)op1 + op2); + address_word vaddr = loadstore_ea (SD_, base, index); address_word paddr; int uncached; if ((vaddr & 3) != 0) - SignalExceptionAddressStore(); + { + SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal); + } else { if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) @@ -4692,7 +4677,7 @@ unsigned int byte; paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); - memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte)); + memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte)); { StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); } @@ -4702,60 +4687,41 @@ } -010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt +010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt "trunc.l.%s f, f" *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int format = ((instruction >> 21) & 0x00000007); - { - if ((format != fmt_single) && (format != fmt_double)) - SignalException(ReservedInstruction,instruction); - else - StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long)); - } + int fmt = FMT; + check_fpu (SD_); + check_fmt (SD_, fmt, instruction_0); + StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt, + fmt_long)); } -010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W +010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W "trunc.w.%s f, f" *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - int destreg = ((instruction >> 6) & 0x0000001F); - int fs = ((instruction >> 11) & 0x0000001F); - int format = ((instruction >> 21) & 0x00000007); - { - if ((format != fmt_single) && (format != fmt_double)) - SignalException(ReservedInstruction,instruction); - else - StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word)); - } + int fmt = FMT; + check_fpu (SD_); + check_fmt (SD_, fmt, instruction_0); + StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt, + fmt_word)); } @@ -4772,12 +4738,19 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: + +010000,01000,00000,16.OFFSET:COP0:32::BC0F +"bc0f " +// stub needed for eCos as tx39 hardware bug workaround +*r3900: +{ + /* do nothing */ +} 010000,01000,00010,16.OFFSET:COP0:32::BC0FL @@ -4786,12 +4759,11 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: 010000,01000,00001,16.OFFSET:COP0:32::BC0T @@ -4800,10 +4772,10 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 - +*mipsV: +*mips32: +*mips64: +*vr4100: 010000,01000,00011,16.OFFSET:COP0:32::BC0TL @@ -4812,80 +4784,106 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE +"cache , (r)" *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: *r3900: -// start-sanitize-tx19 -*tx19: -// end-sanitize-tx19 { - unsigned32 instruction = instruction_0; - signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); - int hint = ((instruction >> 16) & 0x0000001F); - signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; + address_word base = GPR[BASE]; + address_word offset = EXTEND16 (OFFSET); { - address_word vaddr = (op1 + offset); + address_word vaddr = loadstore_ea (SD_, base, offset); address_word paddr; int uncached; if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - CacheOp(hint,vaddr,paddr,instruction); + CacheOp(OP,vaddr,paddr,instruction_0); } } -010000,10000,000000000000000,111001:COP0:32::DI +010000,1,0000000000000000000,111001:COP0:32::DI "di" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*vr4100: +*vr5000: + + +010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0 +"dmfc0 r, r" +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +{ + check_u64 (SD_, instruction_0); + DecodeCoproc (instruction_0); +} + + +010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0 +"dmtc0 r, r" +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +{ + check_u64 (SD_, instruction_0); + DecodeCoproc (instruction_0); +} -010000,10000,000000000000000,111000:COP0:32::EI +010000,1,0000000000000000000,111000:COP0:32::EI "ei" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips64: +*vr4100: +*vr5000: -010000,10000,000000000000000,011000:COP0:32::ERET +010000,1,0000000000000000000,011000:COP0:32::ERET "eret" *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: +{ + if (SR & status_ERL) + { + /* Oops, not yet available */ + sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported"); + NIA = EPC; + SR &= ~status_ERL; + } + else + { + NIA = EPC; + SR &= ~status_EXL; + } +} 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0 @@ -4894,13 +4892,17 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 - +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: +*r3900: +{ + TRACE_ALU_INPUT0 (); + DecodeCoproc (instruction_0); + TRACE_ALU_RESULT (GPR[RT]); +} 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0 "mtc0 r, r # " @@ -4908,174 +4910,104 @@ *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: +*r3900: +{ + DecodeCoproc (instruction_0); +} + + +010000,1,0000000000000000000,010000:COP0:32::RFE +"rfe" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*vr4100: +*vr5000: +*r3900: +{ + DecodeCoproc (instruction_0); +} + + +0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz +"cop " +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips64: +*vr4100: +*r3900: +{ + DecodeCoproc (instruction_0); +} + -010000,10000,000000000000000,001000:COP0:32::TLBP +010000,1,0000000000000000000,001000:COP0:32::TLBP "tlbp" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: -010000,10000,000000000000000,000001:COP0:32::TLBR +010000,1,0000000000000000000,000001:COP0:32::TLBR "tlbr" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: -010000,10000,000000000000000,000010:COP0:32::TLBWI +010000,1,0000000000000000000,000010:COP0:32::TLBWI "tlbwi" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: -010000,10000,000000000000000,000110:COP0:32::TLBWR +010000,1,0000000000000000000,000110:COP0:32::TLBWR "tlbwr" *mipsI: *mipsII: *mipsIII: *mipsIV: -// start-sanitize-vr5400 -*vr5400: -// end-sanitize-vr5400 -// start-sanitize-r5900 -*r5900: -// end-sanitize-r5900 +*mipsV: +*mips32: +*mips64: +*vr4100: +*vr5000: :include:::m16.igen -// start-sanitize-vr5400 -:include::vr5400:vr5400.igen -// end-sanitize-vr5400 -// start-sanitize-r5900 -:include::r5900:r5900.igen -// end-sanitize-r5900 +:include:::mdmx.igen +:include:::sb1.igen +:include:::tx.igen +:include:::vr.igen -// start-sanitize-cygnus-never - -// // FIXME FIXME FIXME What is this instruction? -// 111011,5.RS,5.RT,16.OFFSET:NORMAL:32:: -// *mipsI: -// *mipsII: -// *mipsIII: -// *mipsIV: -// // start-sanitize-r5900 -// *r5900: -// // end-sanitize-r5900 -// *r3900: -// // start-sanitize-tx19 -// *tx19: -// // end-sanitize-tx19 -// { -// unsigned32 instruction = instruction_0; -// signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); -// signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; -// signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; -// { -// if (CoProcPresent(3)) -// SignalException(CoProcessorUnusable); -// else -// SignalException(ReservedInstruction,instruction); -// } -// } - -// end-sanitize-cygnus-never -// start-sanitize-cygnus-never - -// // FIXME FIXME FIXME What is this? -// 11100,******,00001:RR:16::SDBBP -// *mips16: -// { -// unsigned32 instruction = instruction_0; -// if (have_extendval) -// SignalException (ReservedInstruction, instruction); -// { -// SignalException(DebugBreakPoint,instruction); -// } -// } - -// end-sanitize-cygnus-never -// start-sanitize-cygnus-never - -// // FIXME FIXME FIXME What is this? -// 000000,********************,001110:SPECIAL:32::SDBBP -// *r3900: -// { -// unsigned32 instruction = instruction_0; -// { -// SignalException(DebugBreakPoint,instruction); -// } -// } - -// end-sanitize-cygnus-never -// start-sanitize-cygnus-never - -// // FIXME FIXME FIXME This apparently belongs to the vr4100 which -// // isn't yet reconized by this simulator. -// 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16 -// *vr4100: -// { -// unsigned32 instruction = instruction_0; -// signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; -// signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; -// { -// CHECKHILO("Multiply-Add"); -// { -// unsigned64 temp = (op1 * op2); -// temp += (SET64HI(VL4_8(HI)) | VL4_8(LO)); -// LO = SIGNEXTEND((unsigned64)VL4_8(temp),32); -// HI = SIGNEXTEND((unsigned64)VH4_8(temp),32); -// } -// } -// } - -// end-sanitize-cygnus-never -// start-sanitize-cygnus-never - -// // FIXME FIXME FIXME This apparently belongs to the vr4100 which -// // isn't yet reconized by this simulator. -// 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16 -// *vr4100: -// { -// unsigned32 instruction = instruction_0; -// signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; -// signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; -// { -// CHECKHILO("Multiply-Add"); -// { -// unsigned64 temp = (op1 * op2); -// LO = LO + temp; -// } -// } -// } - -// start-sanitize-cygnus-never