X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fmips%2Fmips.igen;h=fece487e10d6a3a9844b8b59fd12fdd57125796e;hb=4c54fc26ed171989615301442435fa4dd3af9755;hp=e03f226e9e453f8d461bf53d1a749bfe84108fef;hpb=8612006bd764dee799659e34f29e76d8a2745f25;p=deliverable%2Fbinutils-gdb.git

diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index e03f226e9e..fece487e10 100644
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -1,9 +1,5 @@
 // -*- C -*-
 //
-// In mips.igen, the semantics for many of the instructions were created
-// using code generated by gencode.  Those semantic segments could be
-// greatly simplified.
-//
 //    <insn> ::=
 //        <insn-word> { "+" <insn-word> }
 //        ":" <format-name>
@@ -48,6 +44,8 @@
 :model:::mipsIII:mips4000:
 :model:::mipsIV:mips8000:
 :model:::mipsV:mipsisaV:
+:model:::mips32:mipsisa32:
+:model:::mips64:mipsisa64:
 
 //  Vendor ISAs:
 //
@@ -57,13 +55,25 @@
 //  (or which pre-date or use different encodings than the standard
 //  instructions) are (for the most part) in separate .igen files.
 :model:::vr4100:mips4100:		// vr.igen
+:model:::vr4120:mips4120:
 :model:::vr5000:mips5000:
+:model:::vr5400:mips5400:
+:model:::vr5500:mips5500:
 :model:::r3900:mips3900:		// tx.igen
 
 //  MIPS Application Specific Extensions (ASEs)
 //
 //  Instructions for the ASEs are in separate .igen files.
+//  ASEs add instructions on to a base ISA.
 :model:::mips16:mips16:			// m16.igen (and m16.dc)
+:model:::mips3d:mips3d:			// mips3d.igen
+:model:::mdmx:mdmx:			// mdmx.igen
+
+//  Vendor Extensions
+//
+//  Instructions specific to these extensions are in separate .igen files.
+//  Extensions add instructions on to a base ISA.
+:model:::sb1:sb1:			// sb1.igen
 
 
 // Pseudo instructions known by IGEN
@@ -121,6 +131,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
 *vr4100:
 *vr5000:
 *r3900:
@@ -128,6 +139,84 @@
   return base + offset;
 }
 
+:function:::address_word:loadstore_ea:address_word base, address_word offset
+*mips64:
+{
+#if 0 /* XXX FIXME: enable this only after some additional testing.  */
+  /* If in user mode and UX is not set, use 32-bit compatibility effective
+     address computations as defined in the MIPS64 Architecture for
+     Programmers Volume III, Revision 0.95, section 4.9.  */
+  if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
+      == (ksu_user << status_KSU_shift))
+    return (address_word)((signed32)base + (signed32)offset);
+#endif
+  return base + offset;
+}
+
+
+// Helper:
+//
+// Check that a 32-bit register value is properly sign-extended.
+// (See NotWordValue in ISA spec.)
+//
+
+:function:::int:not_word_value:unsigned_word value
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+  /* For historical simulator compatibility (until documentation is
+     found that makes these operations unpredictable on some of these
+     architectures), this check never returns true.  */
+  return 0;
+}
+
+:function:::int:not_word_value:unsigned_word value
+*mips32:
+{
+  /* On MIPS32, since registers are 32-bits, there's no check to be done.  */
+  return 0;
+}
+
+:function:::int:not_word_value:unsigned_word value
+*mips64:
+{
+  return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0));
+}
+
+
+// Helper:
+//
+// Handle UNPREDICTABLE operation behaviour.  The goal here is to prevent
+// theoretically portable code which invokes non-portable behaviour from
+// running with no indication of the portability issue.
+// (See definition of UNPREDICTABLE in ISA spec.)
+//
+
+:function:::void:unpredictable:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+}
+
+:function:::void:unpredictable:
+*mips32:
+*mips64:
+{
+  unpredictable_action (CPU, CIA);
+}
+
 
 // Helper:
 //
@@ -171,6 +260,8 @@
 }
 
 :function:::int:check_mt_hilo:hilo_history *history
+*mips32:
+*mips64:
 *r3900:
 {
   signed64 time = sim_events_time (SD);
@@ -186,6 +277,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -238,6 +331,8 @@
 // The r3900 mult and multu insns _can_ be exectuted immediatly after
 // a mf{hi,lo}
 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
+*mips32:
+*mips64:
 *r3900:
 {
   /* FIXME: could record the fact that a stall occured if we want */
@@ -256,6 +351,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -274,7 +371,7 @@
 // Helper:
 //
 // Check that the 64-bit instruction can currently be used, and signal
-// an ReservedInstruction exception if not.
+// a ReservedInstruction exception if not.
 //
 
 :function:::void:check_u64:instruction_word insn
@@ -284,16 +381,24 @@
 *vr4100:
 *vr5000:
 {
-  // On mips64, if UserMode check SR:PX & SR:UX bits.
   // The check should be similar to mips64 for any with PX/UX bit equivalents.
 }
 
+:function:::void:check_u64:instruction_word insn
+*mips64:
+{
+#if 0 /* XXX FIXME: enable this only after some additional testing.  */
+  if (UserMode && (SR & (status_UX|status_PX)) == 0)
+    SignalException (ReservedInstruction, insn);
+#endif
+}
+
 
 
 //
 // MIPS Architecture:
 //
-//        CPU Instruction Set (mipsI - mipsV)
+//        CPU Instruction Set (mipsI - mipsV, mips32, mips64)
 //
 
 
@@ -305,10 +410,14 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
+  if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+    Unpredictable ();
   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
   {
     ALU32_BEGIN (GPR[RS]);
@@ -327,10 +436,14 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
+  if (NotWordValue (GPR[RS]))
+    Unpredictable ();
   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
   {
     ALU32_BEGIN (GPR[RS]);
@@ -344,6 +457,8 @@
 
 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 {
+  if (NotWordValue (GPR[rs]))
+    Unpredictable ();
   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
   TRACE_ALU_RESULT (GPR[rt]);
@@ -356,6 +471,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -367,6 +484,8 @@
 
 :function:::void:do_addu:int rs, int rt, int rd
 {
+  if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
+    Unpredictable ();
   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
   TRACE_ALU_RESULT (GPR[rd]);
@@ -379,6 +498,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -402,6 +523,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -412,12 +535,14 @@
 
 
 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
-"and r<RT>, r<RS>, <IMMEDIATE>"
+"andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
 *mipsI:
 *mipsII:
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -436,15 +561,15 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
 }
@@ -457,15 +582,15 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
   else
@@ -481,15 +606,15 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   if ((signed_word) GPR[RS] >= 0)
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
 }
@@ -503,16 +628,18 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
+  if (RS == 31)
+    Unpredictable ();
   RA = (CIA + 8);
   if ((signed_word) GPR[RS] >= 0)
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
 }
@@ -525,18 +652,20 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
+  if (RS == 31)
+    Unpredictable ();
   RA = (CIA + 8);
   /* NOTE: The branch occurs AFTER the next instruction has been
      executed */
   if ((signed_word) GPR[RS] >= 0)
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
   else
@@ -551,15 +680,15 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   if ((signed_word) GPR[RS] >= 0)
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
   else
@@ -575,15 +704,15 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   if ((signed_word) GPR[RS] > 0)
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
 }
@@ -596,17 +725,17 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   /* NOTE: The branch occurs AFTER the next instruction has been
      executed */
   if ((signed_word) GPR[RS] > 0)
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
   else
@@ -622,17 +751,17 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   /* NOTE: The branch occurs AFTER the next instruction has been
      executed */
   if ((signed_word) GPR[RS] <= 0)
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
 }
@@ -645,15 +774,15 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   if ((signed_word) GPR[RS] <= 0)
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
   else
@@ -669,15 +798,15 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   if ((signed_word) GPR[RS] < 0)
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
 }
@@ -691,18 +820,20 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
+  if (RS == 31)
+    Unpredictable ();
   RA = (CIA + 8);
   /* NOTE: The branch occurs AFTER the next instruction has been
      executed */
   if ((signed_word) GPR[RS] < 0)
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
 }
@@ -715,16 +846,18 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
+  if (RS == 31)
+    Unpredictable ();
   RA = (CIA + 8);
   if ((signed_word) GPR[RS] < 0)
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
   else
@@ -739,17 +872,17 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   /* NOTE: The branch occurs AFTER the next instruction has been
      executed */
   if ((signed_word) GPR[RS] < 0)
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
   else
@@ -765,15 +898,15 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
 }
@@ -786,15 +919,15 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
   else
@@ -804,12 +937,14 @@
 
 
 000000,20.CODE,001101:SPECIAL:32::BREAK
-"break <CODE>"
+"break %#lx<CODE>"
 *mipsI:
 *mipsII:
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -829,15 +964,65 @@
         PC = cia - 4; /* reference the branch instruction */
       else
         PC = cia;
-      SignalException(BreakPoint, instruction_0);
+      SignalException (BreakPoint, instruction_0);
     }
 
   else
     {
       /* If we get this far, we're not an instruction reserved by the sim.  Raise
 	 the exception. */
-      SignalException(BreakPoint, instruction_0);
+      SignalException (BreakPoint, instruction_0);
+    }
+}
+
+
+
+011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
+"clo r<RD>, r<RS>"
+*mips32:
+*mips64:
+*vr5500:
+{
+  unsigned32 temp = GPR[RS];
+  unsigned32 i, mask;
+  if (RT != RD)
+    Unpredictable ();
+  if (NotWordValue (GPR[RS]))
+    Unpredictable ();
+  TRACE_ALU_INPUT1 (GPR[RS]);
+  for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
+    {
+      if ((temp & mask) == 0)
+	break;
+      mask >>= 1;
+    }
+  GPR[RD] = EXTEND32 (i);
+  TRACE_ALU_RESULT (GPR[RD]);
+}
+
+
+
+011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
+"clz r<RD>, r<RS>"
+*mips32:
+*mips64:
+*vr5500:
+{
+  unsigned32 temp = GPR[RS];
+  unsigned32 i, mask;
+  if (RT != RD)
+    Unpredictable ();
+  if (NotWordValue (GPR[RS]))
+    Unpredictable ();
+  TRACE_ALU_INPUT1 (GPR[RS]);
+  for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
+    {
+      if ((temp & mask) != 0)
+	break;
+      mask >>= 1;
     }
+  GPR[RD] = EXTEND32 (i);
+  TRACE_ALU_RESULT (GPR[RD]);
 }
 
 
@@ -847,6 +1032,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -867,6 +1053,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -894,6 +1081,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -915,6 +1103,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -924,6 +1113,54 @@
 
 
 
+011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
+"dclo r<RD>, r<RS>"
+*mips64:
+*vr5500:
+{
+  unsigned64 temp = GPR[RS];
+  unsigned32 i;
+  unsigned64 mask;
+  check_u64 (SD_, instruction_0);
+  if (RT != RD)
+    Unpredictable ();
+  TRACE_ALU_INPUT1 (GPR[RS]);
+  for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
+    {
+      if ((temp & mask) == 0)
+	break;
+      mask >>= 1;
+    }
+  GPR[RD] = EXTEND32 (i);
+  TRACE_ALU_RESULT (GPR[RD]);
+}
+
+
+
+011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
+"dclz r<RD>, r<RS>"
+*mips64:
+*vr5500:
+{
+  unsigned64 temp = GPR[RS];
+  unsigned32 i;
+  unsigned64 mask;
+  check_u64 (SD_, instruction_0);
+  if (RT != RD)
+    Unpredictable ();
+  TRACE_ALU_INPUT1 (GPR[RS]);
+  for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
+    {
+      if ((temp & mask) != 0)
+	break;
+      mask >>= 1;
+    }
+  GPR[RD] = EXTEND32 (i);
+  TRACE_ALU_RESULT (GPR[RD]);
+}
+
+
+
 :function:::void:do_ddiv:int rs, int rt
 {
   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
@@ -959,6 +1196,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -998,6 +1236,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1040,6 +1279,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1077,6 +1318,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1156,6 +1399,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 {
   check_u64 (SD_, instruction_0);
@@ -1183,6 +1427,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 {
   check_u64 (SD_, instruction_0);
@@ -1210,6 +1455,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1223,6 +1469,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1246,6 +1493,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1266,6 +1514,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1279,6 +1528,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1303,6 +1553,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1323,6 +1574,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1336,6 +1588,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1362,6 +1615,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1375,6 +1629,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1401,6 +1656,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1416,6 +1672,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1434,6 +1692,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1453,6 +1713,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1470,6 +1732,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1595,6 +1859,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1610,6 +1876,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1623,6 +1891,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1637,6 +1906,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1652,6 +1923,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1665,6 +1937,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1680,6 +1953,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1695,6 +1970,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1709,6 +1986,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1749,6 +2028,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1779,12 +2059,14 @@
 
 
 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
-"lui r<RT>, <IMMEDIATE>"
+"lui r<RT>, %#lx<IMMEDIATE>"
 *mipsI:
 *mipsII:
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1802,6 +2084,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1817,6 +2101,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1832,6 +2118,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1847,6 +2135,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1860,6 +2150,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -1868,6 +2159,46 @@
 }
 
 
+
+011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
+"madd r<RS>, r<RT>"
+*mips32:
+*mips64:
+*vr5500:
+{
+  signed64 temp;
+  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+  if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+    Unpredictable ();
+  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+  temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+          + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
+  LO = EXTEND32 (temp);
+  HI = EXTEND32 (VH4_8 (temp));
+  TRACE_ALU_RESULT2 (HI, LO);
+}
+
+
+
+011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
+"maddu r<RS>, r<RT>"
+*mips32:
+*mips64:
+*vr5500:
+{
+  unsigned64 temp;
+  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+  if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+    Unpredictable ();
+  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+  temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+          + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
+  LO = EXTEND32 (temp);
+  HI = EXTEND32 (VH4_8 (temp));
+  TRACE_ALU_RESULT2 (HI, LO);
+}
+
+
 :function:::void:do_mfhi:int rd
 {
   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
@@ -1883,6 +2214,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1907,6 +2240,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1920,10 +2255,15 @@
 "movn r<RD>, r<RS>, r<RT>"
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr5000:
 {
   if (GPR[RT] != 0)
-    GPR[RD] = GPR[RS];
+    {
+      GPR[RD] = GPR[RS];
+      TRACE_ALU_RESULT (GPR[RD]);
+    }
 }
 
 
@@ -1932,10 +2272,55 @@
 "movz r<RD>, r<RS>, r<RT>"
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr5000:
 {
   if (GPR[RT] == 0)
-    GPR[RD] = GPR[RS];
+    {
+      GPR[RD] = GPR[RS];
+      TRACE_ALU_RESULT (GPR[RD]);
+    }
+}
+
+
+
+011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
+"msub r<RS>, r<RT>"
+*mips32:
+*mips64:
+*vr5500:
+{
+  signed64 temp;
+  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+  if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+    Unpredictable ();
+  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+  temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+          - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
+  LO = EXTEND32 (temp);
+  HI = EXTEND32 (VH4_8 (temp));
+  TRACE_ALU_RESULT2 (HI, LO);
+}
+
+
+
+011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
+"msubu r<RS>, r<RT>"
+*mips32:
+*mips64:
+*vr5500:
+{
+  unsigned64 temp;
+  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+  if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+    Unpredictable ();
+  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+  temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+          - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
+  LO = EXTEND32 (temp);
+  HI = EXTEND32 (VH4_8 (temp));
+  TRACE_ALU_RESULT2 (HI, LO);
 }
 
 
@@ -1947,6 +2332,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1964,6 +2351,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -1974,10 +2363,30 @@
 
 
 
+011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
+"mul r<RD>, r<RS>, r<RT>"
+*mips32:
+*mips64:
+*vr5500:
+{
+  signed64 prod;
+  if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+    Unpredictable ();
+  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+  prod = (((signed64)(signed32) GPR[RS])
+          * ((signed64)(signed32) GPR[RT]));
+  GPR[RD] = EXTEND32 (VL4_8 (prod));
+  TRACE_ALU_RESULT (GPR[RD]);
+}
+
+
+
 :function:::void:do_mult:int rs, int rt, int rd
 {
   signed64 prod;
   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+  if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
+    Unpredictable ();
   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
   prod = (((signed64)(signed32) GPR[rs])
 	  * ((signed64)(signed32) GPR[rt]));
@@ -1995,6 +2404,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 {
   do_mult (SD_, RS, RT, 0);
@@ -2015,6 +2426,8 @@
 {
   unsigned64 prod;
   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+  if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
+    Unpredictable ();
   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
   prod = (((unsigned64)(unsigned32) GPR[rs])
 	  * ((unsigned64)(unsigned32) GPR[rt]));
@@ -2032,6 +2445,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 {
   do_multu (SD_, RS, RT, 0);
@@ -2061,6 +2476,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2083,6 +2500,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2100,12 +2519,14 @@
 }
 
 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
-"ori r<RT>, r<RS>, <IMMEDIATE>"
+"ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
 *mipsI:
 *mipsII:
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2118,6 +2539,8 @@
 "pref <HINT>, <OFFSET>(r<BASE>)"
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr5000:
 {
   address_word base = GPR[BASE];
@@ -2231,6 +2654,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2245,6 +2670,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -2286,6 +2713,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -2323,6 +2751,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -2337,6 +2766,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -2349,6 +2780,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -2362,6 +2794,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -2377,6 +2810,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2393,7 +2828,7 @@
   TRACE_ALU_RESULT (GPR[rd]);
 }
 
-000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
+000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
 "nop":RD == 0 && RT == 0 && SHIFT == 0
 "sll r<RD>, r<RT>, <SHIFT>"
 *mipsI:
@@ -2411,6 +2846,19 @@
     do_sll (SD_, RT, RD, SHIFT);
 }
 
+000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
+"nop":RD == 0 && RT == 0 && SHIFT == 0
+"ssnop":RD == 0 && RT == 0 && SHIFT == 1
+"sll r<RD>, r<RT>, <SHIFT>"
+*mips32:
+*mips64:
+{
+  /* Skip shift for NOP and SSNOP, so that there won't be lots of
+     extraneous trace output.  */
+  if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
+    do_sll (SD_, RT, RD, SHIFT);
+}
+
 
 :function:::void:do_sllv:int rs, int rt, int rd
 {
@@ -2428,6 +2876,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2450,6 +2900,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2472,6 +2924,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2494,6 +2948,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2517,6 +2973,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2528,6 +2986,8 @@
 :function:::void:do_sra:int rt, int rd, int shift
 {
   signed32 temp = (signed32) GPR[rt] >> shift;
+  if (NotWordValue (GPR[rt]))
+    Unpredictable ();
   TRACE_ALU_INPUT2 (GPR[rt], shift);
   GPR[rd] = EXTEND32 (temp);
   TRACE_ALU_RESULT (GPR[rd]);
@@ -2540,6 +3000,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2553,6 +3015,8 @@
 {
   int s = MASKED (GPR[rs], 4, 0);
   signed32 temp = (signed32) GPR[rt] >> s;
+  if (NotWordValue (GPR[rt]))
+    Unpredictable ();
   TRACE_ALU_INPUT2 (GPR[rt], s);
   GPR[rd] = EXTEND32 (temp);
   TRACE_ALU_RESULT (GPR[rd]);
@@ -2565,6 +3029,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2577,6 +3043,8 @@
 :function:::void:do_srl:int rt, int rd, int shift
 {
   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
+  if (NotWordValue (GPR[rt]))
+    Unpredictable ();
   TRACE_ALU_INPUT2 (GPR[rt], shift);
   GPR[rd] = EXTEND32 (temp);
   TRACE_ALU_RESULT (GPR[rd]);
@@ -2589,6 +3057,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2601,6 +3071,8 @@
 {
   int s = MASKED (GPR[rs], 4, 0);
   unsigned32 temp = (unsigned32) GPR[rt] >> s;
+  if (NotWordValue (GPR[rt]))
+    Unpredictable ();
   TRACE_ALU_INPUT2 (GPR[rt], s);
   GPR[rd] = EXTEND32 (temp);
   TRACE_ALU_RESULT (GPR[rd]);
@@ -2613,6 +3085,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2628,10 +3102,14 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
+  if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+    Unpredictable ();
   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
   {
     ALU32_BEGIN (GPR[RS]);
@@ -2644,6 +3122,8 @@
 
 :function:::void:do_subu:int rs, int rt, int rd
 {
+  if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
+    Unpredictable ();
   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
   TRACE_ALU_RESULT (GPR[rd]);
@@ -2656,6 +3136,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2671,6 +3153,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *r3900:
 *vr5000:
@@ -2686,6 +3170,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2701,6 +3187,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2716,6 +3204,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2731,6 +3221,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2740,17 +3232,19 @@
 
 
 000000,20.CODE,001100:SPECIAL:32::SYSCALL
-"syscall <CODE>"
+"syscall %#lx<CODE>"
 *mipsI:
 *mipsII:
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
-  SignalException(SystemCall, instruction_0);
+  SignalException (SystemCall, instruction_0);
 }
 
 
@@ -2760,11 +3254,13 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
-    SignalException(Trap, instruction_0);
+    SignalException (Trap, instruction_0);
 }
 
 
@@ -2774,11 +3270,13 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
-    SignalException(Trap, instruction_0);
+    SignalException (Trap, instruction_0);
 }
 
 
@@ -2788,11 +3286,13 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
-    SignalException(Trap, instruction_0);
+    SignalException (Trap, instruction_0);
 }
 
 
@@ -2802,11 +3302,13 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
-    SignalException(Trap, instruction_0);
+    SignalException (Trap, instruction_0);
 }
 
 
@@ -2816,11 +3318,13 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
-    SignalException(Trap, instruction_0);
+    SignalException (Trap, instruction_0);
 }
 
 
@@ -2830,11 +3334,13 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
-    SignalException(Trap, instruction_0);
+    SignalException (Trap, instruction_0);
 }
 
 
@@ -2844,11 +3350,13 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
-    SignalException(Trap, instruction_0);
+    SignalException (Trap, instruction_0);
 }
 
 
@@ -2858,11 +3366,13 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
-    SignalException(Trap, instruction_0);
+    SignalException (Trap, instruction_0);
 }
 
 
@@ -2872,11 +3382,13 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
-    SignalException(Trap, instruction_0);
+    SignalException (Trap, instruction_0);
 }
 
 
@@ -2886,11 +3398,13 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
-    SignalException(Trap, instruction_0);
+    SignalException (Trap, instruction_0);
 }
 
 
@@ -2900,25 +3414,29 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
-    SignalException(Trap, instruction_0);
+    SignalException (Trap, instruction_0);
 }
 
 
 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
-"tne r<RS>, <IMMEDIATE>"
+"tnei r<RS>, <IMMEDIATE>"
 *mipsII:
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
-    SignalException(Trap, instruction_0);
+    SignalException (Trap, instruction_0);
 }
 
 
@@ -2936,6 +3454,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2952,12 +3472,14 @@
 }
 
 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
-"xori r<RT>, r<RS>, <IMMEDIATE>"
+"xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
 *mipsI:
 *mipsII:
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -2981,16 +3503,7 @@
     case fmt_double: return "d";
     case fmt_word: return "w";
     case fmt_long: return "l";
-    default: return "?";
-    }
-}
-
-:%s::::X:int x
-{
-  switch (x)
-    {
-    case 0: return "f";
-    case 1: return "t";
+    case fmt_ps: return "ps";
     default: return "?";
     }
 }
@@ -3049,6 +3562,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3063,17 +3578,25 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
-*mipsV:
+*mips32:
 *vr4100:
 *vr5000:
 *r3900:
 {
   /* None of these ISAs support Paired Single, so just fall back to
      the single/double check.  */
-  /* XXX FIXME: not true for mipsV, but we don't support .ps insns yet.  */
   check_fmt (SD_, fmt, insn);
 }
 
+:function:::void:check_fmt_p:int fmt, instruction_word insn
+*mipsV:
+*mips64:
+{
+  if ((fmt != fmt_single) && (fmt != fmt_double)
+      && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
+    SignalException (ReservedInstruction, insn);
+}
+
 
 // Helper:
 //
@@ -3087,14 +3610,85 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
-#if 0	/* XXX FIXME: For now, never treat the FPU as disabled.  */
   if (! COP_Usable (1))
     SignalExceptionCoProcessorUnusable (1);
-#endif
+}
+
+
+// Helper:
+//
+// Load a double word FP value using 2 32-bit memory cycles a la MIPS II
+// or MIPS32.  do_load cannot be used instead because it returns an
+// unsigned_word, which is limited to the size of the machine's registers.
+//
+
+:function:::unsigned64:do_load_double:address_word base, address_word offset
+*mipsII:
+*mips32:
+{
+  int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
+  address_word vaddr;
+  address_word paddr;
+  int uncached;
+  unsigned64 memval;
+  unsigned64 v;
+
+  vaddr = loadstore_ea (SD_, base, offset);
+  if ((vaddr & AccessLength_DOUBLEWORD) != 0)
+    {
+      SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
+		       AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
+		       sim_core_unaligned_signal);
+    }
+  AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
+		      isREAL);
+  LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
+	      isDATA, isREAL);
+  v = (unsigned64)memval;
+  LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
+	      isDATA, isREAL);
+  return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
+}
+
+
+// Helper:
+//
+// Store a double word FP value using 2 32-bit memory cycles a la MIPS II
+// or MIPS32.  do_load cannot be used instead because it returns an
+// unsigned_word, which is limited to the size of the machine's registers.
+//
+
+:function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
+*mipsII:
+*mips32:
+{
+  int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
+  address_word vaddr;
+  address_word paddr;
+  int uncached;
+  unsigned64 memval;
+
+  vaddr = loadstore_ea (SD_, base, offset);
+  if ((vaddr & AccessLength_DOUBLEWORD) != 0)
+    {
+      SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
+		       AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
+		       sim_core_unaligned_signal);
+    }
+  AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
+		      isREAL);
+  memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
+  StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
+	       isREAL);
+  memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
+  StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
+	       isREAL);
 }
 
 
@@ -3105,6 +3699,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3112,7 +3708,7 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt_p (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt,AbsoluteValue(ValueFPR(FS,fmt),fmt));
+  StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt));
 }
 
 
@@ -3124,6 +3720,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3131,10 +3729,36 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt_p (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt,Add(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
+  StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
 }
 
 
+010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:64,f::ALNV.PS
+"alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
+*mipsV:
+*mips64:
+{
+  unsigned64 fs;
+  unsigned64 ft;
+  unsigned64 fd;
+  check_fpu (SD_);
+  check_u64 (SD_, instruction_0);
+  fs = ValueFPR (FS, fmt_ps);
+  if ((GPR[RS] & 0x3) != 0)
+    Unpredictable ();
+  if ((GPR[RS] & 0x4) == 0)
+    fd = fs;
+  else
+    {
+      ft = ValueFPR (FT, fmt_ps);
+      if (BigEndianCPU)
+	fd = PackPS (PSLower (fs), PSUpper (ft));
+      else
+	fd = PackPS (PSLower (ft), PSUpper (fs));
+    }
+  StoreFPR (FD, fmt_ps, fd);
+}
+
 
 // BC1F
 // BC1FL
@@ -3148,13 +3772,11 @@
 *mipsIII:
 {
   check_fpu (SD_);
-  check_branch_bug ();
   TRACE_BRANCH_INPUT (PREVCOC1());
   if (PREVCOC1() == TF)
     {
       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
       TRACE_BRANCH_RESULT (dest);
-      mark_branch_bug (dest);
       DELAY_SLOT (dest);
     }
   else if (ND)
@@ -3173,16 +3795,16 @@
 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 #*vr4100:
 *vr5000:
 *r3900:
 {
   check_fpu (SD_);
-  check_branch_bug ();
   if (GETFCC(CC) == TF)
     {
       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
-      mark_branch_bug (dest);
       DELAY_SLOT (dest);
     }
   else if (ND)
@@ -3192,45 +3814,6 @@
 }
 
 
-
-
-
-
-// C.EQ.S
-// C.EQ.D
-// ...
-
-:function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
-{
-  int less;
-  int equal;
-  int unordered;
-  int condition;
-  unsigned64 ofs = ValueFPR (fs, fmt);
-  unsigned64 oft = ValueFPR (ft, fmt);
-  if (NaN (ofs, fmt) || NaN (oft, fmt))
-    {
-      if (FCSR & FP_ENABLE (IO))
-	{
-	  FCSR |= FP_CAUSE (IO);
-	  SignalExceptionFPE ();
-	}
-      less = 0;
-      equal = 0;
-      unordered = 1;
-    }
-  else
-    {
-      less = Less (ofs, oft, fmt);
-      equal = Equal (ofs, oft, fmt);
-      unordered = 0;
-    }
-  condition = (((cond & (1 << 2)) && less)
-	       || ((cond & (1 << 1)) && equal)
-	       || ((cond & (1 << 0)) && unordered));
-  SETFCC (cc, condition);
-}
-
 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
 *mipsI:
@@ -3240,7 +3823,8 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt_p (SD_, fmt, instruction_0);
-  do_c_cond_fmt (SD_, fmt, FT, FS, 0, COND, instruction_0);
+  Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
+  TRACE_ALU_RESULT (ValueFCR (31));
 }
 
 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
@@ -3248,6 +3832,8 @@
 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3255,7 +3841,8 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt_p (SD_, fmt, instruction_0);
-  do_c_cond_fmt (SD_, fmt, FT, FS, CC, COND, instruction_0);
+  Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
+  TRACE_ALU_RESULT (ValueFCR (31));
 }
 
 
@@ -3264,6 +3851,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3271,15 +3859,19 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(FS,fmt),fmt,fmt_long));
+  StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
+	    fmt_long));
 }
 
 
 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
+"ceil.w.%s<FMT> f<FD>, f<FS>"
 *mipsII:
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3287,82 +3879,97 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(FS,fmt),fmt,fmt_word));
+  StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
+	    fmt_word));
 }
 
 
-// CFC1
-// CTC1
-010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32,f::CxC1
-"c%s<X>c1 r<RT>, f<FS>"
+010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
+"cfc1 r<RT>, f<FS>"
 *mipsI:
 *mipsII:
 *mipsIII:
 {
   check_fpu (SD_);
-  if (X)
-    {
-      if (FS == 0)
-	PENDING_FILL(FCR0IDX,VL4_8(GPR[RT]));
-      else if (FS == 31)
-	PENDING_FILL(FCR31IDX,VL4_8(GPR[RT]));
-      /* else NOP */
-      PENDING_SCHED(FCSR, FCR31 & (1<<23), 1, 23);
-    }
-  else
-    { /* control from */
-      if (FS == 0)
- 	PENDING_FILL(RT, EXTEND32 (FCR0));
-      else if (FS == 31)
- 	PENDING_FILL(RT, EXTEND32 (FCR31));
-      /* else NOP */
-    }
+  if (FS == 0)
+    PENDING_FILL (RT, EXTEND32 (FCR0));
+  else if (FS == 31)
+    PENDING_FILL (RT, EXTEND32 (FCR31));
+  /* else NOP */
 }
-010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32,f::CxC1
-"c%s<X>c1 r<RT>, f<FS>"
+
+010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
+"cfc1 r<RT>, f<FS>"
 *mipsIV:
-*mipsV:
 *vr4100:
 *vr5000:
 *r3900:
 {
   check_fpu (SD_);
-  if (X)
+  if (FS == 0 || FS == 31)
     {
-      /* control to */
-      TRACE_ALU_INPUT1 (GPR[RT]);
-      if (FS == 0)
-	{
-	  FCR0 = VL4_8(GPR[RT]);
-	  TRACE_ALU_RESULT (FCR0);
-	}
-      else if (FS == 31)
-	{
-	  FCR31 = VL4_8(GPR[RT]);
-	  SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
-	  TRACE_ALU_RESULT (FCR31);
-	}
-      else
-	{
-	  TRACE_ALU_RESULT0 ();
-	}
-      /* else NOP */
+      unsigned_word  fcr = ValueFCR (FS);
+      TRACE_ALU_INPUT1 (fcr);
+      GPR[RT] = fcr;
     }
-  else
-    { /* control from */
-      if (FS == 0)
-	{
-	  TRACE_ALU_INPUT1 (FCR0);
-	  GPR[RT] = EXTEND32 (FCR0);
-	}
-      else if (FS == 31)
-	{
-	  TRACE_ALU_INPUT1 (FCR31);
-	  GPR[RT] = EXTEND32 (FCR31);
-	}
-      TRACE_ALU_RESULT (GPR[RT]);
-      /* else NOP */
+  /* else NOP */
+  TRACE_ALU_RESULT (GPR[RT]);
+}
+
+010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
+"cfc1 r<RT>, f<FS>"
+*mipsV:
+*mips32:
+*mips64:
+{
+  check_fpu (SD_);
+  if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
+    {
+      unsigned_word  fcr = ValueFCR (FS);
+      TRACE_ALU_INPUT1 (fcr);
+      GPR[RT] = fcr;
     }
+  /* else NOP */
+  TRACE_ALU_RESULT (GPR[RT]);
+}
+
+010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
+"ctc1 r<RT>, f<FS>"
+*mipsI:
+*mipsII:
+*mipsIII:
+{
+  check_fpu (SD_);
+  if (FS == 31)
+    PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
+  /* else NOP */
+}
+
+010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
+"ctc1 r<RT>, f<FS>"
+*mipsIV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+  check_fpu (SD_);
+  TRACE_ALU_INPUT1 (GPR[RT]);
+  if (FS == 31)
+    StoreFCR (FS, GPR[RT]);
+  /* else NOP */
+}
+
+010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
+"ctc1 r<RT>, f<FS>"
+*mipsV:
+*mips32:
+*mips64:
+{
+  check_fpu (SD_);
+  TRACE_ALU_INPUT1 (GPR[RT]);
+  if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
+      StoreFCR (FS, GPR[RT]);
+  /* else NOP */
 }
 
 
@@ -3376,18 +3983,18 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   int fmt = FMT;
   check_fpu (SD_);
-  {
-    if ((fmt == fmt_double) | 0)
-      SignalException(ReservedInstruction,instruction_0);
-    else
-      StoreFPR(FD,fmt_double,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_double));
-  }
+  if ((fmt == fmt_double) | 0)
+    SignalException (ReservedInstruction, instruction_0);
+  StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
+	    fmt_double));
 }
 
 
@@ -3396,65 +4003,98 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   int fmt = FMT;
   check_fpu (SD_);
-  {
-    if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
-      SignalException(ReservedInstruction,instruction_0);
-    else
-      StoreFPR(FD,fmt_long,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_long));
-  }
+  if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
+    SignalException (ReservedInstruction, instruction_0);
+  StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
+	    fmt_long));
+}
+
+
+010001,10,000,5.FT,5.FS,5.FD,100110:COP1:64,f::CVT.PS.S
+"cvt.ps.s f<FD>, f<FS>, f<FT>"
+*mipsV:
+*mips64:
+{
+  check_fpu (SD_);
+  check_u64 (SD_, instruction_0);
+  StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single),
+				ValueFPR (FT, fmt_single)));
 }
 
 
 //
 // FIXME: Does not correctly differentiate between mips*
 //
-010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
+010001,10,3.FMT!6,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
 "cvt.s.%s<FMT> f<FD>, f<FS>"
 *mipsI:
 *mipsII:
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   int fmt = FMT;
   check_fpu (SD_);
-  {
-    if ((fmt == fmt_single) | 0)
-      SignalException(ReservedInstruction,instruction_0);
-    else
-      StoreFPR(FD,fmt_single,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_single));
-  }
+  if ((fmt == fmt_single) | 0)
+    SignalException (ReservedInstruction, instruction_0);
+  StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
+	    fmt_single));
+}
+
+
+010001,10,110,00000,5.FS,5.FD,101000:COP1:64,f::CVT.S.PL
+"cvt.s.pl f<FD>, f<FS>"
+*mipsV:
+*mips64:
+{
+  check_fpu (SD_);
+  check_u64 (SD_, instruction_0);
+  StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps)));
+}
+
+
+010001,10,110,00000,5.FS,5.FD,100000:COP1:64,f::CVT.S.PU
+"cvt.s.pu f<FD>, f<FS>"
+*mipsV:
+*mips64:
+{
+  check_fpu (SD_);
+  check_u64 (SD_, instruction_0);
+  StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps)));
 }
 
 
-010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
+010001,10,3.FMT!6,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
 "cvt.w.%s<FMT> f<FD>, f<FS>"
 *mipsI:
 *mipsII:
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   int fmt = FMT;
   check_fpu (SD_);
-  {
-    if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
-      SignalException(ReservedInstruction,instruction_0);
-    else
-      StoreFPR(FD,fmt_word,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_word));
-  }
+  if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
+    SignalException (ReservedInstruction, instruction_0);
+  StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
+	    fmt_word));
 }
 
 
@@ -3465,6 +4105,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3472,76 +4114,84 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt,Divide(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
+  StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
 }
 
 
-// DMFC1
-// DMTC1
-010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64,f::DMxC1
-"dm%s<X>c1 r<RT>, f<FS>"
+010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
+"dmfc1 r<RT>, f<FS>"
 *mipsIII:
 {
+  unsigned64 v;
   check_fpu (SD_);
   check_u64 (SD_, instruction_0);
-  if (X)
-    {
-      if (SizeFGR() == 64)
-	PENDING_FILL((FS + FGRIDX),GPR[RT]);
-      else if ((FS & 0x1) == 0)
-	{
-	  PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
-	  PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
-	}
-    }
+  if (SizeFGR () == 64)
+    v = FGR[FS];
+  else if ((FS & 0x1) == 0)
+    v = SET64HI (FGR[FS+1]) | FGR[FS];
   else
-    {
-      if (SizeFGR() == 64)
-	PENDING_FILL(RT,FGR[FS]);
-      else if ((FS & 0x1) == 0)
-	PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
-      else
-	{
-	  if (STATE_VERBOSE_P(SD))
-	    sim_io_eprintf (SD,
-	      "Warning: PC 0x%lx: semantic_DMxC1_COP1Sa 32-bit use of odd FPR number\n",
-	      (long) CIA);
-	  PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
-	}
-    }
+    v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
+  PENDING_FILL (RT, v);
+  TRACE_ALU_RESULT (v);
 }
-010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64,f::DMxC1
-"dm%s<X>c1 r<RT>, f<FS>"
+
+010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
+"dmfc1 r<RT>, f<FS>"
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
 {
   check_fpu (SD_);
   check_u64 (SD_, instruction_0);
-  if (X)
-    {
-      if (SizeFGR() == 64)
-	StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
-      else if ((FS & 0x1) == 0)
-	StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
-    }
+  if (SizeFGR () == 64)
+    GPR[RT] = FGR[FS];
+  else if ((FS & 0x1) == 0)
+    GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
   else
+    GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
+  TRACE_ALU_RESULT (GPR[RT]);
+}
+
+
+010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
+"dmtc1 r<RT>, f<FS>"
+*mipsIII:
+{
+  unsigned64 v;
+  check_fpu (SD_);
+  check_u64 (SD_, instruction_0);
+  if (SizeFGR () == 64)
+    PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
+  else if ((FS & 0x1) == 0)
     {
-      if (SizeFGR() == 64)
-	GPR[RT] = FGR[FS];
-      else if ((FS & 0x1) == 0)
-	GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
-      else
-	{
-	  if (STATE_VERBOSE_P(SD))
-	    sim_io_eprintf (SD,
-	      "Warning: PC 0x%lx: DMxC1 32-bit use of odd FPR number\n",
-			    (long) CIA);
-	  GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
-	}
+      PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
+      PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
     }
+  else
+    Unpredictable ();
+  TRACE_FP_RESULT (GPR[RT]);
+}
+
+010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
+"dmtc1 r<RT>, f<FS>"
+*mipsIV:
+*mipsV:
+*mips64:
+*vr4100:
+*vr5000:
+*r3900:
+{
+  check_fpu (SD_);
+  check_u64 (SD_, instruction_0);
+  if (SizeFGR () == 64)
+    StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
+  else if ((FS & 0x1) == 0)
+    StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
+  else
+    Unpredictable ();
 }
 
 
@@ -3550,6 +4200,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3557,7 +4208,8 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(FS,fmt),fmt,fmt_long));
+  StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
+	    fmt_long));
 }
 
 
@@ -3567,6 +4219,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3574,16 +4228,27 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(FS,fmt),fmt,fmt_word));
+  StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
+	    fmt_word));
 }
 
 
-110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1
+110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
 *mipsII:
+*mips32:
+{
+  check_fpu (SD_);
+  COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
+}
+
+
+110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
+"ldc1 f<FT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3597,6 +4262,7 @@
 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
 *mipsIV:
 *mipsV:
+*mips64:
 *vr5000:
 {
   check_fpu (SD_);
@@ -3613,6 +4279,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3626,6 +4294,7 @@
 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
 *mipsIV:
 *mipsV:
+*mips64:
 *vr5000:
 {
   check_fpu (SD_);
@@ -3635,75 +4304,48 @@
 
 
 
-//
-// FIXME: Not correct for mips*
-//
-010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
-"madd.d f<FD>, f<FR>, f<FS>, f<FT>"
-*mipsIV:
-*mipsV:
-*vr5000:
-{
-  check_fpu (SD_);
-  {
-    StoreFPR(FD,fmt_double,Add(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double));
-  }
-}
-
-
-010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
-"madd.s f<FD>, f<FR>, f<FS>, f<FT>"
+010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT:COP1X:64,f::MADD.fmt
+"madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
 *mipsV:
+*mips64:
 *vr5000:
 {
+  int fmt = FMT;
   check_fpu (SD_);
-  {
-    StoreFPR(FD,fmt_single,Add(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single));
-  }
+  check_u64 (SD_, instruction_0);
+  check_fmt_p (SD_, fmt, instruction_0); 
+  StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
+				  ValueFPR (FR, fmt), fmt));
 }
 
 
-// MFC1
-// MTC1
-010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32,f::MxC1
-"m%s<X>c1 r<RT>, f<FS>"
+010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
+"mfc1 r<RT>, f<FS>"
 *mipsI:
 *mipsII:
 *mipsIII:
 {
+  unsigned64 v;
   check_fpu (SD_);
-  if (X)
-    { /*MTC1*/
-      if (SizeFGR() == 64)
-	{
-	  if (STATE_VERBOSE_P(SD))
-	    sim_io_eprintf (SD,
-			    "Warning:  PC 0x%lx: MTC1 not DMTC1 with 64 bit regs\n",
-			    (long) CIA);
-	  PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
-	}
-      else
-	PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
-    }
-  else /*MFC1*/
-    PENDING_FILL (RT, EXTEND32 (FGR[FS]));
+  v = EXTEND32 (FGR[FS]);
+  PENDING_FILL (RT, v);
+  TRACE_ALU_RESULT (v);
 }
-010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32,f::MxC1
-"m%s<X>c1 r<RT>, f<FS>"
+  
+010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
+"mfc1 r<RT>, f<FS>"
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
-{
-  int fs = FS;
+{ 
   check_fpu (SD_);
-  if (X)
-    /*MTC1*/
-    StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
-  else /*MFC1*/
-    GPR[RT] = EXTEND32 (FGR[FS]);
+  GPR[RT] = EXTEND32 (FGR[FS]);
+  TRACE_ALU_RESULT (GPR[RT]);
 }
 
 
@@ -3714,6 +4356,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3721,7 +4365,7 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt_p (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt,ValueFPR(FS,fmt));
+  StoreFPR (FD, fmt, ValueFPR (FS, fmt));
 }
 
 
@@ -3731,6 +4375,8 @@
 "mov%s<TF> r<RD>, r<RS>, <CC>"
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr5000:
 {
   check_fpu (SD_);
@@ -3745,16 +4391,28 @@
 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr5000:
 {
   int fmt = FMT;
   check_fpu (SD_);
-  {
-   if (GETFCC(CC) == TF)
-     StoreFPR (FD, fmt, ValueFPR (FS, fmt));
-   else
-     StoreFPR (FD, fmt, ValueFPR (FD, fmt));
-  }
+  if (fmt != fmt_ps)
+    {
+      if (GETFCC(CC) == TF)
+	StoreFPR (FD, fmt, ValueFPR (FS, fmt));
+      else
+	StoreFPR (FD, fmt, ValueFPR (FD, fmt));   /* set fmt */
+    }
+  else
+    {
+      unsigned64 fd;
+      fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD,
+				      fmt_ps)),
+		   PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD,
+				      fmt_ps)));
+      StoreFPR (FD, fmt_ps, fd);
+    }
 }
 
 
@@ -3762,6 +4420,8 @@
 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr5000:
 {
   check_fpu (SD_);
@@ -3783,6 +4443,8 @@
 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr5000:
 {
   check_fpu (SD_);
@@ -3793,33 +4455,51 @@
 }
 
 
-// MSUB.fmt
-010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32,f::MSUB.D
-"msub.d f<FD>, f<FR>, f<FS>, f<FT>"
+010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT:COP1X:64,f::MSUB.fmt
+"msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
 *mipsV:
+*mips64:
 *vr5000:
 {
+  int fmt = FMT;
   check_fpu (SD_);
-  StoreFPR(FD,fmt_double,Sub(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double));
+  check_u64 (SD_, instruction_0);
+  check_fmt_p (SD_, fmt, instruction_0);
+  StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
+				  ValueFPR (FR, fmt), fmt));
 }
 
 
-// MSUB.fmt
-010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32,f::MSUB.S
-"msub.s f<FD>, f<FR>, f<FS>, f<FT>"
+010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
+"mtc1 r<RT>, f<FS>"
+*mipsI:
+*mipsII:
+*mipsIII:
+{ 
+  check_fpu (SD_);
+  if (SizeFGR () == 64)
+    PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
+  else
+    PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
+  TRACE_FP_RESULT (GPR[RT]);
+} 
+
+010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
+"mtc1 r<RT>, f<FS>"
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
+*vr4100:
 *vr5000:
+*r3900:
 {
-  check_fpu (SD_);
-  StoreFPR(FD,fmt_single,Sub(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single));
+  check_fpu (SD_); 
+  StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
 }
 
 
-// MTC1 see MxC1
-
-
 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
 *mipsI:
@@ -3827,6 +4507,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3834,7 +4516,7 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt_p (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt,Multiply(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
+  StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
 }
 
 
@@ -3845,6 +4527,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3852,55 +4536,63 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt_p (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt,Negate(ValueFPR(FS,fmt),fmt));
+  StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt));
 }
 
 
-// NMADD.fmt
-010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32,f::NMADD.D
-"nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
+010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT:COP1X:64,f::NMADD.fmt
+"nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
 *mipsV:
+*mips64:
 *vr5000:
 {
+  int fmt = FMT;
   check_fpu (SD_);
-  StoreFPR(FD,fmt_double,Negate(Add(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double),fmt_double));
+  check_u64 (SD_, instruction_0);
+  check_fmt_p (SD_, fmt, instruction_0);
+  StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
+				     ValueFPR (FR, fmt), fmt));
 }
 
 
-// NMADD.fmt
-010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32,f::NMADD.S
-"nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
+010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT:COP1X:64,f::NMSUB.fmt
+"nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
 *mipsV:
+*mips64:
 *vr5000:
 {
+  int fmt = FMT;
   check_fpu (SD_);
-  StoreFPR(FD,fmt_single,Negate(Add(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single),fmt_single));
+  check_u64 (SD_, instruction_0);
+  check_fmt_p (SD_, fmt, instruction_0);
+  StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
+				     ValueFPR (FR, fmt), fmt));
 }
 
 
-// NMSUB.fmt
-010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32,f::NMSUB.D
-"nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
-*mipsIV:
+010001,10,110,5.FT,5.FS,5.FD,101100:COP1:64,f::PLL.PS
+"pll.ps f<FD>, f<FS>, f<FT>"
 *mipsV:
-*vr5000:
+*mips64:
 {
   check_fpu (SD_);
-  StoreFPR(FD,fmt_double,Negate(Sub(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double),fmt_double));
+  check_u64 (SD_, instruction_0);
+  StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
+				PSLower (ValueFPR (FT, fmt_ps))));
 }
 
 
-// NMSUB.fmt
-010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32,f::NMSUB.S
-"nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
-*mipsIV:
+010001,10,110,5.FT,5.FS,5.FD,101101:COP1:64,f::PLU.PS
+"plu.ps f<FD>, f<FS>, f<FT>"
 *mipsV:
-*vr5000:
+*mips64:
 {
   check_fpu (SD_);
-  StoreFPR(FD,fmt_single,Negate(Sub(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single),fmt_single));
+  check_u64 (SD_, instruction_0);
+  StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
+				PSUpper (ValueFPR (FT, fmt_ps))));
 }
 
 
@@ -3908,6 +4600,7 @@
 "prefx <HINT>, r<INDEX>(r<BASE>)"
 *mipsIV:
 *mipsV:
+*mips64:
 *vr5000:
 {
   address_word base = GPR[BASE];
@@ -3921,16 +4614,42 @@
   }
 }
 
+
+010001,10,110,5.FT,5.FS,5.FD,101110:COP1:64,f::PUL.PS
+"pul.ps f<FD>, f<FS>, f<FT>"
+*mipsV:
+*mips64:
+{
+  check_fpu (SD_);
+  check_u64 (SD_, instruction_0);
+  StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
+				PSLower (ValueFPR (FT, fmt_ps))));
+}
+
+
+010001,10,110,5.FT,5.FS,5.FD,101111:COP1:64,f::PUU.PS
+"puu.ps f<FD>, f<FS>, f<FT>"
+*mipsV:
+*mips64:
+{
+  check_fpu (SD_);
+  check_u64 (SD_, instruction_0);
+  StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
+				PSUpper (ValueFPR (FT, fmt_ps))));
+}
+
+
 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
 "recip.%s<FMT> f<FD>, f<FS>"
 *mipsIV:
 *mipsV:
+*mips64:
 *vr5000:
 {
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt,Recip(ValueFPR(FS,fmt),fmt));
+  StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
 }
 
 
@@ -3939,6 +4658,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3946,7 +4666,8 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(FS,fmt),fmt,fmt_long));
+  StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
+	    fmt_long));
 }
 
 
@@ -3956,6 +4677,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3963,29 +4686,41 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(FS,fmt),fmt,fmt_word));
+  StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
+	    fmt_word));
 }
 
 
 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
+"rsqrt.%s<FMT> f<FD>, f<FS>"
 *mipsIV:
 *mipsV:
-"rsqrt.%s<FMT> f<FD>, f<FS>"
+*mips64:
 *vr5000:
 {
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt,Recip(SquareRoot(ValueFPR(FS,fmt),fmt),fmt));
+  StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
 }
 
 
-111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1
+111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
 *mipsII:
+*mips32:
+{
+  check_fpu (SD_);
+  do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
+}
+
+
+111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
+"sdc1 f<FT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -3999,6 +4734,7 @@
 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
 *mipsIV:
 *mipsV:
+*mips64:
 *vr5000:
 {
   check_fpu (SD_);
@@ -4013,6 +4749,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -4020,7 +4758,7 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt,(SquareRoot(ValueFPR(FS,fmt),fmt)));
+  StoreFPR (FD, fmt,  (SquareRoot (ValueFPR (FS, fmt), fmt)));
 }
 
 
@@ -4031,6 +4769,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -4038,7 +4778,7 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt_p (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt,Sub(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
+  StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
 }
 
 
@@ -4050,6 +4790,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -4089,6 +4831,7 @@
 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
 *mipsIV:
 *mipsV:
+*mips64:
 *vr5000:
 {
 
@@ -4129,6 +4872,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -4136,7 +4880,8 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(FS,fmt),fmt,fmt_long));
+  StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
+	    fmt_long));
 }
 
 
@@ -4146,6 +4891,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -4153,7 +4900,8 @@
   int fmt = FMT;
   check_fpu (SD_);
   check_fmt (SD_, fmt, instruction_0);
-  StoreFPR(FD,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(FS,fmt),fmt,fmt_word));
+  StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
+	    fmt_word));
 }
 
 
@@ -4171,6 +4919,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 
@@ -4190,6 +4940,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 
@@ -4201,6 +4953,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 
 
@@ -4211,6 +4965,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 
@@ -4220,6 +4976,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -4252,6 +5010,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 {
   check_u64 (SD_, instruction_0);
   DecodeCoproc (instruction_0);
@@ -4263,6 +5022,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 {
   check_u64 (SD_, instruction_0);
   DecodeCoproc (instruction_0);
@@ -4276,6 +5036,7 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips64:
 *vr4100:
 *vr5000:
 
@@ -4285,6 +5046,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 {
@@ -4310,6 +5073,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -4326,6 +5091,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 *r3900:
@@ -4356,6 +5123,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *r3900:
 {
@@ -4371,6 +5140,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 
@@ -4382,6 +5153,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 
@@ -4393,6 +5166,8 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 
@@ -4404,11 +5179,16 @@
 *mipsIII:
 *mipsIV:
 *mipsV:
+*mips32:
+*mips64:
 *vr4100:
 *vr5000:
 
 
 :include:::m16.igen
+:include:::mdmx.igen
+:include:::mips3d.igen
+:include:::sb1.igen
 :include:::tx.igen
 :include:::vr.igen