X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fmips%2Fmips3264r2.igen;h=3531fd04e13fab83c1edff3328f0f89111166a4f;hb=128e85e3ab36b8e30f6612fb50de3cbb4ede6824;hp=e0d1326354e5f5a2ff25f50ad3ddb3d493254b1b;hpb=e70cb6cd9ab5e88c1d4fe20a454ddc3bcd1a4453;p=deliverable%2Fbinutils-gdb.git
diff --git a/sim/mips/mips3264r2.igen b/sim/mips/mips3264r2.igen
index e0d1326354..3531fd04e1 100644
--- a/sim/mips/mips3264r2.igen
+++ b/sim/mips/mips3264r2.igen
@@ -1,34 +1,201 @@
// -*- C -*-
// Simulator definition for the MIPS 32/64 revision 2 instructions.
-// Copyright (C) 2004 Free Software Foundation, Inc.
+// Copyright (C) 2004-2016 Free Software Foundation, Inc.
// Contributed by David Ung, of MIPS Technologies.
//
-// This file is part of GDB, the GNU debugger.
+// This file is part of the MIPS sim.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; either version 2, or (at your option)
-// any later version.
-//
+// the Free Software Foundation; either version 3 of the License, or
+// (at your option) any later version.
+//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License along
-// with this program; if not, write to the Free Software Foundation, Inc.,
-// 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see .
+
+:function:::void:do_dsbh:int rd, int rt
+{
+ union { unsigned64 d; unsigned16 h[4]; } u;
+ TRACE_ALU_INPUT1 (GPR[rt]);
+ u.d = GPR[rt];
+ u.h[0] = SWAP_2 (u.h[0]);
+ u.h[1] = SWAP_2 (u.h[1]);
+ u.h[2] = SWAP_2 (u.h[2]);
+ u.h[3] = SWAP_2 (u.h[3]);
+ GPR[rd] = u.d;
+ TRACE_ALU_RESULT1 (GPR[rd]);
+}
+
+:function:::void:do_dshd:int rd, int rt
+{
+ unsigned64 d;
+ TRACE_ALU_INPUT1 (GPR[rt]);
+ d = GPR[rt];
+ GPR[rd] = ((d >> 48)
+ | (d << 48)
+ | ((d & 0x0000ffff00000000ULL) >> 16)
+ | ((d & 0x00000000ffff0000ULL) << 16));
+ TRACE_ALU_RESULT1 (GPR[rd]);
+}
+
+:function:::void:do_dext:int rt, int rs, int lsb, int size
+{
+ TRACE_ALU_INPUT3 (GPR[rs], lsb, size);
+ GPR[rt] = EXTRACTED64 (GPR[rs], lsb + size, lsb);
+ TRACE_ALU_RESULT1 (GPR[rt]);
+}
+
+:function:::void:do_dextm:int rt, int rs, int lsb, int size
+{
+ TRACE_ALU_INPUT3 (GPR[rs], lsb, size);
+ GPR[rt] = EXTRACTED64 (GPR[rs], lsb + size + 32, lsb);
+ TRACE_ALU_RESULT1 (GPR[rt]);
+}
+
+:function:::void:do_dextu:int rt, int rs, int lsb, int size
+{
+ TRACE_ALU_INPUT3 (GPR[rs], lsb, size);
+ GPR[rt] = EXTRACTED64 (GPR[rs], lsb + 32 + size, lsb + 32);
+ TRACE_ALU_RESULT1 (GPR[rt]);
+}
+
+:function:::void:do_di:int rt
+{
+ TRACE_ALU_INPUT0 ();
+ GPR[rt] = EXTEND32 (SR);
+ SR &= ~status_IE;
+ TRACE_ALU_RESULT1 (GPR[rt]);
+}
+:function:::void:do_dins:int rt, int rs, int lsb, int msb
+{
+ TRACE_ALU_INPUT4 (GPR[rt], GPR[rs], lsb, msb);
+ if (lsb <= msb)
+ GPR[rt] ^= (GPR[rt] ^ (GPR[rs] << lsb)) & MASK64 (msb, lsb);
+ TRACE_ALU_RESULT1 (GPR[rt]);
+}
+
+:function:::void:do_dinsm:int rt, int rs, int lsb, int msb
+{
+ TRACE_ALU_INPUT4 (GPR[rt], GPR[rs], lsb, msb);
+ if (lsb <= msb + 32)
+ GPR[rt] ^= (GPR[rt] ^ (GPR[rs] << lsb)) & MASK64 (msb + 32, lsb);
+ TRACE_ALU_RESULT1 (GPR[rt]);
+}
+
+:function:::void:do_ei:int rt
+{
+ TRACE_ALU_INPUT0 ();
+ GPR[rt] = EXTEND32 (SR);
+ SR |= status_IE;
+ TRACE_ALU_RESULT1 (GPR[rt]);
+}
+
+:function:::void:do_ext:int rt, int rs, int lsb, int size
+{
+ TRACE_ALU_INPUT3 (GPR[rs], lsb, size);
+ GPR[rt] = EXTEND32 (EXTRACTED32 (GPR[rs], lsb + size, lsb));
+ TRACE_ALU_RESULT1 (GPR[rt]);
+}
+
+:function:::void:do_mfhc1:int rt, int fs
+{
+ check_fpu (SD_);
+ if (SizeFGR() == 64)
+ GPR[rt] = EXTEND32 (WORD64HI (FGR[fs]));
+ else if ((fs & 0x1) == 0)
+ GPR[rt] = EXTEND32 (FGR[fs + 1]);
+ else
+ {
+ if (STATE_VERBOSE_P(SD))
+ sim_io_eprintf (SD,
+ "Warning: PC 0x%lx: MFHC1 32-bit use of odd FPR number\n",
+ (long) CIA);
+ GPR[rt] = EXTEND32 (0xBADF00D);
+ }
+ TRACE_ALU_RESULT (GPR[rt]);
+}
+
+:function:::void:do_mthc1:int rt, int fs
+{
+ check_fpu (SD_);
+ if (SizeFGR() == 64)
+ StoreFPR (fs, fmt_uninterpreted_64, SET64HI (GPR[rt]) | VL4_8 (FGR[fs]));
+ else if ((fs & 0x1) == 0)
+ StoreFPR (fs + 1, fmt_uninterpreted_32, VL4_8 (GPR[rt]));
+ else
+ {
+ if (STATE_VERBOSE_P(SD))
+ sim_io_eprintf (SD,
+ "Warning: PC 0x%lx: MTHC1 32-bit use of odd FPR number\n",
+ (long) CIA);
+ StoreFPR (fs, fmt_uninterpreted_32, 0xDEADC0DE);
+ }
+ TRACE_FP_RESULT (GPR[rt]);
+}
+
+:function:::void:do_ins:int rt, int rs, int lsb, int msb
+{
+ TRACE_ALU_INPUT4 (GPR[rt], GPR[rs], lsb, msb);
+ if (lsb <= msb)
+ GPR[rt] = EXTEND32 (GPR[rt] ^
+ ((GPR[rt] ^ (GPR[rs] << lsb)) & MASK32 (msb, lsb)));
+ TRACE_ALU_RESULT1 (GPR[rt]);
+}
+
+:function:::void:do_dinsu:int rt, int rs, int lsb, int msb
+{
+ TRACE_ALU_INPUT4 (GPR[rt], GPR[rs], lsb, msb);
+ if (lsb <= msb)
+ GPR[rt] ^= (GPR[rt] ^ (GPR[rs] << (lsb + 32)))
+ & MASK64 (msb + 32, lsb + 32);
+ TRACE_ALU_RESULT1 (GPR[rt]);
+}
+
+:function:::void:do_seb:int rd, int rt
+{
+ TRACE_ALU_INPUT1 (GPR[rt]);
+ GPR[rd] = EXTEND8 (GPR[rt]);
+ TRACE_ALU_RESULT1 (GPR[rd]);
+}
+
+:function:::void:do_seh:int rd, int rt
+{
+ TRACE_ALU_INPUT1 (GPR[rt]);
+ GPR[rd] = EXTEND16 (GPR[rt]);
+ TRACE_ALU_RESULT1 (GPR[rd]);
+}
+
+:function:::void:do_rdhwr:int rt, int rd
+{
+ // Return 0 for all hardware registers currently
+ GPR[rt] = EXTEND32 (0);
+ TRACE_ALU_RESULT1 (GPR[rt]);
+}
+
+:function:::void:do_wsbh:int rd, int rt
+{
+ union { unsigned32 w; unsigned16 h[2]; } u;
+ TRACE_ALU_INPUT1 (GPR[rt]);
+ u.w = GPR[rt];
+ u.h[0] = SWAP_2 (u.h[0]);
+ u.h[1] = SWAP_2 (u.h[1]);
+ GPR[rd] = EXTEND32 (u.w);
+ TRACE_ALU_RESULT1 (GPR[rd]);
+}
011111,5.RS,5.RT,5.SIZE,5.LSB,000011::64::DEXT
"dext r