X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fmips%2Fsb1.igen;h=3677cba8f3d3a6f745ed70d986e725ba2b536043;hb=5fd104addfddb68844fb8df67be832ee98ad9888;hp=6453670b1d6eed902dac8ca0263313ace86d0f29;hpb=2ee563b53258d390d7446e90a67f465d504ae44c;p=deliverable%2Fbinutils-gdb.git

diff --git a/sim/mips/sb1.igen b/sim/mips/sb1.igen
index 6453670b1d..3677cba8f3 100644
--- a/sim/mips/sb1.igen
+++ b/sim/mips/sb1.igen
@@ -1,24 +1,38 @@
 // -*- C -*-
 
 // Simulator definition for the Broadcom SiByte SB-1 CPU extensions.
-// Copyright (C) 2002 Free Software Foundation, Inc.
-// Contributed by Broadcom Corporation (SiByte).
+// Copyright (C) 2002-2020 Free Software Foundation, Inc.
+// Contributed by Ed Satterthwaite and Chris Demetriou, of Broadcom
+// Corporation (SiByte).
 //
 // This file is part of GDB, the GNU debugger.
 // 
 // This program is free software; you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; either version 2, or (at your option)
-// any later version.
-// 
+// the Free Software Foundation; either version 3 of the License, or
+// (at your option) any later version.
+//
 // This program is distributed in the hope that it will be useful,
 // but WITHOUT ANY WARRANTY; without even the implied warranty of
 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 // GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License along
-// with this program; if not, write to the Free Software Foundation, Inc.,
-// 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+
+// Helper:
+//
+// Check that the SB-1 extension instruction can currently be used, and
+// signal a ReservedInstruction exception if not.
+//
+
+:function:::void:check_sbx:instruction_word insn
+*sb1:
+{
+  if ((SR & status_SBX) == 0)
+    SignalException(ReservedInstruction, insn);
+}
 
 
 //  MDMX ASE Instructions
@@ -151,13 +165,9 @@
 *sb1:
 {
   check_mdmx (SD_, instruction_0);
-  if (SR & status_SBX)
-    {
-      check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
-      StoreFPR(VD,fmt_mdmx,MX_AbsDiff(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
-    }
-  else
-    SignalException(ReservedInstruction, instruction_0);
+  check_sbx (SD_, instruction_0);
+  check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
+  StoreFPR(VD,fmt_mdmx,MX_AbsDiff(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
 }
 
 
@@ -166,13 +176,9 @@
 *sb1:
 {
   check_mdmx (SD_, instruction_0);
-  if (SR & status_SBX)
-    {
-      check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
-      MX_AbsDiffC(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
-    }
-  else
-    SignalException(ReservedInstruction, instruction_0);
+  check_sbx (SD_, instruction_0);
+  check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
+  MX_AbsDiffC(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
 }
 
 
@@ -181,11 +187,57 @@
 *sb1:
 {
   check_mdmx (SD_, instruction_0);
-  if (SR & status_SBX)
-    {
-      check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
-      StoreFPR(VD,fmt_mdmx,MX_Avg(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
-    }
-  else
-    SignalException(ReservedInstruction, instruction_0);
+  check_sbx (SD_, instruction_0);
+  check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
+  StoreFPR(VD,fmt_mdmx,MX_Avg(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
+}
+
+
+//  Paired-Single Extension Instructions
+//  ------------------------------------
+//
+//  The SB-1 implements several .PS format instructions that are
+//  extensions to the MIPS64 architecture.
+
+010001,10,3.FMT=6,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.PS
+"div.%s<FMT> f<FD>, f<FS>, f<FT>"
+*sb1:
+{
+  int fmt = FMT;
+  check_fpu (SD_);
+  check_sbx (SD_, instruction_0);
+  StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
+}
+
+
+010001,10,3.FMT=6,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.PS
+"recip.%s<FMT> f<FD>, f<FS>"
+*sb1:
+{
+  int fmt = FMT;
+  check_fpu (SD_);
+  check_sbx (SD_, instruction_0);
+  StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
+}
+
+
+010001,10,3.FMT=6,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.PS
+"rsqrt.%s<FMT> f<FD>, f<FS>"
+*sb1:
+{
+  int fmt = FMT;
+  check_fpu (SD_);
+  check_sbx (SD_, instruction_0);
+  StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
+}
+
+
+010001,10,3.FMT=6,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.PS
+"sqrt.%s<FMT> f<FD>, f<FS>"
+*sb1:
+{
+  int fmt = FMT;
+  check_fpu (SD_);
+  check_sbx (SD_, instruction_0);
+  StoreFPR (FD, fmt,  (SquareRoot (ValueFPR (FS, fmt), fmt)));
 }