X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fmips%2Fsim-main.c;h=edee498bc94c2ac494e018b8a463241d0081467a;hb=1a27f959ea4265e9ba61e61b22b673347bb9b3ed;hp=48a37ae8ec43d6f988ebf7384f3443f4b00e3b87;hpb=d0352a18a504a4e7b761f6b3264cf11347d8d056;p=deliverable%2Fbinutils-gdb.git

diff --git a/sim/mips/sim-main.c b/sim/mips/sim-main.c
index 48a37ae8ec..edee498bc9 100644
--- a/sim/mips/sim-main.c
+++ b/sim/mips/sim-main.c
@@ -163,44 +163,36 @@ load_memory (SIM_DESC SD,
 
   switch (AccessLength)
     {
-    case AccessLength_QUADWORD :
+    case AccessLength_QUADWORD:
       {
-	unsigned_16 val = sim_core_read_aligned_16 (CPU, NULL_CIA, read_map, pAddr);
+	unsigned_16 val = sim_core_read_aligned_16 (CPU, cia, read_map, pAddr);
 	value1 = VH8_16 (val);
 	value = VL8_16 (val);
 	break;
       }
-    case AccessLength_DOUBLEWORD :
-      value = sim_core_read_aligned_8 (CPU, NULL_CIA,
-				       read_map, pAddr);
+    case AccessLength_DOUBLEWORD:
+      value = sim_core_read_aligned_8 (CPU, cia, read_map, pAddr);
       break;
-    case AccessLength_SEPTIBYTE :
-      value = sim_core_read_misaligned_7 (CPU, NULL_CIA,
-					  read_map, pAddr);
+    case AccessLength_SEPTIBYTE:
+      value = sim_core_read_misaligned_7 (CPU, cia, read_map, pAddr);
       break;
-    case AccessLength_SEXTIBYTE :
-      value = sim_core_read_misaligned_6 (CPU, NULL_CIA,
-					  read_map, pAddr);
+    case AccessLength_SEXTIBYTE:
+      value = sim_core_read_misaligned_6 (CPU, cia, read_map, pAddr);
       break;
-    case AccessLength_QUINTIBYTE :
-      value = sim_core_read_misaligned_5 (CPU, NULL_CIA,
-					  read_map, pAddr);
+    case AccessLength_QUINTIBYTE:
+      value = sim_core_read_misaligned_5 (CPU, cia, read_map, pAddr);
       break;
-    case AccessLength_WORD :
-      value = sim_core_read_aligned_4 (CPU, NULL_CIA,
-				       read_map, pAddr);
+    case AccessLength_WORD:
+      value = sim_core_read_aligned_4 (CPU, cia, read_map, pAddr);
       break;
-    case AccessLength_TRIPLEBYTE :
-      value = sim_core_read_misaligned_3 (CPU, NULL_CIA,
-					  read_map, pAddr);
+    case AccessLength_TRIPLEBYTE:
+      value = sim_core_read_misaligned_3 (CPU, cia, read_map, pAddr);
       break;
-    case AccessLength_HALFWORD :
-      value = sim_core_read_aligned_2 (CPU, NULL_CIA,
-				       read_map, pAddr);
+    case AccessLength_HALFWORD:
+      value = sim_core_read_aligned_2 (CPU, cia, read_map, pAddr);
       break;
-    case AccessLength_BYTE :
-      value = sim_core_read_aligned_1 (CPU, NULL_CIA,
-				       read_map, pAddr);
+    case AccessLength_BYTE:
+      value = sim_core_read_aligned_1 (CPU, cia, read_map, pAddr);
       break;
     default:
       abort ();
@@ -300,43 +292,35 @@ store_memory (SIM_DESC SD,
   
   switch (AccessLength)
     {
-    case AccessLength_QUADWORD :
+    case AccessLength_QUADWORD:
       {
 	unsigned_16 val = U16_8 (MemElem1, MemElem);
-	sim_core_write_aligned_16 (CPU, NULL_CIA, write_map, pAddr, val);
+	sim_core_write_aligned_16 (CPU, cia, write_map, pAddr, val);
 	break;
       }
-    case AccessLength_DOUBLEWORD :
-      sim_core_write_aligned_8 (CPU, NULL_CIA,
-				write_map, pAddr, MemElem);
+    case AccessLength_DOUBLEWORD:
+      sim_core_write_aligned_8 (CPU, cia, write_map, pAddr, MemElem);
       break;
-    case AccessLength_SEPTIBYTE :
-      sim_core_write_misaligned_7 (CPU, NULL_CIA,
-				   write_map, pAddr, MemElem);
+    case AccessLength_SEPTIBYTE:
+      sim_core_write_misaligned_7 (CPU, cia, write_map, pAddr, MemElem);
       break;
-    case AccessLength_SEXTIBYTE :
-      sim_core_write_misaligned_6 (CPU, NULL_CIA,
-				   write_map, pAddr, MemElem);
+    case AccessLength_SEXTIBYTE:
+      sim_core_write_misaligned_6 (CPU, cia, write_map, pAddr, MemElem);
       break;
-    case AccessLength_QUINTIBYTE :
-      sim_core_write_misaligned_5 (CPU, NULL_CIA,
-				   write_map, pAddr, MemElem);
+    case AccessLength_QUINTIBYTE:
+      sim_core_write_misaligned_5 (CPU, cia, write_map, pAddr, MemElem);
       break;
-    case AccessLength_WORD :
-      sim_core_write_aligned_4 (CPU, NULL_CIA,
-				write_map, pAddr, MemElem);
+    case AccessLength_WORD:
+      sim_core_write_aligned_4 (CPU, cia, write_map, pAddr, MemElem);
       break;
-    case AccessLength_TRIPLEBYTE :
-      sim_core_write_misaligned_3 (CPU, NULL_CIA,
-				   write_map, pAddr, MemElem);
+    case AccessLength_TRIPLEBYTE:
+      sim_core_write_misaligned_3 (CPU, cia, write_map, pAddr, MemElem);
       break;
-    case AccessLength_HALFWORD :
-      sim_core_write_aligned_2 (CPU, NULL_CIA,
-				write_map, pAddr, MemElem);
+    case AccessLength_HALFWORD:
+      sim_core_write_aligned_2 (CPU, cia, write_map, pAddr, MemElem);
       break;
-    case AccessLength_BYTE :
-      sim_core_write_aligned_1 (CPU, NULL_CIA,
-				write_map, pAddr, MemElem);
+    case AccessLength_BYTE:
+      sim_core_write_aligned_1 (CPU, cia, write_map, pAddr, MemElem);
       break;
     default:
       abort ();