X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fmips%2Fsim-main.h;h=0ea1234fe6b019927e29298f3a745e6e064eb963;hb=1ac72f0659d64d6a14da862242db0d841d2878d0;hp=7e1b89420157e487bd91111a0ba68476d68eab4b;hpb=14bbac6609d4009076b47ee1ce21c17890152056;p=deliverable%2Fbinutils-gdb.git
diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h
index 7e1b894201..0ea1234fe6 100644
--- a/sim/mips/sim-main.h
+++ b/sim/mips/sim-main.h
@@ -1,49 +1,36 @@
/* MIPS Simulator definition.
- Copyright (C) 1997, 1998 Free Software Foundation, Inc.
+ Copyright (C) 1997-2016 Free Software Foundation, Inc.
Contributed by Cygnus Support.
-This file is part of GDB, the GNU debugger.
+This file is part of the MIPS sim.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+the Free Software Foundation; either version 3 of the License, or
+(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+You should have received a copy of the GNU General Public License
+along with this program. If not, see . */
#ifndef SIM_MAIN_H
#define SIM_MAIN_H
-/* This simulator doesn't cache the Current Instruction Address */
-/* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
-/* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
-
-#define SIM_HAVE_BIENDIAN
-
-
-/* hobble some common features for moment */
-#define WITH_WATCHPOINTS 1
-#define WITH_MODULO_MEMORY 1
-
+/* MIPS uses an unusual format for floating point quiet NaNs. */
+#define SIM_QUIET_NAN_NEGATED
#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
#include "sim-basics.h"
-
-typedef address_word sim_cia;
-
#include "sim-base.h"
+#include "bfd.h"
-
-/* Depreciated macros and types for manipulating 64bit values. Use
+/* Deprecated macros and types for manipulating 64bit values. Use
../common/sim-bits.h and ../common/sim-endian.h macros instead. */
typedef signed64 word64;
@@ -56,23 +43,29 @@ typedef unsigned64 uword64;
#define WORD64(h,l) ((word64)((SET64HI(h)|SET64LO(l))))
#define UWORD64(h,l) (SET64HI(h)|SET64LO(l))
-/* Sign-extend the given value (e) as a value (b) bits long. We cannot
- assume the HI32bits of the operand are zero, so we must perform a
- mask to ensure we can use the simple subtraction to sign-extend. */
-#define SIGNEXTEND(e,b) \
- ((unsigned_word) \
- (((e) & ((uword64) 1 << ((b) - 1))) \
- ? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \
- : ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1))))
-
/* Check if a value will fit within a halfword: */
#define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
+typedef enum {
+ cp0_dmfc0,
+ cp0_dmtc0,
+ cp0_mfc0,
+ cp0_mtc0,
+ cp0_tlbr,
+ cp0_tlbwi,
+ cp0_tlbwr,
+ cp0_tlbp,
+ cp0_cache,
+ cp0_eret,
+ cp0_deret,
+ cp0_rfe
+} CP0_operation;
/* Floating-point operations: */
#include "sim-fpu.h"
+#include "cp1.h"
/* FPU registers must be one of the following types. All other values
are reserved (and undefined). */
@@ -81,6 +74,7 @@ typedef enum {
fmt_double = 1,
fmt_word = 4,
fmt_long = 5,
+ fmt_ps = 6,
/* The following are well outside the normal acceptable format
range, and are used in the register status vector. */
fmt_unknown = 0x10000000,
@@ -89,40 +83,9 @@ typedef enum {
fmt_uninterpreted_64 = 0x80000000U,
} FP_formats;
-unsigned64 value_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats));
-#define ValueFPR(FPR,FMT) value_fpr (SD, CPU, cia, (FPR), (FMT))
-
-void store_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats fmt, unsigned64 value));
-#define StoreFPR(FPR,FMT,VALUE) store_fpr (SD, CPU, cia, (FPR), (FMT), (VALUE))
-
-int NaN PARAMS ((unsigned64 op, FP_formats fmt));
-int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
-int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
-int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
-unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
-unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
-unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
-unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
-unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
-unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
-unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
-unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
-unsigned64 Max PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
-unsigned64 Min PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
-unsigned64 convert PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
-#define Convert(rm,op,from,to) \
-convert (SD, CPU, cia, rm, op, from, to)
-
-/* Macro to update FPSR condition-code field. This is complicated by
- the fact that there is a hole in the index range of the bits within
- the FCSR register. Also, the number of bits visible depends on the
- MIPS ISA version being supported. */
-
-#define SETFCC(cc,v) {\
- int bit = ((cc == 0) ? 23 : (24 + (cc)));\
- FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
-}
-#define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1U : 0)
+/* For paired word (pw) operations, the opcode representation is fmt_word,
+ but register transfers (StoreFPR, ValueFPR, etc.) are done as fmt_long. */
+#define fmt_pw fmt_long
/* This should be the COC1 value at the start of the preceding
instruction: */
@@ -137,44 +100,6 @@ convert (SD, CPU, cia, rm, op, from, to)
#define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
#endif
-/* Standard FCRS bits: */
-#define IR (0) /* Inexact Result */
-#define UF (1) /* UnderFlow */
-#define OF (2) /* OverFlow */
-#define DZ (3) /* Division by Zero */
-#define IO (4) /* Invalid Operation */
-#define UO (5) /* Unimplemented Operation */
-
-/* Get masks for individual flags: */
-#if 1 /* SAFE version */
-#define FP_FLAGS(b) (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
-#define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
-#define FP_CAUSE(b) (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
-#else
-#define FP_FLAGS(b) (1 << ((b) + 2))
-#define FP_ENABLE(b) (1 << ((b) + 7))
-#define FP_CAUSE(b) (1 << ((b) + 12))
-#endif
-
-#define FP_FS (1 << 24) /* MIPS III onwards : Flush to Zero */
-
-#define FP_MASK_RM (0x3)
-#define FP_SH_RM (0)
-#define FP_RM_NEAREST (0) /* Round to nearest (Round) */
-#define FP_RM_TOZERO (1) /* Round to zero (Trunc) */
-#define FP_RM_TOPINF (2) /* Round to Plus infinity (Ceil) */
-#define FP_RM_TOMINF (3) /* Round to Minus infinity (Floor) */
-#define GETRM() (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
-
-/* start-sanitize-sky */
-#ifdef TARGET_SKY
-#ifdef SKY_FUNIT
-#include
-#include "wf.h"
-#endif
-#endif
-/* end-sanitize-sky */
-
@@ -219,213 +144,6 @@ typedef struct _hilo_history {
(ANS) = ALU64_OVERFLOW_RESULT;
-/* start-sanitize-r5900 */
-
-/* Figure 10-5 FPU Control/Status Register.
- Note: some of these bits are different to what is found in a
- standard MIPS manual. */
-enum {
- R5900_FCSR_C = BIT (23), /* OK */
- R5900_FCSR_I = BIT (17),
- R5900_FCSR_D = BIT (16),
- R5900_FCSR_O = BIT (15),
- R5900_FCSR_U = BIT (14),
- R5900_FCSR_CAUSE = MASK (16,14),
- R5900_FCSR_SI = BIT (6),
- R5900_FCSR_SD = BIT (5),
- R5900_FCSR_SO = BIT (4),
- R5900_FCSR_SU = BIT (3),
-};
-
-/* Table 10-1 FP format values.
- Note: some of these bits are different to what is found in a
- standard MIPS manual. */
-enum {
- R5900_EXPMAX = 128,
- R5900_EXPMIN = -127,
- R5900_EXPBIAS = 127,
-};
-
-/* MAX and MIN FP values */
-enum {
- R5900_FPMAX = LSMASK32 (30, 0),
- R5900_FPMIN = LSMASK32 (31, 0),
-};
-
-typedef struct _r4000_tlb_entry {
- unsigned32 mask;
- unsigned32 hi;
- unsigned32 lo0;
- unsigned32 lo1;
-} r4000_tlb_entry_t;
-
-#define TLB_MASK_MASK_MASK 0x01ffe000
-#define TLB_HI_VPN2_MASK 0xffffe000
-#define TLB_HI_G_MASK 0x00001000
-#define TLB_HI_ASID_MASK 0x000000ff
-
-#define TLB_LO_S_MASK 0x80000000
-#define TLB_LO_PFN_MASK 0x03ffffc0
-#define TLB_LO_C_MASK 0x00000038
-#define TLB_LO_D_MASK 0x00000004
-#define TLB_LO_V_MASK 0x00000002
-
-#define TLB_SIZE 48
-
-typedef struct _sim_r5900_cpu {
-
- /* The R5900 has 32 x 128bit general purpose registers.
- Fortunatly, the high 64 bits are only touched by multimedia (MMI)
- instructions. The normal mips instructions just use the lower 64
- bits. To avoid changing the older parts of the simulator to
- handle this weirdness, the high 64 bits of each register are kept
- in a separate array (registers1). The high 64 bits of any
- register are by convention refered by adding a '1' to the end of
- the normal register's name. So LO still refers to the low 64
- bits of the LO register, LO1 refers to the high 64 bits of that
- same register. */
- signed_word gpr1[32];
-#define GPR1 ((CPU)->r5900.gpr1)
-#define GPR1_SET(N,VAL) (GPR1[(N]) = (VAL))
- signed_word lo1;
- signed_word hi1;
-#define LO1 ((CPU)->r5900.lo1)
-#define HI1 ((CPU)->r5900.hi1)
-
- /* The R5900 defines a shift amount register, that controls the
- amount of certain shift instructions */
- unsigned_word sa; /* the shift amount register */
-#define REGISTER_SA (124) /* GET RID IF THIS! */
-#define SA ((CPU)->r5900.sa)
-
- /* The R5900, in addition to the (almost) standard floating point
- registers, defines a 32 bit accumulator. This is used in
- multiply/accumulate style instructions */
- fp_word acc; /* floating-point accumulator */
-#define ACC ((CPU)->r5900.acc)
-
- /* See comments below about needing to count cycles between updating
- and setting HI/LO registers */
- hilo_history hi1_history;
-#define HI1HISTORY (&(CPU)->r5900.hi1_history)
- hilo_history lo1_history;
-#define LO1HISTORY (&(CPU)->r5900.lo1_history)
-
- r4000_tlb_entry_t tlb[TLB_SIZE];
-#define TLB ((CPU)->r5900.tlb)
-
-} sim_r5900_cpu;
-
-#define BYTES_IN_MMI_REGS (sizeof(signed_word) + sizeof(signed_word))
-#define HALFWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/2)
-#define WORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/4)
-#define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
-
-#define BYTES_IN_MIPS_REGS (sizeof(signed_word))
-#define HALFWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/2)
-#define WORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/4)
-#define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
-
-/* SUB_REG_FETCH - return as lvalue some sub-part of a "register"
- T - type of the sub part
- TC - # of T's in the mips part of the "register"
- I - index (from 0) of desired sub part
- A - low part of "register"
- A1 - high part of register
-*/
-#define SUB_REG_FETCH(T,TC,A,A1,I) \
-(*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
- + (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
- ? ((TC) - 1 - (I) % (TC)) \
- : ((I) % (TC)) \
- ) \
- ) \
- )
-
-/*
-GPR_(R,I) - return, as lvalue, the I'th of general register R
- where has two letters:
- 1 is S=signed or U=unsigned
- 2 is B=byte H=halfword W=word D=doubleword
-*/
-
-#define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8, BYTES_IN_MIPS_REGS, A, A1, I)
-#define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS, A, A1, I)
-#define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS, A, A1, I)
-#define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
-
-#define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8, BYTES_IN_MIPS_REGS, A, A1, I)
-#define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS, A, A1, I)
-#define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS, A, A1, I)
-#define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
-
-#define GPR_SB(R,I) SUB_REG_SB(&GPR[R], &GPR1[R], I)
-#define GPR_SH(R,I) SUB_REG_SH(&GPR[R], &GPR1[R], I)
-#define GPR_SW(R,I) SUB_REG_SW(&GPR[R], &GPR1[R], I)
-#define GPR_SD(R,I) SUB_REG_SD(&GPR[R], &GPR1[R], I)
-
-#define GPR_UB(R,I) SUB_REG_UB(&GPR[R], &GPR1[R], I)
-#define GPR_UH(R,I) SUB_REG_UH(&GPR[R], &GPR1[R], I)
-#define GPR_UW(R,I) SUB_REG_UW(&GPR[R], &GPR1[R], I)
-#define GPR_UD(R,I) SUB_REG_UD(&GPR[R], &GPR1[R], I)
-
-#define TMP_DCL unsigned64 tmp_reg, tmp_reg1
-
-#define TMP_SB(I) SUB_REG_SB(&tmp_reg, &tmp_reg1, I)
-#define TMP_SH(I) SUB_REG_SH(&tmp_reg, &tmp_reg1, I)
-#define TMP_SW(I) SUB_REG_SW(&tmp_reg, &tmp_reg1, I)
-#define TMP_SD(I) SUB_REG_SD(&tmp_reg, &tmp_reg1, I)
-
-#define TMP_UB(I) SUB_REG_UB(&tmp_reg, &tmp_reg1, I)
-#define TMP_UH(I) SUB_REG_UH(&tmp_reg, &tmp_reg1, I)
-#define TMP_UW(I) SUB_REG_UW(&tmp_reg, &tmp_reg1, I)
-#define TMP_UD(I) SUB_REG_UD(&tmp_reg, &tmp_reg1, I)
-
-#define TMP_WRT(R) do { GPR[R] = tmp_reg; GPR1[R] = tmp_reg1; } while(0)
-
-#define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
-#define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
-#define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
-#define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
-
-#define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
-#define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
-#define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
-#define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
-
-#define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
-#define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
-#define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
-#define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
-
-#define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
-#define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
-#define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
-#define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
-
-
-
-#define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
-#define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
-#define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
-#define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
-
-#define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
-#define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
-#define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
-#define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
-
-#define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
-#define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
-#define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
-#define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
-
-#define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
-#define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
-#define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
-#define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
-
-/* end-sanitize-r5900 */
@@ -502,23 +220,46 @@ memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
/* For backward compatibility */
#define PENDING_FILL(R,VAL) \
do { \
- if ((R) >= FGRIDX && (R) < FGRIDX + NR_FGR) \
+ if ((R) >= FGR_BASE && (R) < FGR_BASE + NR_FGR) \
{ \
- PENDING_SCHED(FGR[(R) - FGRIDX], VAL, 1, -1); \
- PENDING_SCHED(FPR_STATE[(R) - FGRIDX], fmt_uninterpreted, 1, -1); \
+ PENDING_SCHED(FGR[(R) - FGR_BASE], VAL, 1, -1); \
+ PENDING_SCHED(FPR_STATE[(R) - FGR_BASE], fmt_uninterpreted, 1, -1); \
} \
else \
PENDING_SCHED(GPR[(R)], VAL, 1, -1); \
} while (0)
+enum float_operation
+ {
+ FLOP_ADD, FLOP_SUB, FLOP_MUL, FLOP_MADD,
+ FLOP_MSUB, FLOP_MAX=10, FLOP_MIN, FLOP_ABS,
+ FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
+ };
+
+
+/* The internal representation of an MDMX accumulator.
+ Note that 24 and 48 bit accumulator elements are represented in
+ 32 or 64 bits. Since the accumulators are 2's complement with
+ overflow suppressed, high-order bits can be ignored in most contexts. */
+
+typedef signed32 signed24;
+typedef signed64 signed48;
+
+typedef union {
+ signed24 ob[8];
+ signed48 qh[4];
+} MDMX_accumulator;
+
+
+/* Conventional system arguments. */
+#define SIM_STATE sim_cpu *cpu, address_word cia
+#define SIM_ARGS CPU, cia
struct _sim_cpu {
/* The following are internal simulator state variables: */
-#define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
-#define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
address_word dspc; /* delay-slot PC */
#define DSPC ((CPU)->dspc)
@@ -543,6 +284,7 @@ struct _sim_cpu {
#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
+#ifndef ENGINE_ISSUE_PREFIX_HOOK
#define ENGINE_ISSUE_PREFIX_HOOK() \
{ \
/* Perform any pending writes */ \
@@ -558,6 +300,7 @@ struct _sim_cpu {
else \
STATE &= ~simPCOC0; \
}
+#endif /* ENGINE_ISSUE_PREFIX_HOOK */
/* This is nasty, since we have to rely on matching the register
@@ -568,46 +311,14 @@ struct _sim_cpu {
state. */
#ifndef TM_MIPS_H
-#define LAST_EMBED_REGNUM (89)
+#define LAST_EMBED_REGNUM (96)
#define NUM_REGS (LAST_EMBED_REGNUM + 1)
-/* start-sanitize-r5900 */
-#define FIRST_COP0_REG 128
-#define NUM_COP0_REGS 22
-#undef NUM_REGS
-#define NUM_REGS (150)
-/* end-sanitize-r5900 */
-
+#define FP0_REGNUM 38 /* Floating point register 0 (single float) */
+#define FCRCS_REGNUM 70 /* FP control/status */
+#define FCRIR_REGNUM 71 /* FP implementation/revision */
#endif
-/* start-sanitize-sky */
-#ifdef TARGET_SKY
-#ifndef TM_TXVU_H
-/* Number of machine registers */
-#define NUM_VU_REGS 160
-
-#define NUM_VU_INTEGER_REGS 16
-#define FIRST_VEC_REG 32
-
-#define NUM_VIF_REGS 26
-
-#define NUM_CORE_REGS 150
-
-#undef NUM_REGS
-#define NUM_REGS (NUM_CORE_REGS + 2*(NUM_VU_REGS) + 2*(NUM_VIF_REGS))
-#endif /* no tm-txvu.h */
-#endif /* TARGET_SKY */
-/* end-sanitize-sky */
-
-enum float_operation
-/* start-sanitize-sky */
-/* NOTE: THE VALUES of THESE CONSTANTS MUST BE IN SYNC WITH THOSE IN WF.H */
-/* end-sanitize-sky */
- {
- FLOP_ADD, FLOP_SUB, FLOP_MUL, FLOP_MADD,
- FLOP_MSUB, FLOP_MAX=10, FLOP_MIN, FLOP_ABS,
- FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
- };
/* To keep this default simulator simple, and fast, we use a direct
vector of registers. The internal simulator engine then uses
@@ -621,15 +332,6 @@ enum float_operation
#define GPR (®ISTERS[0])
#define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
- /* While space is allocated for the floating point registers in the
- main registers array, they are stored separatly. This is because
- their size may not necessarily match the size of either the
- general-purpose or system specific registers */
-#define NR_FGR (32)
-#define FGRIDX (38)
- fp_word fgr[NR_FGR];
-#define FGR ((CPU)->fgr)
-
#define LO (REGISTERS[33])
#define HI (REGISTERS[34])
#define PCIDX 37
@@ -645,7 +347,52 @@ enum float_operation
#define Debug (REGISTERS[86])
#define DEPC (REGISTERS[87])
#define EPC (REGISTERS[88])
-#define COCIDX (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
+#define ACX (REGISTERS[89])
+
+#define AC0LOIDX (33) /* Must be the same register as LO */
+#define AC0HIIDX (34) /* Must be the same register as HI */
+#define AC1LOIDX (90)
+#define AC1HIIDX (91)
+#define AC2LOIDX (92)
+#define AC2HIIDX (93)
+#define AC3LOIDX (94)
+#define AC3HIIDX (95)
+
+#define DSPLO(N) (REGISTERS[DSPLO_REGNUM[N]])
+#define DSPHI(N) (REGISTERS[DSPHI_REGNUM[N]])
+
+#define DSPCRIDX (96) /* DSP control register */
+#define DSPCR (REGISTERS[DSPCRIDX])
+
+#define DSPCR_POS_SHIFT (0)
+#define DSPCR_POS_MASK (0x3f)
+#define DSPCR_POS_SMASK (DSPCR_POS_MASK << DSPCR_POS_SHIFT)
+
+#define DSPCR_SCOUNT_SHIFT (7)
+#define DSPCR_SCOUNT_MASK (0x3f)
+#define DSPCR_SCOUNT_SMASK (DSPCR_SCOUNT_MASK << DSPCR_SCOUNT_SHIFT)
+
+#define DSPCR_CARRY_SHIFT (13)
+#define DSPCR_CARRY_MASK (1)
+#define DSPCR_CARRY_SMASK (DSPCR_CARRY_MASK << DSPCR_CARRY_SHIFT)
+#define DSPCR_CARRY (1 << DSPCR_CARRY_SHIFT)
+
+#define DSPCR_EFI_SHIFT (14)
+#define DSPCR_EFI_MASK (1)
+#define DSPCR_EFI_SMASK (DSPCR_EFI_MASK << DSPCR_EFI_SHIFT)
+#define DSPCR_EFI (1 << DSPCR_EFI_MASK)
+
+#define DSPCR_OUFLAG_SHIFT (16)
+#define DSPCR_OUFLAG_MASK (0xff)
+#define DSPCR_OUFLAG_SMASK (DSPCR_OUFLAG_MASK << DSPCR_OUFLAG_SHIFT)
+#define DSPCR_OUFLAG4 (1 << (DSPCR_OUFLAG_SHIFT + 4))
+#define DSPCR_OUFLAG5 (1 << (DSPCR_OUFLAG_SHIFT + 5))
+#define DSPCR_OUFLAG6 (1 << (DSPCR_OUFLAG_SHIFT + 6))
+#define DSPCR_OUFLAG7 (1 << (DSPCR_OUFLAG_SHIFT + 7))
+
+#define DSPCR_CCOND_SHIFT (24)
+#define DSPCR_CCOND_MASK (0xf)
+#define DSPCR_CCOND_SMASK (DSPCR_CCOND_MASK << DSPCR_CCOND_SHIFT)
/* All internal state modified by signal_exception() that may need to be
rolled back for passing moment-of-exception image back to gdb. */
@@ -681,39 +428,16 @@ enum float_operation
#define NR_COP0_GPR 32
unsigned_word cop0_gpr[NR_COP0_GPR];
#define COP0_GPR ((CPU)->cop0_gpr)
- /* start-sanitize-r5900 */
-#define NR_COP0_BP 8
- unsigned_word cop0_bp[NR_COP0_BP];
-#define COP0_BP ((CPU)->cop0_bp)
-#define NR_COP0_P 64
- unsigned_word cop0_p[NR_COP0_P];
-
-#define COP0_P ((CPU)->cop0_p)
-#define COP0_INDEX ((unsigned32)(COP0_GPR[0]))
-#define COP0_RANDOM ((unsigned32)(COP0_GPR[1]))
-#define COP0_ENTRYLO0 ((unsigned32)(COP0_GPR[2]))
-#define COP0_ENTRYLO1 ((unsigned32)(COP0_GPR[3]))
-#define COP0_CONTEXT ((unsigned32)(COP0_GPR[4]))
-#define COP0_PAGEMASK ((unsigned32)(COP0_GPR[5]))
-#define COP0_WIRED ((unsigned32)(COP0_GPR[6]))
- /* end-sanitize-r5900 */
-#define COP0_BADVADDR ((unsigned32)(COP0_GPR[8]))
- /* start-sanitize-r5900 */
-#define COP0_COUNT ((unsigned32)(COP0_GPR[9]))
-#define COP0_ENTRYHI ((unsigned32)(COP0_GPR[10]))
-#define COP0_COMPARE ((unsigned32)(COP0_GPR[11]))
-#define COP0_EPC ((unsigned32)(EPC)) /* 14 */
-#define COP0_PRID ((unsigned32)(COP0_GPR[15]))
-#define COP0_CONFIG ((unsigned32)(C0_CONFIG)) /* 16 */
-#define COP0_TAGLO ((unsigned32)(COP0_GPR[28]))
-#define COP0_TAGHI ((unsigned32)(COP0_GPR[29]))
-#define COP0_ERROREPC ((unsigned32)(COP0_GPR[30]))
-
-#define COP0_CONTEXT_BADVPN2_MASK 0x007ffff0
-
-#define COP0_CONTEXT_set_BADVPN2(x) \
- (COP0_CONTEXT = ((COP0_CONTEXT & 0xff100000) | ((x << 4) & 0x007ffff0)))
- /* end-sanitize-r5900 */
+#define COP0_BADVADDR (COP0_GPR[8])
+
+ /* While space is allocated for the floating point registers in the
+ main registers array, they are stored separatly. This is because
+ their size may not necessarily match the size of either the
+ general-purpose or system specific registers. */
+#define NR_FGR (32)
+#define FGR_BASE FP0_REGNUM
+ fp_word fgr[NR_FGR];
+#define FGR ((CPU)->fgr)
/* Keep the current format state for each register: */
FP_formats fpr_state[32];
@@ -721,6 +445,10 @@ enum float_operation
pending_write_queue pending;
+ /* The MDMX accumulator (used only for MDMX ASE). */
+ MDMX_accumulator acc;
+#define ACC ((CPU)->acc)
+
/* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
read-write instructions. It is set when a linked load occurs. It
is tested and cleared by the conditional store. It is cleared
@@ -740,47 +468,16 @@ enum float_operation
hilo_history lo_history;
#define LOHISTORY (&(CPU)->lo_history)
- /* start-sanitize-branchbug4011 */
-#if 1
- int branchbug4011_option;
-#define BRANCHBUG4011_OPTION ((CPU)->branchbug4011_option)
- address_word branchbug4011_last_target;
-#define BRANCHBUG4011_LAST_TARGET ((CPU)->branchbug4011_last_target)
- address_word branchbug4011_last_cia;
-#define BRANCHBUG4011_LAST_CIA ((CPU)->branchbug4011_last_cia)
-
-#define check_branch_bug() (check_4011_branch_bug (_SD))
-#define mark_branch_bug(TARGET) (mark_4011_branch_bug (_SD,TARGET))
-#else
- /* end-sanitize-branchbug4011 */
-#define check_branch_bug()
-#define mark_branch_bug(TARGET)
- /* start-sanitize-branchbug4011 */
-#endif
- /* end-sanitize-branchbug4011 */
- /* start-sanitize-r5900 */
- sim_r5900_cpu r5900;
- /* end-sanitize-r5900 */
-
- /* start-sanitize-cygnus */
- /* The MDMX ISA has a very very large accumulator */
- unsigned8 acc[3 * 8];
- /* end-sanitize-cygnus */
-
- /* start-sanitize-sky */
-#ifdef TARGET_SKY
- /* Device on which instruction issue last occured. */
- char cur_device;
-#endif
- /* end-sanitize-sky */
sim_cpu_base base;
};
+extern void mips_sim_close (SIM_DESC sd, int quitting);
+#define SIM_CLOSE_HOOK(...) mips_sim_close (__VA_ARGS__)
/* MIPS specific simulator watch config */
-void watch_options_install PARAMS ((SIM_DESC sd));
+void watch_options_install (SIM_DESC sd);
struct swatch {
sim_event *pc;
@@ -794,39 +491,10 @@ struct sim_state {
struct swatch watch;
- sim_cpu cpu[MAX_NR_PROCESSORS];
-#if (WITH_SMP)
-#define STATE_CPU(sd,n) (&(sd)->cpu[n])
-#else
-#define STATE_CPU(sd,n) (&(sd)->cpu[0])
-#endif
-
-/* start-sanitize-sky */
-#ifdef TARGET_SKY
-
-#ifdef SKY_FUNIT
- /* Record of option for floating point implementation type. */
- int fp_type_opt;
-#define STATE_FP_TYPE_OPT(sd) ((sd)->fp_type_opt)
-#define STATE_FP_TYPE_OPT_ACCURATE 0x80000000
-#endif
-
- /* Index of next unused name slot for multi-phase load list. */
- int next_mload_count;
-#define STATE_MLOAD_COUNT(sd) ((sd)->next_mload_count)
-
-#define MAX_MLOAD_COUNT 2 /* limit for next_load_count and load_index */
-
- /* Program names for multi-phase load. */
- char *next_mload_name[MAX_MLOAD_COUNT];
-#define STATE_MLOAD_NAME(sd) ((sd)->next_mload_name)
+ sim_cpu *cpu[MAX_NR_PROCESSORS];
- /* Index of next program for multi-phase load. */
- int mload_index;
-#define STATE_MLOAD_INDEX(sd) ((sd)->mload_index)
-
-#endif
-/* end-sanitize-sky */
+ /* microMIPS ISA mode. */
+ int isa_mode;
sim_state_base base;
};
@@ -858,11 +526,6 @@ struct sim_state {
#define status_ERL (1 << 2) /* Error level */
#define status_IM7 (1 << 15) /* Timer Interrupt Mask */
#define status_RP (1 << 27) /* Reduced Power mode */
-/* start-sanitize-r5900 */
-#define status_CU0 (1 << 28) /* COP0 usable */
-#define status_CU1 (1 << 29) /* COP1 usable */
-#define status_CU2 (1 << 30) /* COP2 usable */
-/* end-sanitize-r5900 */
/* Specializations for TX39 family */
#define status_IEc (1 << 0) /* Interrupt enable (current) */
@@ -876,6 +539,20 @@ struct sim_state {
#define status_NMI (1 << 20) /* NMI */
#define status_NMI (1 << 20) /* NMI */
+/* Status bits used by MIPS32/MIPS64. */
+#define status_UX (1 << 5) /* 64-bit user addrs */
+#define status_SX (1 << 6) /* 64-bit supervisor addrs */
+#define status_KX (1 << 7) /* 64-bit kernel addrs */
+#define status_TS (1 << 21) /* TLB shutdown has occurred */
+#define status_PX (1 << 23) /* Enable 64 bit operations */
+#define status_MX (1 << 24) /* Enable MDMX resources */
+#define status_CU0 (1 << 28) /* Coprocessor 0 usable */
+#define status_CU1 (1 << 29) /* Coprocessor 1 usable */
+#define status_CU2 (1 << 30) /* Coprocessor 2 usable */
+#define status_CU3 (1 << 31) /* Coprocessor 3 usable */
+/* Bits reserved for implementations: */
+#define status_SBX (1 << 16) /* Enable SiByte SB-1 extensions. */
+
#define cause_BD ((unsigned)1 << 31) /* L1 Exception in branch delay slot */
#define cause_BD2 (1 << 30) /* L2 Exception in branch delay slot */
#define cause_CE_mask 0x30000000 /* Coprocessor exception */
@@ -887,15 +564,7 @@ struct sim_state {
#define cause_IP3 (1 << 11) /* Int 0 pending */
#define cause_IP2 (1 << 10) /* Int 1 pending */
-/* start-sanitize-sky */
-#ifdef TARGET_SKY
-#define cause_EXC_mask (0x7c) /* Exception code */
-#else
-/* end-sanitize-sky */
#define cause_EXC_mask (0x1c) /* Exception code */
-/* start-sanitize-sky */
-#endif
-/* end-sanitize-sky */
#define cause_EXC_shift (2)
#define cause_SW0 (1 << 8) /* Software interrupt 0 */
@@ -923,7 +592,7 @@ struct sim_state {
/* Hardware configuration. Affects endianness of LoadMemory and
StoreMemory and the endianness of Kernel and Supervisor mode
execution. The value is 0 for little-endian; 1 for big-endian. */
-#define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
+#define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
/*(state & simBE) ? 1 : 0)*/
/* ReverseEndian */
@@ -961,9 +630,12 @@ enum ExceptionCause {
IntegerOverflow = 12, /* Arithmetic overflow (IDT monitor raises SIGFPE) */
Trap = 13,
FPE = 15,
- DebugBreakPoint = 16,
+ DebugBreakPoint = 16, /* Impl. dep. in MIPS32/MIPS64. */
+ MDMX = 22,
Watch = 23,
- NMIReset = 31,
+ MCheck = 24,
+ CacheErr = 30,
+ NMIReset = 31, /* Reserved in MIPS32/MIPS64. */
/* The following exception code is actually private to the simulator
@@ -975,13 +647,6 @@ enum ExceptionCause {
#define TLB_REFILL (0)
#define TLB_INVALID (1)
-/* start-sanitize-r5900 */
-/* For the 5900, we have level 1 and level 2 exceptions. The level 2 exceptions
- are ColdReset, NMI, Counter, and Debug/SIO. Of these, we support only
- the NMIReset exception. */
-
-#define is5900Level2Exception(x) (x == NMIReset)
-/* end-sanitize-r5900 */
/* The following break instructions are reserved for use by the
simulator. The first is used to halt the simulation. The second
@@ -992,18 +657,10 @@ enum ExceptionCause {
#define HALT_INSTRUCTION (0x03ff000d)
#define HALT_INSTRUCTION2 (0x0000ffcd)
-/* start-sanitize-sky */
-#define HALT_INSTRUCTION_PASS (0x03fffc0d) /* break 0xffff0 */
-#define HALT_INSTRUCTION_FAIL (0x03ffffcd) /* break 0xfffff */
-/* end-sanitize-sky */
#define BREAKPOINT_INSTRUCTION (0x0005000d)
#define BREAKPOINT_INSTRUCTION2 (0x0000014d)
-/* start-sanitize-sky */
-#define LOAD_INSTRUCTION (0x03fffc4d) /* break 0xffff1 */
-#define PRINTF_INSTRUCTION (0x03fffc8d) /* break 0xffff2 */
-/* end-sanitize-sky */
void interrupt_event (SIM_DESC sd, void *data);
@@ -1018,20 +675,27 @@ void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exceptio
#define SignalExceptionSimulatorFault(buf) signal_exception (SD, CPU, cia, SimulatorFault, buf)
#define SignalExceptionFPE() signal_exception (SD, CPU, cia, FPE)
#define SignalExceptionIntegerOverflow() signal_exception (SD, CPU, cia, IntegerOverflow)
-#define SignalExceptionCoProcessorUnusable() signal_exception (SD, CPU, cia, CoProcessorUnusable)
+#define SignalExceptionCoProcessorUnusable(cop) signal_exception (SD, CPU, cia, CoProcessorUnusable)
#define SignalExceptionNMIReset() signal_exception (SD, CPU, cia, NMIReset)
#define SignalExceptionTLBRefillStore() signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL)
#define SignalExceptionTLBRefillLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL)
#define SignalExceptionTLBInvalidStore() signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID)
#define SignalExceptionTLBInvalidLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID)
#define SignalExceptionTLBModification() signal_exception (SD, CPU, cia, TLBModification)
+#define SignalExceptionMDMX() signal_exception (SD, CPU, cia, MDMX)
+#define SignalExceptionWatch() signal_exception (SD, CPU, cia, Watch)
+#define SignalExceptionMCheck() signal_exception (SD, CPU, cia, MCheck)
+#define SignalExceptionCacheErr() signal_exception (SD, CPU, cia, CacheErr)
/* Co-processor accesses */
-void cop_lw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
-void cop_ld PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
-unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
-uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
+/* XXX FIXME: For now, assume that FPU (cp1) is always usable. */
+#define COP_Usable(coproc_num) (coproc_num == 1)
+
+void cop_lw (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword);
+void cop_ld (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword);
+unsigned int cop_sw (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg);
+uword64 cop_sd (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg);
#define COP_LW(coproc_num,coproc_reg,memword) \
cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
@@ -1042,38 +706,208 @@ cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
#define COP_SD(coproc_num,coproc_reg) \
cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
-/* start-sanitize-sky */
-#ifdef TARGET_SKY
-void cop_lq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia,
- int coproc_num, int coproc_reg, unsigned128 memword));
-unsigned128 cop_sq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia,
- int coproc_num, int coproc_reg));
-#define COP_LQ(coproc_num,coproc_reg,memword) \
-cop_lq (SD, CPU, cia, coproc_num, coproc_reg, memword)
-#define COP_SQ(coproc_num,coproc_reg) \
-cop_sq (SD, CPU, cia, coproc_num, coproc_reg)
-#endif /* TARGET_SKY */
-/* end-sanitize-sky */
-
-void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction));
-#define DecodeCoproc(instruction) \
-decode_coproc (SD, CPU, cia, (instruction))
-
-void sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
+
+void decode_coproc (SIM_DESC sd, sim_cpu *cpu, address_word cia,
+ unsigned int instruction, int coprocnum, CP0_operation op,
+ int rt, int rd, int sel);
+#define DecodeCoproc(instruction,coprocnum,op,rt,rd,sel) \
+ decode_coproc (SD, CPU, cia, (instruction), (coprocnum), (op), \
+ (rt), (rd), (sel))
+
+int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
+/* FPR access. */
+unsigned64 value_fpr (SIM_STATE, int fpr, FP_formats);
+#define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT))
+void store_fpr (SIM_STATE, int fpr, FP_formats fmt, unsigned64 value);
+#define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE))
+unsigned64 ps_lower (SIM_STATE, unsigned64 op);
+#define PSLower(op) ps_lower (SIM_ARGS, op)
+unsigned64 ps_upper (SIM_STATE, unsigned64 op);
+#define PSUpper(op) ps_upper (SIM_ARGS, op)
+unsigned64 pack_ps (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats from);
+#define PackPS(op1,op2) pack_ps (SIM_ARGS, op1, op2, fmt_single)
+
+
+/* FCR access. */
+unsigned_word value_fcr (SIM_STATE, int fcr);
+#define ValueFCR(FCR) value_fcr (SIM_ARGS, (FCR))
+void store_fcr (SIM_STATE, int fcr, unsigned_word value);
+#define StoreFCR(FCR,VALUE) store_fcr (SIM_ARGS, (FCR), (VALUE))
+void test_fcsr (SIM_STATE);
+#define TestFCSR() test_fcsr (SIM_ARGS)
+
+
+/* FPU operations. */
+void fp_cmp (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt, int abs, int cond, int cc);
+#define Compare(op1,op2,fmt,cond,cc) fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc)
+unsigned64 fp_abs (SIM_STATE, unsigned64 op, FP_formats fmt);
+#define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt)
+unsigned64 fp_neg (SIM_STATE, unsigned64 op, FP_formats fmt);
+#define Negate(op,fmt) fp_neg(SIM_ARGS, op, fmt)
+unsigned64 fp_add (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
+#define Add(op1,op2,fmt) fp_add(SIM_ARGS, op1, op2, fmt)
+unsigned64 fp_sub (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
+#define Sub(op1,op2,fmt) fp_sub(SIM_ARGS, op1, op2, fmt)
+unsigned64 fp_mul (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
+#define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt)
+unsigned64 fp_div (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
+#define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt)
+unsigned64 fp_recip (SIM_STATE, unsigned64 op, FP_formats fmt);
+#define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt)
+unsigned64 fp_sqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
+#define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt)
+unsigned64 fp_rsqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
+#define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt)
+unsigned64 fp_madd (SIM_STATE, unsigned64 op1, unsigned64 op2,
+ unsigned64 op3, FP_formats fmt);
+#define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt)
+unsigned64 fp_msub (SIM_STATE, unsigned64 op1, unsigned64 op2,
+ unsigned64 op3, FP_formats fmt);
+#define MultiplySub(op1,op2,op3,fmt) fp_msub(SIM_ARGS, op1, op2, op3, fmt)
+unsigned64 fp_nmadd (SIM_STATE, unsigned64 op1, unsigned64 op2,
+ unsigned64 op3, FP_formats fmt);
+#define NegMultiplyAdd(op1,op2,op3,fmt) fp_nmadd(SIM_ARGS, op1, op2, op3, fmt)
+unsigned64 fp_nmsub (SIM_STATE, unsigned64 op1, unsigned64 op2,
+ unsigned64 op3, FP_formats fmt);
+#define NegMultiplySub(op1,op2,op3,fmt) fp_nmsub(SIM_ARGS, op1, op2, op3, fmt)
+unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to);
+#define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to)
+unsigned64 convert_ps (SIM_STATE, int rm, unsigned64 op, FP_formats from,
+ FP_formats to);
+#define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to)
+
+
+/* MIPS-3D ASE operations. */
+#define CompareAbs(op1,op2,fmt,cond,cc) \
+fp_cmp(SIM_ARGS, op1, op2, fmt, 1, cond, cc)
+unsigned64 fp_add_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
+#define AddR(op1,op2,fmt) fp_add_r(SIM_ARGS, op1, op2, fmt)
+unsigned64 fp_mul_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
+#define MultiplyR(op1,op2,fmt) fp_mul_r(SIM_ARGS, op1, op2, fmt)
+unsigned64 fp_recip1 (SIM_STATE, unsigned64 op, FP_formats fmt);
+#define Recip1(op,fmt) fp_recip1(SIM_ARGS, op, fmt)
+unsigned64 fp_recip2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
+#define Recip2(op1,op2,fmt) fp_recip2(SIM_ARGS, op1, op2, fmt)
+unsigned64 fp_rsqrt1 (SIM_STATE, unsigned64 op, FP_formats fmt);
+#define RSquareRoot1(op,fmt) fp_rsqrt1(SIM_ARGS, op, fmt)
+unsigned64 fp_rsqrt2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
+#define RSquareRoot2(op1,op2,fmt) fp_rsqrt2(SIM_ARGS, op1, op2, fmt)
+
+
+/* MDMX access. */
+
+typedef unsigned int MX_fmtsel; /* MDMX format select field (5 bits). */
+#define ob_fmtsel(sel) (((sel)<<1)|0x0)
+#define qh_fmtsel(sel) (((sel)<<2)|0x1)
+
+#define fmt_mdmx fmt_uninterpreted
+
+#define MX_VECT_AND (0)
+#define MX_VECT_NOR (1)
+#define MX_VECT_OR (2)
+#define MX_VECT_XOR (3)
+#define MX_VECT_SLL (4)
+#define MX_VECT_SRL (5)
+#define MX_VECT_ADD (6)
+#define MX_VECT_SUB (7)
+#define MX_VECT_MIN (8)
+#define MX_VECT_MAX (9)
+#define MX_VECT_MUL (10)
+#define MX_VECT_MSGN (11)
+#define MX_VECT_SRA (12)
+#define MX_VECT_ABSD (13) /* SB-1 only. */
+#define MX_VECT_AVG (14) /* SB-1 only. */
+
+unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
+#define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel)
+#define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel)
+#define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel)
+#define MX_Min(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MIN, op1, vt, fmtsel)
+#define MX_Msgn(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MSGN, op1, vt, fmtsel)
+#define MX_Mul(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MUL, op1, vt, fmtsel)
+#define MX_Nor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_NOR, op1, vt, fmtsel)
+#define MX_Or(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_OR, op1, vt, fmtsel)
+#define MX_ShiftLeftLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SLL, op1, vt, fmtsel)
+#define MX_ShiftRightArith(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRA, op1, vt, fmtsel)
+#define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel)
+#define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel)
+#define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel)
+#define MX_AbsDiff(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ABSD, op1, vt, fmtsel)
+#define MX_Avg(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AVG, op1, vt, fmtsel)
+
+#define MX_C_EQ 0x1
+#define MX_C_LT 0x4
+
+void mdmx_cc_op (SIM_STATE, int cond, unsigned64 op1, int vt, MX_fmtsel fmtsel);
+#define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel)
+
+unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fmtsel);
+#define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel)
+
+#define MX_VECT_ADDA (0)
+#define MX_VECT_ADDL (1)
+#define MX_VECT_MULA (2)
+#define MX_VECT_MULL (3)
+#define MX_VECT_MULS (4)
+#define MX_VECT_MULSL (5)
+#define MX_VECT_SUBA (6)
+#define MX_VECT_SUBL (7)
+#define MX_VECT_ABSDA (8) /* SB-1 only. */
+
+void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
+#define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel)
+#define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel)
+#define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel)
+#define MX_MulL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULL, op1, vt, fmtsel)
+#define MX_MulS(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULS, op1, vt, fmtsel)
+#define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel)
+#define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel)
+#define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel)
+#define MX_AbsDiffC(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ABSDA, op1, vt, fmtsel)
+
+#define MX_FMT_OB (0)
+#define MX_FMT_QH (1)
+
+/* The following codes chosen to indicate the units of shift. */
+#define MX_RAC_L (0)
+#define MX_RAC_M (1)
+#define MX_RAC_H (2)
+
+unsigned64 mdmx_rac_op (SIM_STATE, int, int);
+#define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt)
+
+void mdmx_wacl (SIM_STATE, int, unsigned64, unsigned64);
+#define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt)
+void mdmx_wach (SIM_STATE, int, unsigned64);
+#define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs)
+
+#define MX_RND_AS (0)
+#define MX_RND_AU (1)
+#define MX_RND_ES (2)
+#define MX_RND_EU (3)
+#define MX_RND_ZS (4)
+#define MX_RND_ZU (5)
+
+unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel);
+#define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt)
+#define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt)
+#define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt)
+#define MX_RNEU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_EU, vt, fmt)
+#define MX_RZS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt)
+#define MX_RZU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt)
+
+unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64);
+#define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2)
+
+
/* Memory accesses */
/* The following are generic to all versions of the MIPS architecture
to date: */
-/* Memory Access Types (for CCA): */
-#define Uncached (0)
-#define CachedNoncoherent (1)
-#define CachedCoherent (2)
-#define Cached (3)
-
#define isINSTRUCTION (1 == 0) /* FALSE */
#define isDATA (1 == 1) /* TRUE */
#define isLOAD (1 == 0) /* FALSE */
@@ -1102,105 +936,93 @@ void sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg)
#define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
-INLINE_SIM_MAIN (int) address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
-#define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
-address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
-
-INLINE_SIM_MAIN (void) load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD));
-#define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
-load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
+INLINE_SIM_MAIN (void) load_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD);
+#define LoadMemory(memvalp,memval1p,AccessLength,pAddr,vAddr,IorD,raw) \
+load_memory (SD, CPU, cia, memvalp, memval1p, 0, AccessLength, pAddr, vAddr, IorD)
-INLINE_SIM_MAIN (void) store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
-#define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
-store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
+INLINE_SIM_MAIN (void) store_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr);
+#define StoreMemory(AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
+store_memory (SD, CPU, cia, 0, AccessLength, MemElem, MemElem1, pAddr, vAddr)
-INLINE_SIM_MAIN (void) cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
+INLINE_SIM_MAIN (void) cache_op (SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction);
#define CacheOp(op,pAddr,vAddr,instruction) \
cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
-INLINE_SIM_MAIN (void) sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype));
+INLINE_SIM_MAIN (void) sync_operation (SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype);
#define SyncOperation(stype) \
sync_operation (SD, CPU, cia, (stype))
-INLINE_SIM_MAIN (void) prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
-#define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
-prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
+void unpredictable_action (sim_cpu *cpu, address_word cia);
+#define NotWordValue(val) not_word_value (SD_, (val))
+#define Unpredictable() unpredictable (SD_)
+#define UnpredictableResult() /* For now, do nothing. */
-INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
+INLINE_SIM_MAIN (unsigned32) ifetch32 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr);
#define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
-INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
+INLINE_SIM_MAIN (unsigned16) ifetch16 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr);
#define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
#define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
+#define IMEM32_MICROMIPS(CIA) \
+ (ifetch16 (SD, CPU, (CIA), (CIA)) << 16 | ifetch16 (SD, CPU, (CIA + 2), \
+ (CIA + 2)))
+#define IMEM16_MICROMIPS(CIA) ifetch16 (SD, CPU, (CIA), ((CIA)))
-void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
-extern FILE *tracefh;
-
-INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
-extern SIM_CORE_SIGNAL_FN mips_core_signal;
+#define MICROMIPS_MINOR_OPCODE(INSN) ((INSN & 0x1C00) >> 10)
-char* pr_addr PARAMS ((SIM_ADDR addr));
-char* pr_uword64 PARAMS ((uword64 addr));
+#define MICROMIPS_DELAYSLOT_SIZE_ANY 0
+#define MICROMIPS_DELAYSLOT_SIZE_16 2
+#define MICROMIPS_DELAYSLOT_SIZE_32 4
-/* start-sanitize-sky */
-#ifdef TARGET_SKY
+extern int isa_mode;
-#ifdef SIM_ENGINE_HALT_HOOK
-#undef SIM_ENGINE_HALT_HOOK
-#endif
+#define ISA_MODE_MIPS32 0
+#define ISA_MODE_MICROMIPS 1
-void sky_sim_engine_halt PARAMS ((SIM_DESC sd, sim_cpu *last, sim_cia cia));
-#define SIM_ENGINE_HALT_HOOK(sd, last, cia) sky_sim_engine_halt(sd, last, cia)
+address_word micromips_instruction_decode (SIM_DESC sd, sim_cpu * cpu,
+ address_word cia,
+ int instruction_size);
-#ifdef SIM_ENGINE_RESTART_HOOK
-#undef SIM_ENGINE_RESTART_HOOK
+#if WITH_TRACE_ANY_P
+void dotrace (SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...);
+extern FILE *tracefh;
+#else
+#define dotrace(sd, cpu, tracefh, type, address, width, comment, ...)
#endif
-void sky_sim_engine_restart PARAMS ((SIM_DESC sd, sim_cpu *last, sim_cia cia));
-#define SIM_ENGINE_RESTART_HOOK(sd, L, pc) sky_sim_engine_restart(sd, L, pc)
+extern int DSPLO_REGNUM[4];
+extern int DSPHI_REGNUM[4];
-/* for resume/suspend modules */
-SIM_RC sky_sim_module_install PARAMS ((SIM_DESC sd));
+INLINE_SIM_MAIN (void) pending_tick (SIM_DESC sd, sim_cpu *cpu, address_word cia);
+extern SIM_CORE_SIGNAL_FN mips_core_signal;
-#define MODULE_LIST sky_sim_module_install,
-
-#ifndef TM_TXVU_H /* In case GDB hasn't been configured yet */
-enum txvu_cpu_context
-{
- TXVU_CPU_AUTO = -1, /* context-sensitive context */
- TXVU_CPU_MASTER = 0, /* R5900 core */
- TXVU_CPU_VU0 = 1, /* Vector units */
- TXVU_CPU_VU1 = 2,
- TXVU_CPU_VIF0 = 3, /* Vector interface units */
- TXVU_CPU_VIF1 = 4,
- TXVU_CPU_LAST /* Count of context types */
-};
+char* pr_addr (SIM_ADDR addr);
+char* pr_uword64 (uword64 addr);
-/* memory segment for communication with GDB */
-#define VIO_BASE 0xa0000000
-#define GDB_COMM_AREA 0x19810000 /* Random choice */
-#define GDB_COMM_SIZE 0x4000
-/* Memory address containing last device to execute */
-#define LAST_DEVICE GDB_COMM_AREA
+#define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0)
-/* The FIFO breakpoint count and table */
-#define FIFO_BPT_CNT (GDB_COMM_AREA + 4)
-#define FIFO_BPT_TBL (GDB_COMM_AREA + 8)
+void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
+void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
+void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
-/* Each element of the breakpoint table is three four-byte integers. */
-#define BPT_ELEM_SZ 4*3
+#ifdef MIPS_MACH_MULTI
+extern int mips_mach_multi(SIM_DESC sd);
+#define MIPS_MACH(SD) mips_mach_multi(SD)
+#else
+#define MIPS_MACH(SD) MIPS_MACH_DEFAULT
+#endif
-#define TXVU_VU_BRK_MASK 0x02 /* Breakpoint bit is #57 for VU insns */
-#define TXVU_VIF_BRK_MASK 0x80 /* Use interrupt bit for VIF insns */
+/* Macros for determining whether a MIPS IV or MIPS V part is subject
+ to the hi/lo restrictions described in mips.igen. */
-#endif /* !TM_TXVU_H */
-#endif /* TARGET_SKY */
-/* end-sanitize-sky */
+#define MIPS_MACH_HAS_MT_HILO_HAZARD(SD) \
+ (MIPS_MACH (SD) != bfd_mach_mips5500)
-void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
-void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
-void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
+#define MIPS_MACH_HAS_MULT_HILO_HAZARD(SD) \
+ (MIPS_MACH (SD) != bfd_mach_mips5500)
+#define MIPS_MACH_HAS_DIV_HILO_HAZARD(SD) \
+ (MIPS_MACH (SD) != bfd_mach_mips5500)
#if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
#include "sim-main.c"