X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fmn10300%2Fam33.igen;h=5bc96aca6164efb19c08a24cc3870d144350a959;hb=17fc27167f678285d2f64040837b8cc41b6a664a;hp=1123d8c75f0a4816ce2c7dd02b7af0994350ef94;hpb=6ae1456eb5882ebf0c88e39641e6b6a8639ab6f6;p=deliverable%2Fbinutils-gdb.git

diff --git a/sim/mn10300/am33.igen b/sim/mn10300/am33.igen
index 1123d8c75f..5bc96aca61 100644
--- a/sim/mn10300/am33.igen
+++ b/sim/mn10300/am33.igen
@@ -19,10 +19,30 @@
     return REG_E0 + rreg;
 }
 
+:function:::int:translate_xreg:int xreg
+{
+  switch (xreg)
+    {
+    case 0:
+      return REG_SP;
+    case 1:
+      return REG_MDRQ;
+    case 2:
+      return REG_MCRH;
+    case 3:
+      return REG_MCRL;
+    case 4:
+      return REG_MCVF;
+    default:
+      sim_engine_abort (SD, CPU, cia, "%s:%d: bad switch\n", __FILE__, __LINE__);
+    }
+}
+
 // 1111 0000 0010 00An; mov USP,An
 8.0xf0+4.0x2,00,2.AN0:D0m:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   State.regs[REG_A0 + AN0] = State.regs[REG_USP];
@@ -33,6 +53,7 @@
 8.0xf0+4.0x2,01,2.AN0:D0n:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
@@ -43,6 +64,7 @@
 8.0xf0+4.0x2,10,2.AN0:D0o:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
@@ -53,6 +75,7 @@
 8.0xf0+4.0x2,11,2.AN0:D0p:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   State.regs[REG_A0 + AN0] = PC;
@@ -63,6 +86,7 @@
 8.0xf0+4.0x3,2.AM1,00:D0q:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   State.regs[REG_USP] = State.regs[REG_A0 + AM1];
@@ -72,6 +96,7 @@
 8.0xf0+4.0x3,2.AM1,01:D0r:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
@@ -81,6 +106,7 @@
 8.0xf0+4.0x3,2.AM1,10:D0s:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
@@ -91,8 +117,9 @@
 8.0xf0+4.0xe,IMM4:D0t:::syscall
 "syscall"
 *am33
+*am33_2
 {
-  unsigned int sp, next_pc;
+  unsigned32 sp, next_pc;
 
   PC = cia;
   sp = State.regs[REG_SP];
@@ -108,6 +135,7 @@
 8.0xf2+4.0xe,11,2.DN0:D0u:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   State.regs[REG_D0 + DN0] = PSW;
@@ -118,6 +146,7 @@
 8.0xf2+4.0xf,2.DM1,01:D0v:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   PSW = State.regs[REG_D0 + DM1];
@@ -127,6 +156,7 @@
 8.0xf5+00,2.AM1,4.RN0:D0w:::mov
 "mov"
 *am33
+*am33_2
 {
   int destreg = translate_rreg (SD_, RN0);
 
@@ -138,6 +168,7 @@
 8.0xf5+01,2.DM1,4.RN0:D0x:::mov
 "mov"
 *am33
+*am33_2
 {
   int destreg = translate_rreg (SD_, RN0);
 
@@ -149,6 +180,7 @@
 8.0xf5+10,4.RM1,2.AN0:D0y:::mov
 "mov"
 *am33
+*am33_2
 {
   int destreg = translate_rreg (SD_, RM1);
 
@@ -160,6 +192,7 @@
 8.0xf5+11,4.RM1,2.DN0:D0z:::mov
 "mov"
 *am33
+*am33_2
 {
   int destreg = translate_rreg (SD_, RM1);
 
@@ -172,9 +205,10 @@
 8.0xf8+8.0xce+8.REGS:D1a:::movm
 "movm"
 *am33
+*am33_2
 {
-  unsigned long usp = State.regs[REG_USP];
-  unsigned long mask;
+  unsigned32 usp = State.regs[REG_USP];
+  unsigned32 mask;
 
   PC = cia;
   mask = REGS;
@@ -222,8 +256,9 @@
       usp += 4;
     }
 
-  /* start-sanitize-am33 */
-  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
+  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+      || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
+      )
     {
       if (mask & 0x1)
 	{
@@ -255,7 +290,6 @@
 	  usp += 4;
 	}
     }
-  /* end-sanitize-am33 */
 
   /* And make sure to update the stack pointer.  */
   State.regs[REG_USP] = usp;
@@ -265,11 +299,17 @@
 8.0xf8+8.0xcf+8.REGS:D1b:::movm
 "movm"
 *am33
+*am33_2
 {
-  unsigned long usp = State.regs[REG_USP];
-  unsigned long mask;
+  unsigned32 usp = State.regs[REG_USP];
+  unsigned32 mask;
+
+  PC = cia;
+  mask = REGS;
 
-  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
+  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+      || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
+      )
     {
       if (mask & 0x4)
 	{
@@ -301,7 +341,6 @@
 	  /* Need to save MDQR, MCRH, MCRL, and MCVF */
 	}
     }
-  /* end-sanitize-am33 */
 
   if (mask & 0x80)
     {
@@ -354,6 +393,7 @@
 8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
 "and"
 *am33
+*am33_2
 {
   PC = cia;
   PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
@@ -363,6 +403,7 @@
 8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
 "or"
 *am33
+*am33_2
 {
   PC = cia;
   PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
@@ -372,6 +413,7 @@
 8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -386,6 +428,7 @@
 8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
 "mov"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -401,6 +444,7 @@
 8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
 "extb"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -414,6 +458,7 @@
 8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
 "extbu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -427,6 +472,7 @@
 8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
 "exth"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -440,6 +486,7 @@
 8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
 "exthu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -453,6 +500,7 @@
 8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
 "clr"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -467,6 +515,7 @@
 8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
 "add"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -480,10 +529,11 @@
 8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
 "addc"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int z, c, n, v;
-  unsigned long reg1, reg2, sum;
+  unsigned32 reg1, reg2, sum;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
@@ -509,6 +559,7 @@
 8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
 "sub"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -522,10 +573,11 @@
 8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
 "subc"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int z, c, n, v;
-  unsigned long reg1, reg2, difference;
+  unsigned32 reg1, reg2, difference;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
@@ -551,6 +603,7 @@
 8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
 "inc"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -563,18 +616,20 @@
 8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
 "inc4"
 *am33
+*am33_2
 {
   int dstreg;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
-  State.regs[dstreg] += 4;
+  genericAdd (4, dstreg);
 }
 
 // 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
 8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
 "cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
 
@@ -588,42 +643,37 @@
 8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
 "mov"
 *am33
+*am33_2
 {
-  int dstreg;
+  int dstreg, srcreg;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
+  srcreg = translate_xreg (SD_, XRM2);
 
-  if (XRM2 == 0)
-    {
-      State.regs[dstreg] = State.regs[REG_SP];
-    }
-  else
-    abort ();
+  State.regs[dstreg] = State.regs[srcreg];
 }
 
 // 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
 8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
 "mov"
 *am33
+*am33_2
 {
-  int srcreg;
+  int srcreg, dstreg;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
+  dstreg = translate_xreg (SD_, XRN0);
 
-  if (XRN0 == 0)
-    {
-      State.regs[REG_SP] = State.regs[srcreg];
-    }
-  else
-    abort ();
+  State.regs[dstreg] = State.regs[srcreg];
 }
 
 // 1111 1001 0000 1001 Rm Rn; and Rm,Rn
 8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
 "and"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int z, n;
@@ -644,6 +694,7 @@
 8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
 "or"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int z, n;
@@ -663,6 +714,7 @@
 8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
 "xor"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int z, n;
@@ -682,6 +734,7 @@
 8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
 "not"
 *am33
+*am33_2
 {
   int dstreg;
   int z, n;
@@ -700,9 +753,10 @@
 8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
 "asr"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
-  long temp;
+  signed32 temp;
   int c, z, n;
 
   PC = cia;
@@ -723,6 +777,7 @@
 8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
 "lsr"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int z, n, c;
@@ -744,6 +799,7 @@
 8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
 "asl"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int z, n;
@@ -763,6 +819,7 @@
 8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
 "asl2"
 *am33
+*am33_2
 {
   int dstreg;
   int n, z;
@@ -781,10 +838,11 @@
 8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
 "ror"
 *am33
+*am33_2
 {
   int dstreg;
   int c, n, z;
-  unsigned long value;
+  unsigned32 value;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
@@ -805,10 +863,11 @@
 8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
 "rol"
 *am33
+*am33_2
 {
   int dstreg;
   int c, n, z;
-  unsigned long value;
+  unsigned32 value;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
@@ -829,9 +888,10 @@
 8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
 "mul"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
-  unsigned long long temp;
+  unsigned64 temp;
   int n, z;
 
   PC = cia;
@@ -841,7 +901,7 @@
   temp = ((signed64)(signed32)State.regs[dstreg]
           *  (signed64)(signed32)State.regs[srcreg]);
   State.regs[dstreg] = temp & 0xffffffff;
-  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
+  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[dstreg] == 0);
   n = (State.regs[dstreg] & 0x80000000) != 0;
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -852,9 +912,10 @@
 8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
 "mulu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
-  unsigned long long temp;
+  unsigned64 temp;
   int n, z;
 
   PC = cia;
@@ -875,9 +936,10 @@
 8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
 "div"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
-  long long temp;
+  signed64 temp;
   int n, z;
 
   PC = cia;
@@ -900,9 +962,10 @@
 8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
 "divu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
-  unsigned long long temp;
+  unsigned64 temp;
   int n, z;
 
   PC = cia;
@@ -926,6 +989,7 @@
 8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -939,6 +1003,7 @@
 8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -952,6 +1017,7 @@
 8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -965,6 +1031,7 @@
 8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -978,6 +1045,7 @@
 8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -991,6 +1059,7 @@
 8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1001,9 +1070,10 @@
 }
 
 // 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
-8.0xf9+8.0x6a+4.RN2,4.RM0:D1y:::mov
+8.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1018,6 +1088,7 @@
 8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1032,6 +1103,7 @@
 8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -1044,6 +1116,7 @@
 8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -1056,6 +1129,7 @@
 8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -1068,6 +1142,7 @@
 8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -1080,6 +1155,7 @@
 8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -1092,6 +1168,7 @@
 8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -1101,9 +1178,10 @@
 }
 
 // 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
-8.0xf9+8.0xea+4.RN2,4.RM0:D1y:::movhu
+8.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1118,6 +1196,7 @@
 8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1133,9 +1212,10 @@
 8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
 "mac"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -1161,9 +1241,10 @@
 8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
 "macu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
-  unsigned long long temp, sum;
+  unsigned64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -1189,9 +1270,10 @@
 8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
 "macb"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
-  long temp, sum;
+  signed32 temp, sum;
   int v;
 
   PC = cia;
@@ -1212,9 +1294,10 @@
 8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
 "macbu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
-  long long temp, sum;
+  signed64 temp, sum;
   int v;
 
   PC = cia;
@@ -1235,9 +1318,10 @@
 8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
 "mach"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -1263,9 +1347,10 @@
 8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
 "machu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -1291,9 +1376,10 @@
 8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
 "dmach"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
   int v;
 
   PC = cia;
@@ -1316,9 +1402,10 @@
 8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
 "dmachu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
-  unsigned long temp, temp2, sum;
+  unsigned32 temp, temp2, sum;
   int v;
 
   PC = cia;
@@ -1341,9 +1428,10 @@
 8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
 "dmulh"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
-  long temp;
+  signed32 temp;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
@@ -1361,9 +1449,10 @@
 8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
 "dmachu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
-  unsigned long temp;
+  unsigned32 temp;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
@@ -1381,6 +1470,7 @@
 8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
 "sat16"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int value, z, n;
@@ -1408,6 +1498,7 @@
 8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
 "mcste"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1421,7 +1512,7 @@
   /* 32bit saturation.  */
   if (State.regs[srcreg] == 0x20)
     {
-      long long tmp;
+      signed64 tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -1437,7 +1528,7 @@
   /* 16bit saturation */
   else if (State.regs[srcreg] == 0x10)
     {
-      long long tmp;
+      signed64 tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -1453,7 +1544,7 @@
   /* 8 bit saturation */
   else if (State.regs[srcreg] == 0x8)
     {
-      long long tmp;
+      signed64 tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -1469,7 +1560,7 @@
   /* 9 bit saturation */
   else if (State.regs[srcreg] == 0x9)
     {
-      long long tmp;
+      signed64 tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -1485,7 +1576,7 @@
   /* 9 bit saturation */
   else if (State.regs[srcreg] == 0x30)
     {
-      long long tmp;
+      signed64 tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -1505,6 +1596,7 @@
 8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
 "swap"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1522,6 +1614,7 @@
 8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
 "swaph"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1539,6 +1632,7 @@
 8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
 "swhw"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1554,6 +1648,7 @@
 8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
 "bsch"
 *am33
+*am33_2
 {
   int temp, c, i;
   int srcreg, dstreg;
@@ -1568,6 +1663,7 @@
   if (start == -1)
     start = 31;
     
+  c = 0;
   for (i = start; i >= 0; i--)
     {
       if (temp & (1 << i))
@@ -1592,6 +1688,7 @@
 8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -1604,6 +1701,7 @@
 8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
 "movu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -1616,6 +1714,7 @@
 8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
 "add"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -1628,10 +1727,11 @@
 8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
 "addc"
 *am33
+*am33_2
 {
   int dstreg, imm;
   int z, c, n, v;
-  unsigned long reg1, reg2, sum;
+  unsigned32 reg2, sum;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
@@ -1656,6 +1756,7 @@
 8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
 "sub"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -1669,10 +1770,11 @@
 8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
 "subc"
 *am33
+*am33_2
 {
   int imm, dstreg;
   int z, c, n, v;
-  unsigned long reg1, reg2, difference;
+  unsigned32 reg2, difference;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
@@ -1697,6 +1799,7 @@
 8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
 "cmp"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -1709,21 +1812,21 @@
 8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
   PC = cia;
+  dstreg = translate_xreg (SD_, XRN0);
 
-  if (XRN0 == 0)
-    State.regs[REG_SP] = IMM8;
-  else
-    abort ();
+  State.regs[dstreg] = IMM8;
 }
 
 // 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
 8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
 "and"
 *am33
+*am33_2
 {
   int dstreg;
   int z, n;
@@ -1742,6 +1845,7 @@
 8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
 "or"
 *am33
+*am33_2
 {
   int dstreg;
   int z, n;
@@ -1760,6 +1864,7 @@
 8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
 "xor"
 *am33
+*am33_2
 {
   int dstreg;
   int z, n;
@@ -1778,9 +1883,10 @@
 8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
 "asr"
 *am33
+*am33_2
 {
   int dstreg;
-  long temp;
+  signed32 temp;
   int c, z, n;
 
   PC = cia;
@@ -1800,6 +1906,7 @@
 8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
 "lsr"
 *am33
+*am33_2
 {
   int dstreg;
   int z, n, c;
@@ -1819,8 +1926,9 @@
 8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
 "asl"
 *am33
+*am33_2
 {
-  int srcreg, dstreg;
+  int dstreg;
   int z, n;
 
   PC = cia;
@@ -1837,9 +1945,10 @@
 8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
 "mul"
 *am33
+*am33_2
 {
   int dstreg;
-  unsigned long long temp;
+  unsigned64 temp;
   int z, n;
 
   PC = cia;
@@ -1848,7 +1957,7 @@
   temp = ((signed64)(signed32)State.regs[dstreg]
           *  (signed64)(signed32)EXTEND8 (IMM8));
   State.regs[dstreg] = temp & 0xffffffff;
-  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
+  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[dstreg] == 0);
   n = (State.regs[dstreg] & 0x80000000) != 0;
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -1859,9 +1968,10 @@
 8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
 "mulu"
 *am33
+*am33_2
 {
   int dstreg;
-  unsigned long long temp;
+  unsigned64 temp;
   int z, n;
 
   PC = cia;
@@ -1881,6 +1991,7 @@
 8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
 "btst"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -1893,6 +2004,7 @@
 8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1905,6 +2017,8 @@
 // 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
 8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
 "mov"
+*am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1917,6 +2031,8 @@
 // 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
 8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
 "movbu"
+*am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1929,6 +2045,8 @@
 // 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
 8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
 "movbu"
+*am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1941,6 +2059,8 @@
 // 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
 8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
 "movhu"
+*am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1953,6 +2073,8 @@
 // 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
 8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
 "movhu"
+*am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1963,9 +2085,10 @@
 }
 
 // 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
-8.0xfb+8.0x6a+4.RN2,4.RM0+8.IMM8:D2y:::mov
+8.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1979,6 +2102,8 @@
 // 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
 8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
 "mov"
+*am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1993,73 +2118,86 @@
 // 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
 8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
 "mov"
+*am33
+*am33_2
 {
   int dstreg;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN2);
-  State.regs[dstreg] = load_word (State.regs[REG_SP] + EXTEND8 (IMM8));
+  State.regs[dstreg] = load_word (State.regs[REG_SP] + IMM8);
 }
 
-// 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,Rn)
+// 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,sp)
 8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
 "mov"
+*am33
+*am33_2
 {
   int srcreg;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
-  store_word (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
+  store_word (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
 }
 
 // 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
 8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
 "movbu"
+*am33
+*am33_2
 {
   int dstreg;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN2);
-  State.regs[dstreg] = load_byte (State.regs[REG_SP] + EXTEND8 (IMM8));
+  State.regs[dstreg] = load_byte (State.regs[REG_SP] + IMM8);
 }
 
-// 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(sp,Rn)
+// 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(d8,sp)
 8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
 "movbu"
+*am33
+*am33_2
 {
   int srcreg;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
-  store_byte (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
+  store_byte (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
 }
 
 // 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
 8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
 "movhu"
+*am33
+*am33_2
 {
   int dstreg;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN2);
-  State.regs[dstreg] = load_half (State.regs[REG_SP] + EXTEND8 (IMM8));
+  State.regs[dstreg] = load_half (State.regs[REG_SP] + IMM8);
 }
 
 // 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
 8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
 "movhu"
+*am33
+*am33_2
 {
   int srcreg;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
-  store_half (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
+  store_half (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
 }
 
 // 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
-8.0xfb+8.0xea+4.RN2,4.RM0+8.IMM8:D2y:::movhu
+8.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -2073,6 +2211,8 @@
 // 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
 8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
 "movhu"
+*am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -2087,9 +2227,11 @@
 // 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn
 8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
 "mac"
+*am33
+*am33_2
 {
   int srcreg;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -2113,9 +2255,11 @@
 // 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn
 8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
 "macu"
+*am33
+*am33_2
 {
   int srcreg;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -2139,9 +2283,11 @@
 // 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn
 8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
 "macb"
+*am33
+*am33_2
 {
   int srcreg;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -2165,9 +2311,11 @@
 // 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn
 8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
 "macbu"
+*am33
+*am33_2
 {
   int srcreg;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -2191,9 +2339,11 @@
 // 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn
 8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
 "mach"
+*am33
+*am33_2
 {
   int srcreg;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -2217,9 +2367,11 @@
 // 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn
 8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
 "machu"
+*am33
+*am33_2
 {
   int srcreg;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -2243,6 +2395,8 @@
 // 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn
 8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
 "mcste"
+*am33
+*am33_2
 {
   int dstreg;
 
@@ -2255,7 +2409,7 @@
   /* 32bit saturation.  */
   if (IMM8 == 0x20)
     {
-      long long tmp;
+      signed64 tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -2271,7 +2425,7 @@
   /* 16bit saturation */
   else if (IMM8 == 0x10)
     {
-      long long tmp;
+      signed64 tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -2287,7 +2441,7 @@
   /* 8 bit saturation */
   else if (IMM8 == 0x8)
     {
-      long long tmp;
+      signed64 tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -2303,7 +2457,7 @@
   /* 9 bit saturation */
   else if (IMM8 == 0x9)
     {
-      long long tmp;
+      signed64 tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -2319,7 +2473,7 @@
   /* 9 bit saturation */
   else if (IMM8 == 0x30)
     {
-      long long tmp;
+      signed64 tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -2339,9 +2493,10 @@
 8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
 "add"
 *am33
+*am33_2
 {
   int z, c, n, v;
-  unsigned long sum, source1, source2;
+  unsigned32 sum, source1, source2;
   int srcreg1, srcreg2, dstreg;
 
   PC = cia;
@@ -2369,9 +2524,10 @@
 8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
 "addc"
 *am33
+*am33_2
 {
   int z, c, n, v;
-  unsigned long sum, source1, source2;
+  unsigned32 sum, source1, source2;
   int srcreg1, srcreg2, dstreg;
 
   PC = cia;
@@ -2399,9 +2555,10 @@
 8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
 "sub"
 *am33
+*am33_2
 {
   int z, c, n, v;
-  unsigned long difference, source1, source2;
+  unsigned32 difference, source1, source2;
   int srcreg1, srcreg2, dstreg;
 
   PC = cia;
@@ -2416,7 +2573,7 @@
 
   z = (difference == 0);
   n = (difference & 0x80000000);
-  c = (source1 > source1);
+  c = (source1 > source2);
   v = ((source1 & 0x80000000) == (source2 & 0x80000000)
        && (source1 & 0x80000000) != (difference & 0x80000000));
 
@@ -2429,9 +2586,10 @@
 8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
 "subc"
 *am33
+*am33_2
 {
   int z, c, n, v;
-  unsigned long difference, source1, source2;
+  unsigned32 difference, source1, source2;
   int srcreg1, srcreg2, dstreg;
 
   PC = cia;
@@ -2459,6 +2617,7 @@
 8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
 "and"
 *am33
+*am33_2
 {
   int z, n;
   int srcreg1, srcreg2, dstreg;
@@ -2481,6 +2640,7 @@
 8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
 "or"
 *am33
+*am33_2
 {
   int z, n;
   int srcreg1, srcreg2, dstreg;
@@ -2503,6 +2663,7 @@
 8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
 "xor"
 *am33
+*am33_2
 {
   int z, n;
   int srcreg1, srcreg2, dstreg;
@@ -2525,9 +2686,10 @@
 8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
 "asr"
 *am33
+*am33_2
 {
   int z, c, n;
-  long temp;
+  signed32 temp;
   int srcreg1, srcreg2, dstreg;
 
   PC = cia;
@@ -2551,6 +2713,7 @@
 8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
 "lsr"
 *am33
+*am33_2
 {
   int z, c, n;
   int srcreg1, srcreg2, dstreg;
@@ -2574,6 +2737,7 @@
 8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
 "asl"
 *am33
+*am33_2
 {
   int z, n;
   int srcreg1, srcreg2, dstreg;
@@ -2583,7 +2747,7 @@
   srcreg2 = translate_rreg (SD_, RN0);
   dstreg = translate_rreg (SD_, RD0);
 
-  State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];;
+  State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];
 
   z = (State.regs[dstreg] == 0);
   n = (State.regs[dstreg] & 0x80000000);
@@ -2593,12 +2757,13 @@
 }
 
 // 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
-8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mul
+8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul
 "mul"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed long long temp;
+  signed64 temp;
   int n, z;
 
   PC = cia;
@@ -2609,23 +2774,24 @@
 
   temp = ((signed64)(signed32)State.regs[srcreg1]
           *  (signed64)(signed32)State.regs[srcreg2]);
-  State.regs[dstreg1] = temp & 0xffffffff;
-  State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
+  State.regs[dstreg2] = temp & 0xffffffff;
+  State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
 
   z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
-  n = (State.regs[dstreg2] & 0x80000000);
+  n = (State.regs[dstreg1] & 0x80000000);
 
   PSW &= ~(PSW_Z | PSW_N);
   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
 }
 
 // 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
-8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mulu
+8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu
 "mulu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed long long temp;
+  signed64 temp;
   int n, z;
 
   PC = cia;
@@ -2636,11 +2802,11 @@
 
   temp = ((unsigned64)State.regs[srcreg1]
           *  (unsigned64)State.regs[srcreg2]);
-  State.regs[dstreg1] = temp & 0xffffffff;
-  State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
+  State.regs[dstreg2] = temp & 0xffffffff;
+  State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
 
   z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
-  n = (State.regs[dstreg2] & 0x80000000);
+  n = (State.regs[dstreg1] & 0x80000000);
 
   PSW &= ~(PSW_Z | PSW_N);
   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
@@ -2650,6 +2816,7 @@
 8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -2662,6 +2829,7 @@
 8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -2674,6 +2842,7 @@
 8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -2686,6 +2855,7 @@
 8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -2698,6 +2868,7 @@
 8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -2710,6 +2881,7 @@
 8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -2722,12 +2894,13 @@
 8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM0);
-  srcreg1 = translate_rreg (SD_, RI0);
+  srcreg2 = translate_rreg (SD_, RI0);
   dstreg = translate_rreg (SD_, RN0);
   State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
 }
@@ -2736,6 +2909,7 @@
 8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg1, dstreg2;
 
@@ -2750,12 +2924,13 @@
 8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM0);
-  srcreg1 = translate_rreg (SD_, RI0);
+  srcreg2 = translate_rreg (SD_, RI0);
   dstreg = translate_rreg (SD_, RN0);
   State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
 }
@@ -2764,6 +2939,7 @@
 8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg, dstreg1, dstreg2;
 
@@ -2778,12 +2954,13 @@
 8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM0);
-  srcreg1 = translate_rreg (SD_, RI0);
+  srcreg2 = translate_rreg (SD_, RI0);
   dstreg = translate_rreg (SD_, RN0);
   State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
 }
@@ -2792,6 +2969,7 @@
 8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg1, dstreg2;
 
@@ -2803,13 +2981,14 @@
 }
 
 // 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2
-8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mac
+8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac
 "mac"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed long long temp;
-  unsigned long sum;
+  signed64 temp;
+  unsigned32 sum;
   int c, v;
 
   PC = cia;
@@ -2839,13 +3018,14 @@
 }
 
 // 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2
-8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::macu
+8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu
 "macu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed long long temp;
-  unsigned long sum;
+  signed64 temp;
+  unsigned32 sum;
   int c, v;
 
   PC = cia;
@@ -2878,9 +3058,10 @@
 8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
 "macb"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg;
-  long temp, sum;
+  signed32 temp, sum;
   int v;
 
   PC = cia;
@@ -2906,9 +3087,10 @@
 8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
 "macbu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg;
-  long temp, sum;
+  signed32 temp, sum;
   int v;
 
   PC = cia;
@@ -2930,26 +3112,29 @@
     }
 }
 
-// 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1
-8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::mach
+// 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1,Rd2
+8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach
 "mach"
 *am33
+*am33_2
 {
-  int srcreg1, srcreg2, dstreg;
-  long temp, sum;
+  int srcreg1, srcreg2, dstreg1, dstreg2;
+  signed64 temp, sum;
   int v;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM2);
   srcreg2 = translate_rreg (SD_, RN0);
-  dstreg = translate_rreg (SD_, RD0);
+  dstreg1 = translate_rreg (SD_, RD0);
+  dstreg2 = translate_rreg (SD_, RD0);
 
   temp = ((signed32)(State.regs[srcreg2] & 0xffff)
           * (signed32)(State.regs[srcreg1] & 0xffff));
-  sum = State.regs[dstreg] + temp;
-  v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
+  State.regs[dstreg2] += (temp & 0xffffffff);
+  sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
+  v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
         && (temp & 0x80000000) != (sum & 0x80000000));
-  State.regs[dstreg] = sum;
+  State.regs[dstreg1] = sum;
   if (v)
     {
       State.regs[REG_MCVF] = 1;
@@ -2958,26 +3143,29 @@
     }
 }
 
-// 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1
-8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::machu
+// 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1,Rd2
+8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu
 "machu"
 *am33
+*am33_2
 {
-  int srcreg1, srcreg2, dstreg;
-  long temp, sum;
+  int srcreg1, srcreg2, dstreg1, dstreg2;
+  signed64 temp, sum;
   int v;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM2);
   srcreg2 = translate_rreg (SD_, RN0);
-  dstreg = translate_rreg (SD_, RD0);
+  dstreg1 = translate_rreg (SD_, RD0);
+  dstreg2 = translate_rreg (SD_, RD0);
 
   temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
           * (unsigned32)(State.regs[srcreg1] & 0xffff));
-  sum = State.regs[dstreg] + temp;
-  v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
+  State.regs[dstreg2] += (temp & 0xffffffff);
+  sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
+  v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
         && (temp & 0x80000000) != (sum & 0x80000000));
-  State.regs[dstreg] = sum;
+  State.regs[dstreg1] = sum;
   if (v)
     {
       State.regs[REG_MCVF] = 1;
@@ -2990,9 +3178,10 @@
 8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
 "dmach"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
   int v;
 
   PC = cia;
@@ -3020,9 +3209,10 @@
 8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
 "dmachu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
   int v;
 
   PC = cia;
@@ -3047,12 +3237,13 @@
 }
 
 // 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2
-8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::dmulh
+8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh
 "dmulh"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed long long temp;
+  signed64 temp;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM2);
@@ -3069,12 +3260,13 @@
 }
 
 // 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2
-8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::dmulhu
+8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu
 "dmulhu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed long long temp;
+  signed64 temp;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM2);
@@ -3094,6 +3286,7 @@
 8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
 "sat24"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int value, n, z;
@@ -3121,6 +3314,7 @@
 8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
 "bsch"
 *am33
+*am33_2
 {
   int temp, c, i;
   int srcreg1, srcreg2, dstreg;
@@ -3135,7 +3329,8 @@
   start = (State.regs[srcreg2] & 0x1f) - 1;
   if (start == -1)
     start = 31;
-    
+
+  c = 0;    
   for (i = start; i >= 0; i--)
     {
       if (temp & (1 << i))
@@ -3159,6 +3354,7 @@
 8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3171,6 +3367,7 @@
 8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
 "movu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3183,6 +3380,7 @@
 8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
 "add"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3195,9 +3393,10 @@
 8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
 "addc"
 *am33
+*am33_2
 {
   int dstreg, z, n, c, v;
-  unsigned long sum, imm, reg2;
+  unsigned32 sum, imm, reg2;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
@@ -3222,6 +3421,7 @@
 8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
 "sub"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3234,9 +3434,10 @@
 8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
 "subc"
 *am33
+*am33_2
 {
   int dstreg, z, n, c, v;
-  unsigned long difference, imm, reg2;
+  unsigned32 difference, imm, reg2;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
@@ -3261,6 +3462,7 @@
 8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
 "cmp"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -3273,21 +3475,21 @@
 8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
 "mov"
 *am33
+*am33_2
 {
+  int dstreg;
+
   PC = cia;
+  dstreg = translate_xreg (SD_, XRN0);
 
-  if (XRN0 == 0)
-    {
-      State.regs[REG_SP] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
-    }
-  else
-    abort ();
+  State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
 }
 
 // 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
 8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
 "and"
 *am33
+*am33_2
 {
   int dstreg;
   int z,n;
@@ -3306,6 +3508,7 @@
 8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
 "or"
 *am33
+*am33_2
 {
   int dstreg;
   int z,n;
@@ -3324,6 +3527,7 @@
 8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
 "xor"
 *am33
+*am33_2
 {
   int dstreg;
   int z,n;
@@ -3342,9 +3546,10 @@
 8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
 "asr"
 *am33
+*am33_2
 {
   int dstreg;
-  long temp;
+  signed32 temp;
   int c, z, n;
 
   PC = cia;
@@ -3365,6 +3570,7 @@
 8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
 "lsr"
 *am33
+*am33_2
 {
   int dstreg;
   int z, n, c;
@@ -3384,8 +3590,9 @@
 8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
 "asl"
 *am33
+*am33_2
 {
-  int srcreg, dstreg;
+  int dstreg;
   int z, n;
 
   PC = cia;
@@ -3402,9 +3609,10 @@
 8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
 "mul"
 *am33
+*am33_2
 {
   int dstreg;
-  unsigned long long temp;
+  unsigned64 temp;
   int z, n;
 
   PC = cia;
@@ -3413,7 +3621,7 @@
   temp = ((signed64)(signed32)State.regs[dstreg]
           *  (signed64)(signed32)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
   State.regs[dstreg] = temp & 0xffffffff;
-  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
+  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[dstreg] == 0);
   n = (State.regs[dstreg] & 0x80000000) != 0;
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -3424,9 +3632,10 @@
 8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
 "mulu"
 *am33
+*am33_2
 {
   int dstreg;
-  unsigned long long temp;
+  unsigned64 temp;
   int z, n;
 
   PC = cia;
@@ -3435,7 +3644,7 @@
   temp = ((unsigned64)State.regs[dstreg]
           *  (unsigned64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
   State.regs[dstreg] = temp & 0xffffffff;
-  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
+  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[dstreg] == 0);
   n = (State.regs[dstreg] & 0x80000000) != 0;
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -3446,6 +3655,7 @@
 8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
 "btst"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -3458,6 +3668,7 @@
 8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3473,6 +3684,7 @@
 8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3487,6 +3699,7 @@
 8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3502,6 +3715,7 @@
 8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3516,6 +3730,7 @@
 8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3531,6 +3746,7 @@
 8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3542,9 +3758,10 @@
 }
 
 // 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn
-8.0xfd+8.0x6a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
+8.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3559,6 +3776,7 @@
 8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3574,53 +3792,55 @@
 8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN2);
   State.regs[dstreg] = load_word (State.regs[REG_SP]
-				  + EXTEND24 (FETCH24 (IMM24A,
-						       IMM24B, IMM24C)));
+				  + FETCH24 (IMM24A, IMM24B, IMM24C));
 }
 
 // 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
 8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
-  store_word (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
+  store_word (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
 	      State.regs[srcreg]);
 }
 
-// 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,Rm),Rn
+// 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,sp),Rn
 8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int dstreg;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN2);
   State.regs[dstreg] = load_byte (State.regs[REG_SP]
-				  + EXTEND24 (FETCH24 (IMM24A,
-						       IMM24B, IMM24C)));
+				  + FETCH24 (IMM24A, IMM24B, IMM24C));
 }
 
 // 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
 8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
-  store_byte (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
+  store_byte (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
 	      State.regs[srcreg]);
 }
 
@@ -3628,33 +3848,35 @@
 8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int dstreg;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN2);
   State.regs[dstreg] = load_half (State.regs[REG_SP]
-				  + EXTEND24 (FETCH24 (IMM24A,
-						       IMM24B, IMM24C)));
+				  + FETCH24 (IMM24A, IMM24B, IMM24C));
 }
 
 // 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
 8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
-  store_half (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
+  store_half (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
 	      State.regs[srcreg]);
 }
 
 // 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn
-8.0xfd+8.0xea+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
+8.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3669,6 +3891,7 @@
 8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3683,9 +3906,10 @@
 8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
 "mac"
 *am33
+*am33_2
 {
   int srcreg;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -3710,9 +3934,10 @@
 8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
 "macu"
 *am33
+*am33_2
 {
   int srcreg;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -3737,9 +3962,10 @@
 8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
 "macb"
 *am33
+*am33_2
 {
   int srcreg;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -3764,9 +3990,10 @@
 8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
 "macbu"
 *am33
+*am33_2
 {
   int srcreg;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -3791,9 +4018,10 @@
 8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
 "mach"
 *am33
+*am33_2
 {
   int srcreg;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -3818,9 +4046,10 @@
 8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
 "machu"
 *am33
+*am33_2
 {
   int srcreg;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -3845,6 +4074,7 @@
 8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3857,6 +4087,7 @@
 8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -3870,6 +4101,7 @@
 8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3882,6 +4114,7 @@
 8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -3895,6 +4128,7 @@
 8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3907,6 +4141,7 @@
 8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -3920,6 +4155,7 @@
 8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3932,6 +4168,7 @@
 8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
 "movu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3944,6 +4181,7 @@
 8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
 "add"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3956,9 +4194,10 @@
 8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
 "addc"
 *am33
+*am33_2
 {
   int dstreg;
-  unsigned int imm, reg2, sum;
+  unsigned32 imm, reg2, sum;
   int z, n, c, v;
 
   PC = cia;
@@ -3984,6 +4223,7 @@
 8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
 "sub"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3996,9 +4236,10 @@
 8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
 "subc"
 *am33
+*am33_2
 {
   int dstreg;
-  unsigned int imm, reg2, difference;
+  unsigned32 imm, reg2, difference;
   int z, n, c, v;
 
   PC = cia;
@@ -4024,6 +4265,7 @@
 8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
 "cmp"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -4036,19 +4278,21 @@
 8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
 "mov"
 *am33
+*am33_2
 {
+  int dstreg;
+
   PC = cia;
+  dstreg = translate_xreg (SD_, XRN0);
 
-  if (XRN0 == 0)
-    State.regs[REG_SP] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
-  else
-    abort ();
+  State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
 }
 
 // 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
 8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
 "and"
 *am33
+*am33_2
 {
   int dstreg;
   int z,n;
@@ -4067,6 +4311,7 @@
 8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
 "or"
 *am33
+*am33_2
 {
   int dstreg;
   int z,n;
@@ -4085,6 +4330,7 @@
 8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
 "xor"
 *am33
+*am33_2
 {
   int dstreg;
   int z,n;
@@ -4103,9 +4349,10 @@
 8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
 "asr"
 *am33
+*am33_2
 {
   int dstreg;
-  long temp;
+  signed32 temp;
   int c, z, n;
 
   PC = cia;
@@ -4125,6 +4372,7 @@
 8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
 "lsr"
 *am33
+*am33_2
 {
   int dstreg;
   int z, n, c;
@@ -4144,8 +4392,9 @@
 8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
 "asl"
 *am33
+*am33_2
 {
-  int srcreg, dstreg;
+  int dstreg;
   int z, n;
 
   PC = cia;
@@ -4162,9 +4411,10 @@
 8.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul
 "mul"
 *am33
+*am33_2
 {
   int dstreg;
-  unsigned long long temp;
+  unsigned64 temp;
   int z, n;
 
   PC = cia;
@@ -4173,7 +4423,7 @@
   temp = ((signed64)(signed32)State.regs[dstreg]
           *  (signed64)(signed32)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
   State.regs[dstreg] = temp & 0xffffffff;
-  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
+  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[dstreg] == 0);
   n = (State.regs[dstreg] & 0x80000000) != 0;
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -4184,9 +4434,10 @@
 8.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu
 "mulu"
 *am33
+*am33_2
 {
   int dstreg;
-  unsigned long long temp;
+  unsigned64 temp;
   int z, n;
 
   PC = cia;
@@ -4195,7 +4446,7 @@
   temp = ((unsigned64)State.regs[dstreg]
           *  (unsigned64) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
   State.regs[dstreg] = temp & 0xffffffff;
-  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
+  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[dstreg] == 0);
   n = (State.regs[dstreg] & 0x80000000) != 0;
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -4206,6 +4457,7 @@
 8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
 "btst"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -4218,6 +4470,7 @@
 8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4232,6 +4485,7 @@
 8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4246,6 +4500,7 @@
 8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4260,6 +4515,7 @@
 8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4274,6 +4530,7 @@
 8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4288,6 +4545,7 @@
 8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4299,9 +4557,10 @@
 }
 
 // 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn
-8.0xfe+8.0x6a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
+8.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4309,13 +4568,14 @@
   srcreg = translate_rreg (SD_, RM0);
   dstreg = translate_rreg (SD_, RN2);
   State.regs[dstreg] = load_word (State.regs[srcreg]);
-  State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+  State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 }
 
 // 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
 8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4331,6 +4591,7 @@
 8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -4344,6 +4605,7 @@
 8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -4357,6 +4619,7 @@
 8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -4370,6 +4633,7 @@
 8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -4383,6 +4647,7 @@
 8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -4396,6 +4661,7 @@
 8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -4407,9 +4673,10 @@
 
 
 // 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn
-8.0xfe+8.0xea+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
+8.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4424,6 +4691,7 @@
 8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4435,159 +4703,415 @@
 }
 
 
-// ??? mac
-// ??? macu
-// ??? macb
-// ??? macbu
-// ??? mach
-// ??? machu
-// ??? dmach
-// ??? dmachu
-// ??? dmulh
-// ??? dmulhu
-
-// 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
-8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
-"mov"
+// 1111 1110 0000 1011 Rn Rn IMM32; mac imm32,Rn
+8.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac
+"mac"
 *am33
+*am33_2
 {
-  int dstreg;
+  int srcreg, imm;
+  signed64 temp, sum;
+  int c, v;
 
   PC = cia;
-  dstreg = translate_rreg (SD_, RN2);
-  State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+  srcreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+  temp = ((signed64)(signed32)State.regs[srcreg]
+          * (signed64)(signed32)imm);
+  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+  State.regs[REG_MCRL] = sum;
+  temp >>= 32;
+  temp &= 0xffffffff;
+  sum = State.regs[REG_MCRH] + temp + c;
+  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+        && (temp & 0x80000000) != (sum & 0x80000000));
+  State.regs[REG_MCRH] = sum;
+  if (v)
+    State.regs[REG_MCVF] = 1;
 }
 
-// 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
-8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
-"mov"
+// 1111 1110 0001 1011 Rn Rn IMM32; macu imm32,Rn
+8.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu
+"macu"
 *am33
+*am33_2
 {
-  int srcreg;
+  int srcreg, imm;
+  signed64 temp, sum;
+  int c, v;
 
   PC = cia;
-  srcreg = translate_rreg (SD_, RM2);
-  store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
+  srcreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+  temp = ((unsigned64)State.regs[srcreg]
+          * (unsigned64)imm);
+  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+  State.regs[REG_MCRL] = sum;
+  temp >>= 32;
+  temp &= 0xffffffff;
+  sum = State.regs[REG_MCRH] + temp + c;
+  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+        && (temp & 0x80000000) != (sum & 0x80000000));
+  State.regs[REG_MCRH] = sum;
+  if (v)
+    State.regs[REG_MCVF] = 1;
 }
 
-// 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
-8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
-"movbu"
+// 1111 1110 0010 1011 Rn Rn IMM32; macb imm32,Rn
+8.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb
+"macb"
 *am33
+*am33_2
 {
-  int dstreg;
+  int srcreg, imm;
+  signed32 temp, sum;
+  int v;
 
   PC = cia;
-  dstreg = translate_rreg (SD_, RN2);
-  State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+  srcreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+  temp = ((signed32)(signed8)(State.regs[srcreg] & 0xff)
+          * (signed32)(signed8)(imm & 0xff));
+  sum = State.regs[REG_MCRL] + temp;
+  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+        && (temp & 0x80000000) != (sum & 0x80000000));
+  State.regs[REG_MCRL] = sum;
+  if (v)
+    State.regs[REG_MCVF] = 1;
 }
 
-// 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
-8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
-"movbu"
+// 1111 1110 0011 1011 Rn Rn IMM32; macbu imm32,Rn
+8.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu
+"macbu"
 *am33
+*am33_2
 {
-  int srcreg;
+  int srcreg, imm;
+  signed32 temp, sum;
+  int v;
 
   PC = cia;
-  srcreg = translate_rreg (SD_, RM2);
-  store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
+  srcreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+  temp = ((unsigned32)(State.regs[srcreg] & 0xff)
+          * (unsigned32)(imm & 0xff));
+  sum = State.regs[REG_MCRL] + temp;
+  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+        && (temp & 0x80000000) != (sum & 0x80000000));
+  State.regs[REG_MCRL] = sum;
+  if (v)
+    State.regs[REG_MCVF] = 1;
 }
 
-// 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
-8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
-"movhu"
+// 1111 1110 0100 1011 Rn Rn IMM32; mach imm32,Rn
+8.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach
+"mach"
 *am33
+*am33_2
 {
-  int dstreg;
+  int srcreg, imm;
+  signed32 temp, sum;
+  int v;
 
   PC = cia;
-  dstreg = translate_rreg (SD_, RN2);
-  State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+  srcreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+  temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
+          * (signed32)(signed16)(imm & 0xffff));
+  sum = State.regs[REG_MCRL] + temp;
+  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+        && (temp & 0x80000000) != (sum & 0x80000000));
+  State.regs[REG_MCRL] = sum;
+  if (v)
+    State.regs[REG_MCVF] = 1;
 }
 
-// 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
-8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
-"movhu"
+// 1111 1110 0101 1011 Rn Rn IMM32; machu imm32,Rn
+8.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu
+"machu"
 *am33
+*am33_2
 {
-  int srcreg;
+  int srcreg, imm;
+  signed32 temp, sum;
+  int v;
 
   PC = cia;
-  srcreg = translate_rreg (SD_, RM2);
-  store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
+  srcreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+  temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
+          * (unsigned32)(imm & 0xffff));
+  sum = State.regs[REG_MCRL] + temp;
+  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+        && (temp & 0x80000000) != (sum & 0x80000000));
+  State.regs[REG_MCRL] = sum;
+  if (v)
+    State.regs[REG_MCVF] = 1;
 }
 
-// 1111 0111 0000 0000 Rm1 Rn1 Rm2 Rn2; add_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_add
-"add_add"
+// 1111 1110 0110 1011 Rn Rn IMM32; dmach imm32,Rn
+8.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach
+"dmach"
 *am33
+*am33_2
 {
-  int srcreg1, srcreg2, dstreg1, dstreg2;
+  int srcreg, imm;
+  signed32 temp, temp2, sum;
+  int v;
 
   PC = cia;
-  srcreg1 = translate_rreg (SD_, RM1);
-  srcreg2 = translate_rreg (SD_, RM2);
-  dstreg1 = translate_rreg (SD_, RN1);
-  dstreg2 = translate_rreg (SD_, RN2);
+  srcreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
-  State.regs[dstreg2] += State.regs[srcreg2];
+  temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
+          * (signed32)(signed16)(imm & 0xffff));
+  temp2 = ((signed32)(signed16)((State.regs[srcreg] >> 16) & 0xffff)
+	   * (signed32)(signed16)((imm >> 16) & 0xffff));
+  sum = temp + temp2 + State.regs[REG_MCRL];
+  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+        && (temp & 0x80000000) != (sum & 0x80000000));
+  State.regs[REG_MCRL] = sum;
+  if (v)
+    State.regs[REG_MCVF] = 1;
 }
 
-// 1111 0111 0001 0000 Rm1 Rn1 imm4 Rn2; add_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_add
-"add_add"
+// 1111 1110 0111 1011 Rn Rn IMM32; dmachu imm32,Rn
+8.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu
+"dmachu"
 *am33
+*am33_2
 {
-  int srcreg1, dstreg1, dstreg2;
+  int srcreg, imm;
+  signed32 temp, temp2, sum;
+  int v;
 
   PC = cia;
-  srcreg1 = translate_rreg (SD_, RM1);
-  dstreg1 = translate_rreg (SD_, RN1);
-  dstreg2 = translate_rreg (SD_, RN2);
+  srcreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
-  State.regs[dstreg2] += EXTEND4 (IMM4);
+  temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
+          * (unsigned32)(imm & 0xffff));
+  temp2 = ((unsigned32)((State.regs[srcreg] >> 16) & 0xffff)
+	   * (unsigned32)((imm >> 16) & 0xffff));
+  sum = temp + temp2 + State.regs[REG_MCRL];
+  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+        && (temp & 0x80000000) != (sum & 0x80000000));
+  State.regs[REG_MCRL] = sum;
+  if (v)
+    State.regs[REG_MCVF] = 1;
 }
-  
-// 1111 0111 0010 0000 Rm1 Rn1 Rm2 Rn2; add_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_sub
-"add_sub"
+
+// 1111 1110 1000 1011 Rn Rn IMM32; dmulh imm32,Rn
+8.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh
+"dmulh"
 *am33
+*am33_2
 {
-  int srcreg1, srcreg2, dstreg1, dstreg2;
+  int imm, dstreg;
+  signed32 temp;
 
   PC = cia;
-  srcreg1 = translate_rreg (SD_, RM1);
-  srcreg2 = translate_rreg (SD_, RM2);
-  dstreg1 = translate_rreg (SD_, RN1);
-  dstreg2 = translate_rreg (SD_, RN2);
+  dstreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
-  State.regs[dstreg2] -= State.regs[srcreg2];
+  temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
+          * (signed32)(signed16)(imm & 0xffff));
+  State.regs[REG_MDRQ] = temp;
+  temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
+          * (signed32)(signed16)((imm>>16) & 0xffff));
+  State.regs[dstreg] = temp;
+}
+
+// 1111 1110 1001 1011 Rn Rn IMM32; dmulhu imm32,Rn
+8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu
+"dmulhu"
+*am33
+*am33_2
+{
+  int imm, dstreg;
+  signed32 temp;
+
+  PC = cia;
+  dstreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+  temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
+          * (unsigned32)(imm & 0xffff));
+  State.regs[REG_MDRQ] = temp;
+  temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
+          * (unsigned32)((imm >>16) & 0xffff));
+  State.regs[dstreg] = temp;
+}
+
+// 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
+8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
+"mov"
+*am33
+*am33_2
+{
+  int dstreg;
+
+  PC = cia;
+  dstreg = translate_rreg (SD_, RN2);
+  State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
+8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
+"mov"
+*am33
+*am33_2
+{
+  int srcreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM2);
+  store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
+}
+
+// 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
+8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
+"movbu"
+*am33
+*am33_2
+{
+  int dstreg;
+
+  PC = cia;
+  dstreg = translate_rreg (SD_, RN2);
+  State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
+8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
+"movbu"
+*am33
+*am33_2
+{
+  int srcreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM2);
+  store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
+}
+
+// 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
+8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
+"movhu"
+*am33
+*am33_2
+{
+  int dstreg;
+
+  PC = cia;
+  dstreg = translate_rreg (SD_, RN2);
+  State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
+8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
+"movhu"
+*am33
+*am33_2
+{
+  int srcreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM2);
+  store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
+}
+
+// 1111 0111 0000 0000 Rm1 Rn1 Rm2 Rn2; add_add Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_add
+"add_add"
+*am33
+*am33_2
+{
+  int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
+
+  PC = cia;
+  srcreg1 = translate_rreg (SD_, RM1);
+  srcreg2 = translate_rreg (SD_, RM2);
+  dstreg1 = translate_rreg (SD_, RN1);
+  dstreg2 = translate_rreg (SD_, RN2);
+
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
+  State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0001 0000 Rm1 Rn1 imm4 Rn2; add_add Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_add
+"add_add"
+*am33
+*am33_2
+{
+  int srcreg1, dstreg1, dstreg2;
+  int result1;
+
+  PC = cia;
+  srcreg1 = translate_rreg (SD_, RM1);
+  dstreg1 = translate_rreg (SD_, RN1);
+  dstreg2 = translate_rreg (SD_, RN2);
+
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
+  State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
+}
+  
+// 1111 0111 0010 0000 Rm1 Rn1 Rm2 Rn2; add_sub Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_sub
+"add_sub"
+*am33
+*am33_2
+{
+  int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
+
+  PC = cia;
+  srcreg1 = translate_rreg (SD_, RM1);
+  srcreg2 = translate_rreg (SD_, RM2);
+  dstreg1 = translate_rreg (SD_, RN1);
+  dstreg2 = translate_rreg (SD_, RN2);
+
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
+  State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 0000 Rm1 Rn1 imm4 Rn2; add_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_sub
+8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_sub
 "add_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 0000 Rm1 Rn1 Rm2 Rn2; add_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_cmp
+8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_cmp
 "add_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -4597,14 +5121,15 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] += State.regs[srcreg1];
 }
 
 // 1111 0111 0101 0000 Rm1 Rn1 imm4 Rn2; add_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_cmp
+8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_cmp
 "add_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -4613,16 +5138,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] += State.regs[srcreg1];
 }
   
 // 1111 0111 0110 0000 Rm1 Rn1 Rm2 Rn2; add_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_mov
+8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_mov
 "add_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -4630,32 +5157,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 0000 Rm1 Rn1 imm4 Rn2; add_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_mov
+8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_mov
 "add_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 0000 Rm1 Rn1 Rm2 Rn2; add_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_asr
+8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asr
 "add_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -4664,18 +5197,21 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 0000 Rm1 Rn1 imm4 Rn2; add_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_asr
+8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asr
 "add_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -4683,18 +5219,21 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 0000 Rm1 Rn1 Rm2 Rn2; add_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_lsr
+8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_lsr
 "add_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -4702,34 +5241,39 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 0000 Rm1 Rn1 imm4 Rn2; add_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_lsr
+8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_lsr
 "add_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 0000 Rm1 Rn1 Rm2 Rn2; add_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_asl
+8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asl
 "add_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -4737,31 +5281,35 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 0000 Rm1 Rn1 imm4 Rn2; add_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_asl
+8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asl
 "add_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0000 0001 Rm1 Rn1 Rm2 Rn2; cmp_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_add
+8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_add
 "cmp_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -4776,9 +5324,10 @@
 }
 
 // 1111 0111 0001 0001 Rm1 Rn1 imm4 Rn2; cmp_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_add
+8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_add
 "cmp_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -4792,9 +5341,10 @@
 }
   
 // 1111 0111 0010 0001 Rm1 Rn1 Rm2 Rn2; cmp_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_sub
+8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_sub
 "cmp_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -4809,9 +5359,10 @@
 }
 
 // 1111 0111 0011 0001 Rm1 Rn1 imm4 Rn2; cmp_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_sub
+8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_sub
 "cmp_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -4825,9 +5376,10 @@
 }
   
 // 1111 0111 0110 0001 Rm1 Rn1 Rm2 Rn2; cmp_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_mov
+8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_mov
 "cmp_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -4842,9 +5394,10 @@
 }
 
 // 1111 0111 0111 0001 Rm1 Rn1 imm4 Rn2; cmp_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_mov
+8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_mov
 "cmp_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -4858,9 +5411,10 @@
 }
   
 // 1111 0111 1000 0001 Rm1 Rn1 Rm2 Rn2; cmp_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_asr
+8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asr
 "cmp_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   signed int temp;
@@ -4878,9 +5432,10 @@
 }
 
 // 1111 0111 1001 0001 Rm1 Rn1 imm4 Rn2; cmp_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_asr
+8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asr
 "cmp_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   signed int temp;
@@ -4897,9 +5452,10 @@
 }
 
 // 1111 0111 1010 0001 Rm1 Rn1 Rm2 Rn2; cmp_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_lsr
+8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_lsr
 "cmp_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -4914,12 +5470,12 @@
 }
 
 // 1111 0111 1011 0001 Rm1 Rn1 imm4 Rn2; cmp_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_lsr
+8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_lsr
 "cmp_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -4932,9 +5488,10 @@
   
   
 // 1111 0111 1100 0001 Rm1 Rn1 Rm2 Rn2; cmp_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_asl
+8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asl
 "cmp_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -4949,12 +5506,12 @@
 }
 
 // 1111 0111 1101 0001 Rm1 Rn1 imm4 Rn2; cmp_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_asl
+8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asl
 "cmp_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -4966,11 +5523,13 @@
 }
 
 // 1111 0111 0000 0010 Rm1 Rn1 Rm2 Rn2; sub_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_add
+8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_add
 "sub_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -4978,32 +5537,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 0010 Rm1 Rn1 imm4 Rn2; sub_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_add
+8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_add
 "sub_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 0010 Rm1 Rn1 Rm2 Rn2; sub_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_sub
+8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_sub
 "sub_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5011,30 +5576,35 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 0010 Rm1 Rn1 imm4 Rn2; sub_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_sub
+8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_sub
 "sub_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 0010 Rm1 Rn1 Rm2 Rn2; sub_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_cmp
+8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_cmp
 "sub_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -5044,14 +5614,15 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] -= State.regs[srcreg1];
 }
 
 // 1111 0111 0101 0010 Rm1 Rn1 imm4 Rn2; sub_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_cmp
+8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_cmp
 "sub_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -5060,16 +5631,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] -= State.regs[srcreg1];
 }
   
 // 1111 0111 0110 0010 Rm1 Rn1 Rm2 Rn2; sub_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_mov
+8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_mov
 "sub_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5077,32 +5650,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 0010 Rm1 Rn1 imm4 Rn2; sub_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_mov
+8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_mov
 "sub_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 0010 Rm1 Rn1 Rm2 Rn2; sub_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_asr
+8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asr
 "sub_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -5111,18 +5690,21 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 0010 Rm1 Rn1 imm4 Rn2; sub_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_asr
+8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asr
 "sub_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -5130,18 +5712,21 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 0010 Rm1 Rn1 Rm2 Rn2; sub_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_lsr
+8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_lsr
 "sub_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5149,34 +5734,39 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 0010 Rm1 Rn1 imm4 Rn2; sub_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_lsr
+8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_lsr
 "sub_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 0010 Rm1 Rn1 Rm2 Rn2; sub_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_asl
+8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asl
 "sub_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5184,33 +5774,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 0010 Rm1 Rn1 imm4 Rn2; sub_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_asl
+8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asl
 "sub_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0000 0011 Rm1 Rn1 Rm2 Rn2; mov_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_add
+8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_add
 "mov_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5218,32 +5813,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 0011 Rm1 Rn1 imm4 Rn2; mov_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_add
+8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_add
 "mov_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 0011 Rm1 Rn1 Rm2 Rn2; mov_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_sub
+8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_sub
 "mov_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5251,30 +5852,35 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 0011 Rm1 Rn1 imm4 Rn2; mov_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_sub
+8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_sub
 "mov_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 0011 Rm1 Rn1 Rm2 Rn2; mov_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_cmp
+8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_cmp
 "mov_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -5284,14 +5890,15 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] = State.regs[srcreg1];
 }
 
 // 1111 0111 0101 0011 Rm1 Rn1 imm4 Rn2; mov_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_cmp
+8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_cmp
 "mov_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -5300,16 +5907,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] = State.regs[srcreg1];
 }
   
 // 1111 0111 0110 0011 Rm1 Rn1 Rm2 Rn2; mov_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_mov
+8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_mov
 "mov_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5317,32 +5926,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 0011 Rm1 Rn1 imm4 Rn2; mov_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_mov
+8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_mov
 "mov_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 0011 Rm1 Rn1 Rm2 Rn2; mov_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_asr
+8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asr
 "mov_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -5351,18 +5966,21 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 0011 Rm1 Rn1 imm4 Rn2; mov_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_asr
+8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asr
 "mov_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -5370,18 +5988,21 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 0011 Rm1 Rn1 Rm2 Rn2; mov_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_lsr
+8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_lsr
 "mov_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5389,34 +6010,39 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 0011 Rm1 Rn1 imm4 Rn2; mov_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_lsr
+8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_lsr
 "mov_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 0011 Rm1 Rn1 Rm2 Rn2; mov_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_asl
+8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asl
 "mov_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5424,93 +6050,109 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 0011 Rm1 Rn1 imm4 Rn2; mov_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_asl
+8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asl
 "mov_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0000 0100 imm4 Rn1 Rm2 Rn2; add_add imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_add
+8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_add
 "add_add"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 0100 imm4 Rn1 imm4 Rn2; add_add imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_add
+8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_add
 "add_add"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 0100 imm4 Rn1 Rm2 Rn2; add_sub imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_sub
+8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_sub
 "add_sub"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 0100 imm4 Rn1 imm4 Rn2; add_sub imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_sub
+8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_sub
 "add_sub"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 0100 imm4 Rn1 Rm2 Rn2; add_cmp imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_cmp
+8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_cmp
 "add_cmp"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
 
@@ -5519,14 +6161,15 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] += EXTEND4 (IMM4A);
 }
 
 // 1111 0111 0101 0100 imm4 Rn1 imm4 Rn2; add_cmp imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_cmp
+8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_cmp
 "add_cmp"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
 
@@ -5534,47 +6177,55 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] += EXTEND4 (IMM4A);
 }
   
 // 1111 0111 0110 0100 imm4 Rn1 Rm2 Rn2; add_mov imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_mov
+8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_mov
 "add_mov"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 0100 imm4 Rn1 imm4 Rn2; add_mov imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_mov
+8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_mov
 "add_mov"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 0100 imm4 Rn1 Rm2 Rn2; add_asr imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_asr
+8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asr
 "add_asr"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -5582,99 +6233,114 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 0100 imm4 Rn1 imm4 Rn2; add_asr imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_asr
+8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asr
 "add_asr"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 0100 imm4 Rn1 Rm2 Rn2; add_lsr imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_lsr
+8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_lsr
 "add_lsr"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 0100 imm4 Rn1 imm4 Rn2; add_lsr imm4, Rn1, imm4, Rn2
-8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_lsr
+8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_lsr
 "add_lsr"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 0100 imm4 Rn1 Rm2 Rn2; add_asl imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_asl
+8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asl
 "add_asl"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 0100 imm4 Rn1 imm4 Rn2; add_asl imm4, Rn1, imm4, Rn2
-8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_asl
+8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asl
 "add_asl"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0000 0101 imm4 Rn1 Rm2 Rn2; cmp_add imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_add
+8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_add
 "cmp_add"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
 
@@ -5688,9 +6354,10 @@
 }
 
 // 1111 0111 0001 0101 imm4 Rn1 imm4 Rn2; cmp_add imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_add
+8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_add
 "cmp_add"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
 
@@ -5703,9 +6370,10 @@
 }
   
 // 1111 0111 0010 0101 imm4 Rn1 Rm2 Rn2; cmp_sub imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_sub
+8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_sub
 "cmp_sub"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
 
@@ -5719,9 +6387,10 @@
 }
 
 // 1111 0111 0011 0101 imm4 Rn1 imm4 Rn2; cmp_sub imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_sub
+8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_sub
 "cmp_sub"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
 
@@ -5734,9 +6403,10 @@
 }
   
 // 1111 0111 0110 0101 imm4 Rn1 Rm2 Rn2; cmp_mov imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_mov
+8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_mov
 "cmp_mov"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
 
@@ -5750,9 +6420,10 @@
 }
 
 // 1111 0111 0111 0101 imm4 Rn1 imm4 Rn2; cmp_mov imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_mov
+8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_mov
 "cmp_mov"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
 
@@ -5765,9 +6436,10 @@
 }
   
 // 1111 0111 1000 0101 imm4 Rn1 Rm2 Rn2; cmp_asr imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_asr
+8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asr
 "cmp_asr"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
   signed int temp;
@@ -5784,9 +6456,10 @@
 }
 
 // 1111 0111 1001 0101 imm4 Rn1 imm4 Rn2; cmp_asr imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_asr
+8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asr
 "cmp_asr"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
   signed int temp;
@@ -5802,9 +6475,10 @@
 }
   
 // 1111 0111 1010 0101 imm4 Rn1 Rm2 Rn2; cmp_lsr imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_lsr
+8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_lsr
 "cmp_lsr"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
 
@@ -5818,12 +6492,12 @@
 }
 
 // 1111 0111 1011 0101 imm4 Rn1 imm4 Rn2; cmp_lsr imm4, Rn1, imm4, Rn2
-8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_lsr
+8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_lsr
 "cmp_lsr"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
-  signed int temp;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
@@ -5835,9 +6509,10 @@
   
   
 // 1111 0111 1100 0101 imm4 Rn1 Rm2 Rn2; cmp_asl imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_asl
+8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asl
 "cmp_asl"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
 
@@ -5851,12 +6526,12 @@
 }
 
 // 1111 0111 1101 0101 imm4 Rn1 imm4 Rn2; cmp_asl imm4, Rn1, imm4, Rn2
-8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_asl
+8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asl
 "cmp_asl"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
-  signed int temp;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
@@ -5867,71 +6542,84 @@
 }
 
 // 1111 0111 0000 0110 imm4 Rn1 Rm2 Rn2; sub_add imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_add
+8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_add
 "sub_add"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 0110 imm4 Rn1 imm4 Rn2; sub_add imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_add
+8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_add
 "sub_add"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 0110 imm4 Rn1 Rm2 Rn2; sub_sub imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_sub
+8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_sub
 "sub_sub"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 0110 imm4 Rn1 imm4 Rn2; sub_sub imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_sub
+8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_sub
 "sub_sub"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 0110 imm4 Rn1 Rm2 Rn2; sub_cmp imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_cmp
+8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_cmp
 "sub_cmp"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
 
@@ -5940,14 +6628,15 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] -= EXTEND4 (IMM4A);
 }
 
 // 1111 0111 0101 0110 imm4 Rn1 imm4 Rn2; sub_cmp imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_cmp
+8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_cmp
 "sub_cmp"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
 
@@ -5955,47 +6644,55 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] -= EXTEND4 (IMM4A);
 }
   
 // 1111 0111 0110 0110 imm4 Rn1 Rm2 Rn2; sub_mov imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_mov
+8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_mov
 "sub_mov"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 0110 imm4 Rn1 imm4 Rn2; sub_mov imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_mov
+8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_mov
 "sub_mov"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 0110 imm4 Rn1 Rm2 Rn2; sub_asr imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_asr
+8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asr
 "sub_asr"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -6003,161 +6700,188 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 0110 imm4 Rn1 imm4 Rn2; sub_asr imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_asr
+8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asr
 "sub_asr"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 0110 imm4 Rn1 Rm2 Rn2; sub_lsr imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_lsr
+8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_lsr
 "sub_lsr"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 0110 imm4 Rn1 imm4 Rn2; sub_lsr imm4, Rn1, imm4, Rn2
-8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_lsr
+8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_lsr
 "sub_lsr"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 0110 imm4 Rn1 Rm2 Rn2; sub_asl imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_asl
+8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asl
 "sub_asl"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 0110 imm4 Rn1 imm4 Rn2; sub_asl imm4, Rn1, imm4, Rn2
-8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_asl
+8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asl
 "sub_asl"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0000 0111 imm4 Rn1 Rm2 Rn2; mov_add imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_add
+8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_add
 "mov_add"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 0111 imm4 Rn1 imm4 Rn2; mov_add imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_add
+8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_add
 "mov_add"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 0111 imm4 Rn1 Rm2 Rn2; mov_sub imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_sub
+8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_sub
 "mov_sub"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 0111 imm4 Rn1 imm4 Rn2; mov_sub imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_sub
+8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_sub
 "mov_sub"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 0111 imm4 Rn1 Rm2 Rn2; mov_cmp imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_cmp
+8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_cmp
 "mov_cmp"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
 
@@ -6166,14 +6890,15 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] = EXTEND4 (IMM4A);
 }
 
 // 1111 0111 0101 0111 imm4 Rn1 imm4 Rn2; mov_cmp imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_cmp
+8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_cmp
 "mov_cmp"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
 
@@ -6181,47 +6906,55 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] = EXTEND4 (IMM4A);
 }
   
 // 1111 0111 0110 0111 imm4 Rn1 Rm2 Rn2; mov_mov imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_mov
+8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_mov
 "mov_mov"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 0111 imm4 Rn1 imm4 Rn2; mov_mov imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_mov
+8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_mov
 "mov_mov"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 0111 imm4 Rn1 Rm2 Rn2; mov_asr imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_asr
+8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asr
 "mov_asr"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -6229,101 +6962,117 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 0111 imm4 Rn1 imm4 Rn2; mov_asr imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_asr
+8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asr
 "mov_asr"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 0111 imm4 Rn1 Rm2 Rn2; mov_lsr imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_lsr
+8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_lsr
 "mov_lsr"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 0111 imm4 Rn1 imm4 Rn2; mov_lsr imm4, Rn1, imm4, Rn2
-8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_lsr
+8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_lsr
 "mov_lsr"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 0111 imm4 Rn1 Rm2 Rn2; mov_asl imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_asl
+8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asl
 "mov_asl"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 0111 imm4 Rn1 imm4 Rn2; mov_asl imm4, Rn1, imm4, Rn2
-8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_asl
+8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asl
 "mov_asl"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
  
 // 1111 0111 0000 1000 Rm1 Rn1 Rm2 Rn2; and_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_add
+8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_add
 "and_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6331,32 +7080,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 1000 Rm1 Rn1 imm4 Rn2; and_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_add
+8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_add
 "and_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 1000 Rm1 Rn1 Rm2 Rn2; and_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_sub
+8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_sub
 "and_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6364,30 +7119,35 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 1000 Rm1 Rn1 imm4 Rn2; and_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_sub
+8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_sub
 "and_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 1000 Rm1 Rn1 Rm2 Rn2; and_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_cmp
+8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_cmp
 "and_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -6397,14 +7157,15 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] &= State.regs[srcreg1];
 }
 
 // 1111 0111 0101 1000 Rm1 Rn1 imm4 Rn2; and_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_cmp
+8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_cmp
 "and_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -6413,16 +7174,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] &= State.regs[srcreg1];
 }
   
 // 1111 0111 0110 1000 Rm1 Rn1 Rm2 Rn2; and_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_mov
+8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_mov
 "and_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6430,32 +7193,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 1000 Rm1 Rn1 imm4 Rn2; and_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_mov
+8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_mov
 "and_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 1000 Rm1 Rn1 Rm2 Rn2; and_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_asr
+8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asr
 "and_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -6464,18 +7233,21 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 1000 Rm1 Rn1 imm4 Rn2; and_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_asr
+8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asr
 "and_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -6483,18 +7255,21 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 1000 Rm1 Rn1 Rm2 Rn2; and_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_lsr
+8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_lsr
 "and_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6502,34 +7277,39 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 1000 Rm1 Rn1 imm4 Rn2; and_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_lsr
+8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_lsr
 "and_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 1000 Rm1 Rn1 Rm2 Rn2; and_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_asl
+8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asl
 "and_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6537,34 +7317,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 1000 Rm1 Rn1 imm4 Rn2; and_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_asl
+8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asl
 "and_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0000 1001 Rm1 Rn1 Rm2 Rn2; dmach_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_add
+8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_add
 "dmach_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6578,17 +7362,18 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = sum;
 }
 
 // 1111 0111 0001 1001 Rm1 Rn1 imm4 Rn2; dmach_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_add
+8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_add
 "dmach_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6601,17 +7386,18 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = sum;
 }
   
 // 1111 0111 0010 1001 Rm1 Rn1 Rm2 Rn2; dmach_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_sub
+8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_sub
 "dmach_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6625,17 +7411,18 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = sum;
 }
 
 // 1111 0111 0011 1001 Rm1 Rn1 imm4 Rn2; dmach_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_sub
+8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_sub
 "dmach_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6648,17 +7435,18 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = sum;
 }
   
 // 1111 0111 0100 1001 Rm1 Rn1 Rm2 Rn2; dmach_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_cmp
+8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_cmp
 "dmach_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6672,17 +7460,18 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] = sum;
 }
 
 // 1111 0111 0101 1001 Rm1 Rn1 imm4 Rn2; dmach_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_cmp
+8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_cmp
 "dmach_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6695,17 +7484,18 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] = sum;
 }
   
 // 1111 0111 0110 1001 Rm1 Rn1 Rm2 Rn2; dmach_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_mov
+8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_mov
 "dmach_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6719,17 +7509,18 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = sum;
 }
 
 // 1111 0111 0111 1001 Rm1 Rn1 imm4 Rn2; dmach_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_mov
+8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_mov
 "dmach_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6742,17 +7533,18 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = sum;
 }
   
 // 1111 0111 1000 1001 Rm1 Rn1 Rm2 Rn2; dmach_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_asr
+8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asr
 "dmach_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6766,19 +7558,20 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = sum;
 }
 
 // 1111 0111 1001 1001 Rm1 Rn1 imm4 Rn2; dmach_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_asr
+8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asr
 "dmach_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6791,19 +7584,20 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = sum;
 }
   
 // 1111 0111 1010 1001 Rm1 Rn1 Rm2 Rn2; dmach_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_lsr
+8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_lsr
 "dmach_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6817,34 +7611,43 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = sum;
 }
 
 // 1111 0111 1011 1001 Rm1 Rn1 imm4 Rn2; dmach_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_lsr
+8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_lsr
 "dmach_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
+  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+  sum = temp + temp2 + State.regs[REG_MCRL];
+
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = sum;
 }
   
   
 // 1111 0111 1100 1001 Rm1 Rn1 Rm2 Rn2; dmach_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_asl
+8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asl
 "dmach_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6858,17 +7661,18 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = sum;
 }
 
 // 1111 0111 1101 1001 Rm1 Rn1 imm4 Rn2; dmach_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_asl
+8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asl
 "dmach_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6881,16 +7685,18 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = sum;
 }
 
 // 1111 0111 0000 1010 Rm1 Rn1 Rm2 Rn2; xor_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_add
+8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_add
 "xor_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6898,32 +7704,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 1010 Rm1 Rn1 imm4 Rn2; xor_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_add
+8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_add
 "xor_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 1010 Rm1 Rn1 Rm2 Rn2; xor_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_sub
+8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_sub
 "xor_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6931,30 +7743,35 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 1010 Rm1 Rn1 imm4 Rn2; xor_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_sub
+8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_sub
 "xor_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 1010 Rm1 Rn1 Rm2 Rn2; xor_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_cmp
+8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_cmp
 "xor_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -6964,14 +7781,15 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] ^= State.regs[srcreg1];
 }
 
 // 1111 0111 0101 1010 Rm1 Rn1 imm4 Rn2; xor_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_cmp
+8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_cmp
 "xor_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -6980,16 +7798,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] ^= State.regs[srcreg1];
 }
   
 // 1111 0111 0110 1010 Rm1 Rn1 Rm2 Rn2; xor_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_mov
+8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_mov
 "xor_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6997,32 +7817,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 1010 Rm1 Rn1 imm4 Rn2; xor_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_mov
+8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_mov
 "xor_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 1010 Rm1 Rn1 Rm2 Rn2; xor_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_asr
+8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asr
 "xor_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7031,18 +7857,21 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 1010 Rm1 Rn1 imm4 Rn2; xor_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_asr
+8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asr
 "xor_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7050,18 +7879,21 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 1010 Rm1 Rn1 Rm2 Rn2; xor_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_lsr
+8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_lsr
 "xor_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7069,34 +7901,39 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 1010 Rm1 Rn1 imm4 Rn2; xor_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_lsr
+8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_lsr
 "xor_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 1010 Rm1 Rn1 Rm2 Rn2; xor_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_asl
+8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asl
 "xor_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7104,33 +7941,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 1010 Rm1 Rn1 imm4 Rn2; xor_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_asl
+8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asl
 "xor_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0000 1011 Rm1 Rn1 Rm2 Rn2; swhw_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_add
+8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_add
 "swhw_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7138,33 +7980,39 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 1011 Rm1 Rn1 imm4 Rn2; swhw_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_add
+8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_add
 "swhw_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 1011 Rm1 Rn1 Rm2 Rn2; swhw_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_sub
+8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_sub
 "swhw_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7172,32 +8020,37 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 1011 Rm1 Rn1 imm4 Rn2; swhw_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_sub
+8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_sub
 "swhw_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 1011 Rm1 Rn1 Rm2 Rn2; swhw_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_cmp
+8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_cmp
 "swhw_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -7207,15 +8060,16 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
+  genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
   State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
                          | ((State.regs[srcreg1] >> 16) & 0xffff));
-  genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
 }
 
 // 1111 0111 0101 1011 Rm1 Rn1 imm4 Rn2; swhw_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_cmp
+8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_cmp
 "swhw_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -7224,17 +8078,19 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
+  genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
   State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
                          | ((State.regs[srcreg1] >> 16) & 0xffff));
-  genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
 }
   
 // 1111 0111 0110 1011 Rm1 Rn1 Rm2 Rn2; swhw_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_mov
+8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_mov
 "swhw_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7242,34 +8098,40 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 1011 Rm1 Rn1 imm4 Rn2; swhw_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_mov
+8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_mov
 "swhw_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 1011 Rm1 Rn1 Rm2 Rn2; swhw_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_asr
+8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asr
 "swhw_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7278,19 +8140,22 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 1011 Rm1 Rn1 imm4 Rn2; swhw_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_asr
+8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asr
 "swhw_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7298,19 +8163,22 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 1011 Rm1 Rn1 Rm2 Rn2; swhw_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_lsr
+8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_lsr
 "swhw_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7318,36 +8186,41 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 1011 Rm1 Rn1 imm4 Rn2; swhw_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_lsr
+8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_lsr
 "swhw_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 1011 Rm1 Rn1 Rm2 Rn2; swhw_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_asl
+8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asl
 "swhw_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7355,35 +8228,40 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 1011 Rm1 Rn1 imm4 Rn2; swhw_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_asl
+8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asl
 "swhw_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0000 1100 Rm1 Rn1 Rm2 Rn2; or_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_add
+8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_add
 "or_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7391,32 +8269,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 1100 Rm1 Rn1 imm4 Rn2; or_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_add
+8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_add
 "or_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 1100 Rm1 Rn1 Rm2 Rn2; or_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_sub
+8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_sub
 "or_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7424,30 +8308,35 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 1100 Rm1 Rn1 imm4 Rn2; or_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_sub
+8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_sub
 "or_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 1100 Rm1 Rn1 Rm2 Rn2; or_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_cmp
+8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_cmp
 "or_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -7457,14 +8346,15 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] |= State.regs[srcreg1];
 }
 
 // 1111 0111 0101 1100 Rm1 Rn1 imm4 Rn2; or_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_cmp
+8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_cmp
 "or_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -7473,16 +8363,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] |= State.regs[srcreg1];
 }
   
 // 1111 0111 0110 1100 Rm1 Rn1 Rm2 Rn2; or_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_mov
+8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_mov
 "or_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7490,32 +8382,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 1100 Rm1 Rn1 imm4 Rn2; or_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_mov
+8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_mov
 "or_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 1100 Rm1 Rn1 Rm2 Rn2; or_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_asr
+8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asr
 "or_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7524,18 +8422,21 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 1100 Rm1 Rn1 imm4 Rn2; or_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_asr
+8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asr
 "or_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7543,18 +8444,21 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 1100 Rm1 Rn1 Rm2 Rn2; or_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_lsr
+8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_lsr
 "or_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7562,34 +8466,39 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 1100 Rm1 Rn1 imm4 Rn2; or_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_lsr
+8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_lsr
 "or_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 1100 Rm1 Rn1 Rm2 Rn2; or_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_asl
+8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asl
 "or_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7597,33 +8506,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 1100 Rm1 Rn1 imm4 Rn2; or_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_asl
+8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asl
 "or_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0000 1101 Rm1 Rn1 Rm2 Rn2; sat16_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_add
+8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_add
 "sat16_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7632,21 +8546,24 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 1101 Rm1 Rn1 imm4 Rn2; sat16_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_add
+8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_add
 "sat16_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7654,21 +8571,24 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 1101 Rm1 Rn1 Rm2 Rn2; sat16_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_sub
+8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_sub
 "sat16_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7677,21 +8597,24 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 1101 Rm1 Rn1 imm4 Rn2; sat16_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_sub
+8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_sub
 "sat16_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7699,19 +8622,21 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 1101 Rm1 Rn1 Rm2 Rn2; sat16_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_cmp
+8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_cmp
 "sat16_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -7721,20 +8646,20 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
+  genericCmp (State.regs[dstreg2], State.regs[dstreg1]);
   if (State.regs[srcreg1] >= 0x7fff)
     State.regs[dstreg1] = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
     State.regs[dstreg1] = 0xffff8000;
   else
     State.regs[dstreg1] = State.regs[srcreg1];
-
-  genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
 }
 
 // 1111 0111 0101 1101 Rm1 Rn1 imm4 Rn2; sat16_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_cmp
+8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_cmp
 "sat16_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -7743,22 +8668,23 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
+  genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
   if (State.regs[srcreg1] >= 0x7fff)
     State.regs[dstreg1] = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
     State.regs[dstreg1] = 0xffff8000;
   else
     State.regs[dstreg1] = State.regs[srcreg1];
-
-  genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
 }
   
 // 1111 0111 0110 1101 Rm1 Rn1 Rm2 Rn2; sat16_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_mov
+8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_mov
 "sat16_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7767,21 +8693,24 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 1101 Rm1 Rn1 imm4 Rn2; sat16_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_mov
+8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_mov
 "sat16_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7789,21 +8718,24 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 1101 Rm1 Rn1 Rm2 Rn2; sat16_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_asr
+8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asr
 "sat16_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7813,23 +8745,26 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 1101 Rm1 Rn1 imm4 Rn2; sat16_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_asr
+8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asr
 "sat16_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7838,23 +8773,26 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 1101 Rm1 Rn1 Rm2 Rn2; sat16_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_lsr
+8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_lsr
 "sat16_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7863,22 +8801,24 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 1101 Rm1 Rn1 imm4 Rn2; sat16_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_lsr
+8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_lsr
 "sat16_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7886,22 +8826,25 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 1101 Rm1 Rn1 Rm2 Rn2; sat16_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_asl
+8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asl
 "sat16_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7910,22 +8853,24 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 1101 Rm1 Rn1 imm4 Rn2; sat16_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_asl
+8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asl
 "sat16_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7933,19 +8878,21 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0000; mov_llt (Rm+,imm4),Rn
-8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x0:D2:::mov_llt
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x0:D2:::mov_llt
 "mov_llt"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -7964,9 +8911,10 @@
 }
 
 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0001; mov_lgt (Rm+,imm4),Rn
-8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x1:D2:::mov_lgt
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x1:D2:::mov_lgt
 "mov_lgt"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -7986,9 +8934,10 @@
 }
 
 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0010; mov_lge (Rm+,imm4),Rn
-8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x2:D2:::mov_lge
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x2:D2:::mov_lge
 "mov_lge"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8007,9 +8956,10 @@
 }
 
 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0011; mov_lle (Rm+,imm4),Rn
-8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x3:D2:::mov_lle
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x3:D2:::mov_lle
 "mov_lle"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8029,9 +8979,10 @@
 }
 
 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0100; mov_lcs (Rm+,imm4),Rn
-8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x4:D2:::mov_lcs
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x4:D2:::mov_lcs
 "mov_lcs"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8050,9 +9001,10 @@
 }
 
 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0101; mov_lhi (Rm+,imm4),Rn
-8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x5:D2:::mov_lhi
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x5:D2:::mov_lhi
 "mov_lhi"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8071,9 +9023,10 @@
 }
 
 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0110; mov_lcc (Rm+,imm4),Rn
-8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x6:D2:::mov_lcc
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x6:D2:::mov_lcc
 "mov_lcc"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8092,9 +9045,10 @@
 }
 
 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0111; mov_lls (Rm+,imm4),Rn
-8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x7:D2:::mov_lls
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x7:D2:::mov_lls
 "mov_lls"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8113,9 +9067,10 @@
 }
 
 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1000; mov_leq (Rm+,imm4),Rn
-8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x8:D2:::mov_leq
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x8:D2:::mov_leq
 "mov_leq"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8134,9 +9089,10 @@
 }
 
 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1001; mov_lne (Rm+,imm4),Rn
-8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x9:D2:::mov_lne
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x9:D2:::mov_lne
 "mov_lne"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8155,9 +9111,10 @@
 }
 
 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1010; mov_lra (Rm+,imm4),Rn
-8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0xa:D2:::mov_lra
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0xa:D2:::mov_lra
 "mov_lra"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8171,3 +9128,5 @@
   State.regs[REG_PC] = State.regs[REG_LAR] - 4;
   nia = PC;
 }
+
+:include::am33_2:am33-2.igen