X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fmn10300%2Finterp.c;h=e5a90b546a0631d9df36daf2bae7d8a54a889669;hb=5d19c36612c6b08627280bb0063ad1222b0a92dd;hp=18a5dc3b232f7597b837c0a0f547fd701a611db3;hpb=599e0b9e0dab8c7bcfd02a5911d16b7bc4014521;p=deliverable%2Fbinutils-gdb.git diff --git a/sim/mn10300/interp.c b/sim/mn10300/interp.c index 18a5dc3b23..e5a90b546a 100644 --- a/sim/mn10300/interp.c +++ b/sim/mn10300/interp.c @@ -1,10 +1,10 @@ +#include "config.h" #include #include "sim-main.h" #include "sim-options.h" #include "sim-hw.h" -#include "sysdep.h" #include "bfd.h" #include "sim-assert.h" @@ -23,14 +23,6 @@ #include "bfd.h" -#ifndef INLINE -#ifdef __GNUC__ -#define INLINE inline -#else -#define INLINE -#endif -#endif - host_callback *mn10300_callback; int mn10300_debug; @@ -47,12 +39,11 @@ enum { }; static SIM_RC -mn10300_option_handler (sd, cpu, opt, arg, is_command) - SIM_DESC sd; - sim_cpu *cpu; - int opt; - char *arg; - int is_command; +mn10300_option_handler (SIM_DESC sd, + sim_cpu *cpu, + int opt, + char *arg, + int is_command) { int cpu_nr; switch (opt) @@ -85,20 +76,36 @@ static const OPTION mn10300_options[] = /* For compatibility */ SIM_DESC simulator; +static sim_cia +mn10300_pc_get (sim_cpu *cpu) +{ + return PC; +} + +static void +mn10300_pc_set (sim_cpu *cpu, sim_cia pc) +{ + PC = pc; +} + /* These default values correspond to expected usage for the chip. */ SIM_DESC -sim_open (kind, cb, abfd, argv) - SIM_OPEN_KIND kind; - host_callback *cb; - struct bfd *abfd; - char **argv; +sim_open (SIM_OPEN_KIND kind, + host_callback *cb, + struct bfd *abfd, + char **argv) { + int i; SIM_DESC sd = sim_state_alloc (kind, cb); mn10300_callback = cb; SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); + /* The cpu data is kept in a separately allocated chunk of memory. */ + if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK) + return 0; + /* for compatibility */ simulator = sd; @@ -299,25 +306,31 @@ sim_open (kind, cb, abfd, argv) /* STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT */ /* | PSW_CY | PSW_OV | PSW_S | PSW_Z); */ + /* CPU specific initialization. */ + for (i = 0; i < MAX_NR_PROCESSORS; ++i) + { + SIM_CPU *cpu = STATE_CPU (sd, i); + + CPU_PC_FETCH (cpu) = mn10300_pc_get; + CPU_PC_STORE (cpu) = mn10300_pc_set; + } + return sd; } void -sim_close (sd, quitting) - SIM_DESC sd; - int quitting; +sim_close (SIM_DESC sd, int quitting) { sim_module_uninstall (sd); } SIM_RC -sim_create_inferior (sd, prog_bfd, argv, env) - SIM_DESC sd; - struct bfd *prog_bfd; - char **argv; - char **env; +sim_create_inferior (SIM_DESC sd, + struct bfd *prog_bfd, + char **argv, + char **env) { memset (&State, 0, sizeof (State)); if (prog_bfd != NULL) { @@ -325,69 +338,46 @@ sim_create_inferior (sd, prog_bfd, argv, env) } else { PC = 0; } - CIA_SET (STATE_CPU (sd, 0), (unsigned64) PC); + CPU_PC_SET (STATE_CPU (sd, 0), (unsigned64) PC); - return SIM_RC_OK; -} + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2) + PSW |= PSW_FE; -void -sim_do_command (sd, cmd) - SIM_DESC sd; - char *cmd; -{ - char *mm_cmd = "memory-map"; - char *int_cmd = "interrupt"; - - if (sim_args_command (sd, cmd) != SIM_RC_OK) - { - if (strncmp (cmd, mm_cmd, strlen (mm_cmd) == 0)) - sim_io_eprintf (sd, "`memory-map' command replaced by `sim memory'\n"); - else if (strncmp (cmd, int_cmd, strlen (int_cmd)) == 0) - sim_io_eprintf (sd, "`interrupt' command replaced by `sim watch'\n"); - else - sim_io_eprintf (sd, "Unknown command `%s'\n", cmd); - } + return SIM_RC_OK; } /* FIXME These would more efficient to use than load_mem/store_mem, but need to be changed to use the memory map. */ uint8 -get_byte (x) - uint8 *x; +get_byte (uint8 *x) { return *x; } uint16 -get_half (x) - uint8 *x; +get_half (uint8 *x) { uint8 *a = x; return (a[1] << 8) + (a[0]); } uint32 -get_word (x) - uint8 *x; +get_word (uint8 *x) { uint8 *a = x; return (a[3]<<24) + (a[2]<<16) + (a[1]<<8) + (a[0]); } void -put_byte (addr, data) - uint8 *addr; - uint8 data; +put_byte (uint8 *addr, uint8 data) { uint8 *a = addr; a[0] = data; } void -put_half (addr, data) - uint8 *addr; - uint16 data; +put_half (uint8 *addr, uint16 data) { uint8 *a = addr; a[0] = data & 0xff; @@ -395,9 +385,7 @@ put_half (addr, data) } void -put_word (addr, data) - uint8 *addr; - uint32 data; +put_word (uint8 *addr, uint32 data) { uint8 *a = addr; a[0] = data & 0xff; @@ -407,37 +395,34 @@ put_word (addr, data) } int -sim_fetch_register (sd, rn, memory, length) - SIM_DESC sd; - int rn; - unsigned char *memory; - int length; +sim_fetch_register (SIM_DESC sd, + int rn, + unsigned char *memory, + int length) { put_word (memory, State.regs[rn]); - return -1; + return length; } int -sim_store_register (sd, rn, memory, length) - SIM_DESC sd; - int rn; - unsigned char *memory; - int length; +sim_store_register (SIM_DESC sd, + int rn, + unsigned char *memory, + int length) { State.regs[rn] = get_word (memory); - return -1; + return length; } - void mn10300_core_signal (SIM_DESC sd, - sim_cpu *cpu, - sim_cia cia, - unsigned map, - int nr_bytes, - address_word addr, - transfer_type transfer, - sim_core_signals sig) + sim_cpu *cpu, + sim_cia cia, + unsigned map, + int nr_bytes, + address_word addr, + transfer_type transfer, + sim_core_signals sig) { const char *copy = (transfer == read_transfer ? "read" : "write"); address_word ip = CIA_ADDR (cia); @@ -489,7 +474,7 @@ program_interrupt (SIM_DESC sd, { in_interrupt = 1; /* copy NMI handler code from dv-mn103cpu.c */ - store_word (SP - 4, CIA_GET (cpu)); + store_word (SP - 4, CPU_PC_GET (cpu)); store_half (SP - 8, PSW); /* Set the SYSEF flag in NMICR by backdoor method. See @@ -503,7 +488,7 @@ program_interrupt (SIM_DESC sd, PSW &= ~PSW_IE; SP = SP - 8; - CIA_SET (cpu, 0x40000008); + CPU_PC_SET (cpu, 0x40000008); in_interrupt = 0; sim_engine_halt(sd, cpu, NULL, cia, sim_stopped, sig); @@ -518,7 +503,7 @@ mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word cia) if(State.exc_suspended > 0) sim_io_eprintf(sd, "Warning, nested exception triggered (%d)\n", State.exc_suspended); - CIA_SET (cpu, cia); + CPU_PC_SET (cpu, cia); memcpy(State.exc_trigger_regs, State.regs, sizeof(State.exc_trigger_regs)); State.exc_suspended = 0; } @@ -534,7 +519,7 @@ mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception) memcpy(State.exc_suspend_regs, State.regs, sizeof(State.exc_suspend_regs)); memcpy(State.regs, State.exc_trigger_regs, sizeof(State.regs)); - CIA_SET (cpu, PC); /* copy PC back from new State.regs */ + CPU_PC_SET (cpu, PC); /* copy PC back from new State.regs */ State.exc_suspended = exception; } @@ -556,7 +541,7 @@ mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception) State.exc_suspended, exception); memcpy(State.regs, State.exc_suspend_regs, sizeof(State.regs)); - CIA_SET (cpu, PC); /* copy PC back from new State.regs */ + CPU_PC_SET (cpu, PC); /* copy PC back from new State.regs */ } else if(exception != 0 && State.exc_suspended == 0) { @@ -564,3 +549,569 @@ mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception) } State.exc_suspended = 0; } + +/* This is called when an FP instruction is issued when the FP unit is + disabled, i.e., the FE bit of PSW is zero. It raises interrupt + code 0x1c0. */ +void +fpu_disabled_exception (SIM_DESC sd, sim_cpu *cpu, sim_cia cia) +{ + sim_io_eprintf(sd, "FPU disabled exception\n"); + program_interrupt (sd, cpu, cia, SIM_SIGFPE); +} + +/* This is called when the FP unit is enabled but one of the + unimplemented insns is issued. It raises interrupt code 0x1c8. */ +void +fpu_unimp_exception (SIM_DESC sd, sim_cpu *cpu, sim_cia cia) +{ + sim_io_eprintf(sd, "Unimplemented FPU instruction exception\n"); + program_interrupt (sd, cpu, cia, SIM_SIGFPE); +} + +/* This is called at the end of any FP insns that may have triggered + FP exceptions. If no exception is enabled, it returns immediately. + Otherwise, it raises an exception code 0x1d0. */ +void +fpu_check_signal_exception (SIM_DESC sd, sim_cpu *cpu, sim_cia cia) +{ + if ((FPCR & EC_MASK) == 0) + return; + + sim_io_eprintf(sd, "FPU %s%s%s%s%s exception\n", + (FPCR & EC_V) ? "V" : "", + (FPCR & EC_Z) ? "Z" : "", + (FPCR & EC_O) ? "O" : "", + (FPCR & EC_U) ? "U" : "", + (FPCR & EC_I) ? "I" : ""); + program_interrupt (sd, cpu, cia, SIM_SIGFPE); +} + +/* Convert a 32-bit single-precision FP value in the target platform + format to a sim_fpu value. */ +static void +reg2val_32 (const void *reg, sim_fpu *val) +{ + FS2FPU (*(reg_t *)reg, *val); +} + +/* Round the given sim_fpu value to single precision, following the + target platform rounding and denormalization conventions. On + AM33/2.0, round_near is the only rounding mode. */ +static int +round_32 (sim_fpu *val) +{ + return sim_fpu_round_32 (val, sim_fpu_round_near, sim_fpu_denorm_zero); +} + +/* Convert a sim_fpu value to the 32-bit single-precision target + representation. */ +static void +val2reg_32 (const sim_fpu *val, void *reg) +{ + FPU2FS (*val, *(reg_t *)reg); +} + +/* Define the 32-bit single-precision conversion and rounding uniform + interface. */ +const struct fp_prec_t +fp_single_prec = { + reg2val_32, round_32, val2reg_32 +}; + +/* Convert a 64-bit double-precision FP value in the target platform + format to a sim_fpu value. */ +static void +reg2val_64 (const void *reg, sim_fpu *val) +{ + FD2FPU (*(dword *)reg, *val); +} + +/* Round the given sim_fpu value to double precision, following the + target platform rounding and denormalization conventions. On + AM33/2.0, round_near is the only rounding mode. */ +int +round_64 (sim_fpu *val) +{ + return sim_fpu_round_64 (val, sim_fpu_round_near, sim_fpu_denorm_zero); +} + +/* Convert a sim_fpu value to the 64-bit double-precision target + representation. */ +static void +val2reg_64 (const sim_fpu *val, void *reg) +{ + FPU2FD (*val, *(dword *)reg); +} + +/* Define the 64-bit single-precision conversion and rounding uniform + interface. */ +const struct fp_prec_t +fp_double_prec = { + reg2val_64, round_64, val2reg_64 +}; + +/* Define shortcuts to the uniform interface operations. */ +#define REG2VAL(reg,val) (*ops->reg2val) (reg,val) +#define ROUND(val) (*ops->round) (val) +#define VAL2REG(val,reg) (*ops->val2reg) (val,reg) + +/* Check whether overflow, underflow or inexact exceptions should be + raised. */ +int +fpu_status_ok (sim_fpu_status stat) +{ + if ((stat & sim_fpu_status_overflow) + && (FPCR & EE_O)) + FPCR |= EC_O; + else if ((stat & (sim_fpu_status_underflow | sim_fpu_status_denorm)) + && (FPCR & EE_U)) + FPCR |= EC_U; + else if ((stat & (sim_fpu_status_inexact | sim_fpu_status_rounded)) + && (FPCR & EE_I)) + FPCR |= EC_I; + else if (stat & ~ (sim_fpu_status_overflow + | sim_fpu_status_underflow + | sim_fpu_status_denorm + | sim_fpu_status_inexact + | sim_fpu_status_rounded)) + abort (); + else + return 1; + return 0; +} + +/* Implement a 32/64 bit reciprocal square root, signaling FP + exceptions when appropriate. */ +void +fpu_rsqrt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, + const void *reg_in, void *reg_out, const struct fp_prec_t *ops) +{ + sim_fpu in, med, out; + + REG2VAL (reg_in, &in); + ROUND (&in); + FPCR &= ~ EC_MASK; + switch (sim_fpu_is (&in)) + { + case SIM_FPU_IS_SNAN: + case SIM_FPU_IS_NNUMBER: + case SIM_FPU_IS_NINF: + if (FPCR & EE_V) + FPCR |= EC_V; + else + VAL2REG (&sim_fpu_qnan, reg_out); + break; + + case SIM_FPU_IS_QNAN: + VAL2REG (&sim_fpu_qnan, reg_out); + break; + + case SIM_FPU_IS_PINF: + VAL2REG (&sim_fpu_zero, reg_out); + break; + + case SIM_FPU_IS_PNUMBER: + { + /* Since we don't have a function to compute rsqrt directly, + use sqrt and inv. */ + sim_fpu_status stat = 0; + stat |= sim_fpu_sqrt (&med, &in); + stat |= sim_fpu_inv (&out, &med); + stat |= ROUND (&out); + if (fpu_status_ok (stat)) + VAL2REG (&out, reg_out); + } + break; + + case SIM_FPU_IS_NZERO: + case SIM_FPU_IS_PZERO: + if (FPCR & EE_Z) + FPCR |= EC_Z; + else + { + /* Generate an INF with the same sign. */ + sim_fpu_inv (&out, &in); + VAL2REG (&out, reg_out); + } + break; + + default: + abort (); + } + + fpu_check_signal_exception (sd, cpu, cia); +} + +static inline reg_t +cmp2fcc (int res) +{ + switch (res) + { + case SIM_FPU_IS_SNAN: + case SIM_FPU_IS_QNAN: + return FCC_U; + + case SIM_FPU_IS_NINF: + case SIM_FPU_IS_NNUMBER: + case SIM_FPU_IS_NDENORM: + return FCC_L; + + case SIM_FPU_IS_PINF: + case SIM_FPU_IS_PNUMBER: + case SIM_FPU_IS_PDENORM: + return FCC_G; + + case SIM_FPU_IS_NZERO: + case SIM_FPU_IS_PZERO: + return FCC_E; + + default: + abort (); + } +} + +/* Implement a 32/64 bit FP compare, setting the FPCR status and/or + exception bits as specified. */ +void +fpu_cmp (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, + const void *reg_in1, const void *reg_in2, + const struct fp_prec_t *ops) +{ + sim_fpu m, n; + + REG2VAL (reg_in1, &m); + REG2VAL (reg_in2, &n); + FPCR &= ~ EC_MASK; + FPCR &= ~ FCC_MASK; + ROUND (&m); + ROUND (&n); + if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n)) + { + if (FPCR & EE_V) + FPCR |= EC_V; + else + FPCR |= FCC_U; + } + else + FPCR |= cmp2fcc (sim_fpu_cmp (&m, &n)); + + fpu_check_signal_exception (sd, cpu, cia); +} + +/* Implement a 32/64 bit FP add, setting FP exception bits when + appropriate. */ +void +fpu_add (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, + const void *reg_in1, const void *reg_in2, + void *reg_out, const struct fp_prec_t *ops) +{ + sim_fpu m, n, r; + + REG2VAL (reg_in1, &m); + REG2VAL (reg_in2, &n); + ROUND (&m); + ROUND (&n); + FPCR &= ~ EC_MASK; + if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n) + || (sim_fpu_is (&m) == SIM_FPU_IS_PINF + && sim_fpu_is (&n) == SIM_FPU_IS_NINF) + || (sim_fpu_is (&m) == SIM_FPU_IS_NINF + && sim_fpu_is (&n) == SIM_FPU_IS_PINF)) + { + if (FPCR & EE_V) + FPCR |= EC_V; + else + VAL2REG (&sim_fpu_qnan, reg_out); + } + else + { + sim_fpu_status stat = sim_fpu_add (&r, &m, &n); + stat |= ROUND (&r); + if (fpu_status_ok (stat)) + VAL2REG (&r, reg_out); + } + + fpu_check_signal_exception (sd, cpu, cia); +} + +/* Implement a 32/64 bit FP sub, setting FP exception bits when + appropriate. */ +void +fpu_sub (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, + const void *reg_in1, const void *reg_in2, + void *reg_out, const struct fp_prec_t *ops) +{ + sim_fpu m, n, r; + + REG2VAL (reg_in1, &m); + REG2VAL (reg_in2, &n); + ROUND (&m); + ROUND (&n); + FPCR &= ~ EC_MASK; + if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n) + || (sim_fpu_is (&m) == SIM_FPU_IS_PINF + && sim_fpu_is (&n) == SIM_FPU_IS_PINF) + || (sim_fpu_is (&m) == SIM_FPU_IS_NINF + && sim_fpu_is (&n) == SIM_FPU_IS_NINF)) + { + if (FPCR & EE_V) + FPCR |= EC_V; + else + VAL2REG (&sim_fpu_qnan, reg_out); + } + else + { + sim_fpu_status stat = sim_fpu_sub (&r, &m, &n); + stat |= ROUND (&r); + if (fpu_status_ok (stat)) + VAL2REG (&r, reg_out); + } + + fpu_check_signal_exception (sd, cpu, cia); +} + +/* Implement a 32/64 bit FP mul, setting FP exception bits when + appropriate. */ +void +fpu_mul (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, + const void *reg_in1, const void *reg_in2, + void *reg_out, const struct fp_prec_t *ops) +{ + sim_fpu m, n, r; + + REG2VAL (reg_in1, &m); + REG2VAL (reg_in2, &n); + ROUND (&m); + ROUND (&n); + FPCR &= ~ EC_MASK; + if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n) + || (sim_fpu_is_infinity (&m) && sim_fpu_is_zero (&n)) + || (sim_fpu_is_zero (&m) && sim_fpu_is_infinity (&n))) + { + if (FPCR & EE_V) + FPCR |= EC_V; + else + VAL2REG (&sim_fpu_qnan, reg_out); + } + else + { + sim_fpu_status stat = sim_fpu_mul (&r, &m, &n); + stat |= ROUND (&r); + if (fpu_status_ok (stat)) + VAL2REG (&r, reg_out); + } + + fpu_check_signal_exception (sd, cpu, cia); +} + +/* Implement a 32/64 bit FP div, setting FP exception bits when + appropriate. */ +void +fpu_div (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, + const void *reg_in1, const void *reg_in2, + void *reg_out, const struct fp_prec_t *ops) +{ + sim_fpu m, n, r; + + REG2VAL (reg_in1, &m); + REG2VAL (reg_in2, &n); + ROUND (&m); + ROUND (&n); + FPCR &= ~ EC_MASK; + if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n) + || (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n)) + || (sim_fpu_is_zero (&m) && sim_fpu_is_zero (&n))) + { + if (FPCR & EE_V) + FPCR |= EC_V; + else + VAL2REG (&sim_fpu_qnan, reg_out); + } + else if (sim_fpu_is_number (&m) && sim_fpu_is_zero (&n) + && (FPCR & EE_Z)) + FPCR |= EC_Z; + else + { + sim_fpu_status stat = sim_fpu_div (&r, &m, &n); + stat |= ROUND (&r); + if (fpu_status_ok (stat)) + VAL2REG (&r, reg_out); + } + + fpu_check_signal_exception (sd, cpu, cia); +} + +/* Implement a 32/64 bit FP madd, setting FP exception bits when + appropriate. */ +void +fpu_fmadd (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, + const void *reg_in1, const void *reg_in2, const void *reg_in3, + void *reg_out, const struct fp_prec_t *ops) +{ + sim_fpu m1, m2, m, n, r; + + REG2VAL (reg_in1, &m1); + REG2VAL (reg_in2, &m2); + REG2VAL (reg_in3, &n); + ROUND (&m1); + ROUND (&m2); + ROUND (&n); + FPCR &= ~ EC_MASK; + if (sim_fpu_is_snan (&m1) || sim_fpu_is_snan (&m2) || sim_fpu_is_snan (&n) + || (sim_fpu_is_infinity (&m1) && sim_fpu_is_zero (&m2)) + || (sim_fpu_is_zero (&m1) && sim_fpu_is_infinity (&m2))) + { + invalid_operands: + if (FPCR & EE_V) + FPCR |= EC_V; + else + VAL2REG (&sim_fpu_qnan, reg_out); + } + else + { + sim_fpu_status stat = sim_fpu_mul (&m, &m1, &m2); + + if (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n) + && sim_fpu_sign (&m) != sim_fpu_sign (&n)) + goto invalid_operands; + + stat |= sim_fpu_add (&r, &m, &n); + stat |= ROUND (&r); + if (fpu_status_ok (stat)) + VAL2REG (&r, reg_out); + } + + fpu_check_signal_exception (sd, cpu, cia); +} + +/* Implement a 32/64 bit FP msub, setting FP exception bits when + appropriate. */ +void +fpu_fmsub (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, + const void *reg_in1, const void *reg_in2, const void *reg_in3, + void *reg_out, const struct fp_prec_t *ops) +{ + sim_fpu m1, m2, m, n, r; + + REG2VAL (reg_in1, &m1); + REG2VAL (reg_in2, &m2); + REG2VAL (reg_in3, &n); + ROUND (&m1); + ROUND (&m2); + ROUND (&n); + FPCR &= ~ EC_MASK; + if (sim_fpu_is_snan (&m1) || sim_fpu_is_snan (&m2) || sim_fpu_is_snan (&n) + || (sim_fpu_is_infinity (&m1) && sim_fpu_is_zero (&m2)) + || (sim_fpu_is_zero (&m1) && sim_fpu_is_infinity (&m2))) + { + invalid_operands: + if (FPCR & EE_V) + FPCR |= EC_V; + else + VAL2REG (&sim_fpu_qnan, reg_out); + } + else + { + sim_fpu_status stat = sim_fpu_mul (&m, &m1, &m2); + + if (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n) + && sim_fpu_sign (&m) == sim_fpu_sign (&n)) + goto invalid_operands; + + stat |= sim_fpu_sub (&r, &m, &n); + stat |= ROUND (&r); + if (fpu_status_ok (stat)) + VAL2REG (&r, reg_out); + } + + fpu_check_signal_exception (sd, cpu, cia); +} + +/* Implement a 32/64 bit FP nmadd, setting FP exception bits when + appropriate. */ +void +fpu_fnmadd (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, + const void *reg_in1, const void *reg_in2, const void *reg_in3, + void *reg_out, const struct fp_prec_t *ops) +{ + sim_fpu m1, m2, m, mm, n, r; + + REG2VAL (reg_in1, &m1); + REG2VAL (reg_in2, &m2); + REG2VAL (reg_in3, &n); + ROUND (&m1); + ROUND (&m2); + ROUND (&n); + FPCR &= ~ EC_MASK; + if (sim_fpu_is_snan (&m1) || sim_fpu_is_snan (&m2) || sim_fpu_is_snan (&n) + || (sim_fpu_is_infinity (&m1) && sim_fpu_is_zero (&m2)) + || (sim_fpu_is_zero (&m1) && sim_fpu_is_infinity (&m2))) + { + invalid_operands: + if (FPCR & EE_V) + FPCR |= EC_V; + else + VAL2REG (&sim_fpu_qnan, reg_out); + } + else + { + sim_fpu_status stat = sim_fpu_mul (&m, &m1, &m2); + + if (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n) + && sim_fpu_sign (&m) == sim_fpu_sign (&n)) + goto invalid_operands; + + stat |= sim_fpu_neg (&mm, &m); + stat |= sim_fpu_add (&r, &mm, &n); + stat |= ROUND (&r); + if (fpu_status_ok (stat)) + VAL2REG (&r, reg_out); + } + + fpu_check_signal_exception (sd, cpu, cia); +} + +/* Implement a 32/64 bit FP nmsub, setting FP exception bits when + appropriate. */ +void +fpu_fnmsub (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, + const void *reg_in1, const void *reg_in2, const void *reg_in3, + void *reg_out, const struct fp_prec_t *ops) +{ + sim_fpu m1, m2, m, mm, n, r; + + REG2VAL (reg_in1, &m1); + REG2VAL (reg_in2, &m2); + REG2VAL (reg_in3, &n); + ROUND (&m1); + ROUND (&m2); + ROUND (&n); + FPCR &= ~ EC_MASK; + if (sim_fpu_is_snan (&m1) || sim_fpu_is_snan (&m2) || sim_fpu_is_snan (&n) + || (sim_fpu_is_infinity (&m1) && sim_fpu_is_zero (&m2)) + || (sim_fpu_is_zero (&m1) && sim_fpu_is_infinity (&m2))) + { + invalid_operands: + if (FPCR & EE_V) + FPCR |= EC_V; + else + VAL2REG (&sim_fpu_qnan, reg_out); + } + else + { + sim_fpu_status stat = sim_fpu_mul (&m, &m1, &m2); + + if (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n) + && sim_fpu_sign (&m) != sim_fpu_sign (&n)) + goto invalid_operands; + + stat |= sim_fpu_neg (&mm, &m); + stat |= sim_fpu_sub (&r, &mm, &n); + stat |= ROUND (&r); + if (fpu_status_ok (stat)) + VAL2REG (&r, reg_out); + } + + fpu_check_signal_exception (sd, cpu, cia); +}