X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Frx%2FChangeLog;h=8718c258c7fc6581e0e4a70862bb26e556588c90;hb=9c082ca86eb4262078f359850ae4466856f156a1;hp=bb3b45153d4b62f77d9b7e18503611efae2161c9;hpb=feafbb2e30a44528263753647e5b412d9576876e;p=deliverable%2Fbinutils-gdb.git diff --git a/sim/rx/ChangeLog b/sim/rx/ChangeLog index bb3b45153d..8718c258c7 100644 --- a/sim/rx/ChangeLog +++ b/sim/rx/ChangeLog @@ -1,3 +1,155 @@ +2011-10-17 Mike Frysinger + + * configure.ac: Change include to common/acinclude.m4. + +2011-10-17 Mike Frysinger + + * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER + call. Replace common.m4 include with SIM_AC_COMMON. + * configure: Regenerate. + +2011-07-11 Mike Frysinger + + * configure.ac: Rename from configure.in. + +2011-07-11 Mike Frysinger + + * configure.in: Add "dnl" before copyright notice. + +2011-04-16 Mike Frysinger + + * gdb-if.c (sim_complete_command): New stub function. + +2011-01-11 Andrew Burgess + + * gdb-if.c (sim_store_register): Update return value to + match new API. + +2010-12-14 DJ Delorie + + * rx.c (decode_opcode): For "MVFC PC,", use the address of the + opcode, not the address following the opcode. + (decode_opcode): RXO_branchrel is relative to the opcode's PC, not + the address following the opcode. + +2010-11-11 DJ Delorie + + * rx.c (lsb_count): New. + (divu_cycles): New. + (div_cycles): New. + (decode_opcode): Fix cycle count math for div, divu, suntil, and + swhile. + +2010-09-29 Kevin Buettner + + * mem.c (rx_mem_ptr): When invalidating the decode cache, account + for the fact that the instruction decoder never uses swapped + addresses. + +2010-09-29 Nick Clifton + + * rx.c (decode_opcode: RXO_int): Only break out of the emulation + loop if rx_syscall() does not return a RX_STEPPED result. + +2010-09-23 Kevin Buettner + + * rx.c (decode_opcode): Add cycle information for RXO_smovu. + +2010-09-23 Kevin Buettner + + * fpu.c, gdb-if.c, load.c, misc.c, syscalls.c (config.h): Include. + + * rx.c (decode_opcode): Declare `tx' as unsigned. + + * cpu.h (reset_decoder): Declare. + * load.c (rx_load): Call `reset_decoder'. + * rx.c (reset_decoder): New function. + +2010-07-29 DJ Delorie + + * rx.c (decode_cache_base): New. + (id_names): Remove ediv and edivu. + (optype_names): Add TwoReg. + (maybe_get_mem_page): New. + (rx_get_byte): Call it. + (get_op): Add TwoReg support. + (put_op): Likewise. + (PD, PS, PS2, GD, GS, GS2, DSZ, SSZ, S2SZ, US1, US2, OM): "opcode" + is a pointer now. + (DO_RETURN): New. We use longjmp to return an exception result. + (decode_opcode): Make opcode a pointer to the decode cache. Save + decoded opcode information and re-use. Call DO_RETURN instead of + return throughout. Remove ediv and edivu. + * mem.c (ptdc): New. Adds decode cache. + (rx_mem_ptr): Support it. + (rx_mem_decode_cache): New. + * mem.h (enum mem_ptr_action): add MPA_DECODE_CACHE. + (rx_mem_decode_cache): Declare. + * gdb-if.c (sim_resume): Add decode_opcode's setjmp logic here... + * main.c (main): ...and here. Use a fast loop if neither trace + nor disassemble is given. + * cpu.h (RX_MAKE_STEPPED, RX_MAKE_HIT_BREAK, RX_MAKE_EXITED, + RX_MAKE_STOPPED, RX_EXITED, RX_STOPPED): Adjust so that 0 is not a + valid code for anything. + +2010-07-27 DJ Delorie + + * README.txt: New. + * config.h (CYCLE_ACCURATE, CYCLE_STATS): New. + * configure.in (--enable-cycle-accurate, --enable-cycle-stats): + New. Default to enabled. + * configure: Regenerate. + + * cpu.h (regs_type): Add cycle tracking info. + (reset_pipeline_stats): Declare. + (halt_pipeline_stats): Declare. + (pipeline_stats): Declare. + * main.c (done): Call pipeline_stats(). + * mem.h (rx_mem_ptr): Moved to here ... + * mem.c (mem_ptr): ... from here. Rename throughout. + (mem_put_byte): Move LEDs to Port A. Add Port B to control cycle + statistics. Move UART to SCI4. + (mem_put_hi): Add TPU 1-2. TPU 1 and 2 count CPU cycles. + * reg.c (init_regs): Set Rt reg to -1 (no reg). + * rx.c: Add cycle counting and statistics throughout. + (rx_get_byte): Optimize for speed. + (decode_opcode): Likewise. + (reset_pipeline_stats): New. + (halt_pipeline_stats): New. + (pipeline_stats): New. + * trace.c (sim_disasm_one): Print cycle count. + +2010-07-07 Kevin Buettner + + * gdb-if.c (sim_store_register): Add case for sim_rx_acc_regnum. + +2010-06-24 Kevin Buettner + + * gdb-if.c (trace.h): Include. + (reg_size, sim_fetch_register): Add cases for sim_rx_acc_regnum. + +2010-06-07 Nick Clifton + + * reg.c (set_oszc): Use unsigned int for the mask. + (set_szc, set_osz, set_sz): Likewise. + +2010-05-28 Kevin Buettner + + * gdb-if.c (sim_do_command): Add a "sim verbose noisy" command. + +2010-04-14 Mike Frysinger + + * gdb-if.c (sim_write): Add const to buf arg. + +2010-01-30 Masaki Muranaka + + * configure.in: Check if the host has getopt.h. + * configure: Regenerate. + * config.in: Regenerate. + * main.c: Include config.h. + Use HAVE_STDLIB_H, HAVE_UNISTD_H, HAVE_GETOPT_H. + Include getopt.h in case HAVE_GETOPT_H is defined. + 2009-12-22 Yoshinori Sato * rx/rx.c (decode_opcode): btst bit address mask fix.