X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fsh%2FChangeLog;h=2127ab8cfacadf8e935b71fe625b60f6f6f7f1b5;hb=00923338dec84505addaf9cdeca2e9c844757824;hp=62320a84a69371a01012e952c0eae1e99433007c;hpb=3c25f8c7b071182238e0833c72552ee0e72fd2ae;p=deliverable%2Fbinutils-gdb.git diff --git a/sim/sh/ChangeLog b/sim/sh/ChangeLog index 62320a84a6..2127ab8cfa 100644 --- a/sim/sh/ChangeLog +++ b/sim/sh/ChangeLog @@ -1,3 +1,522 @@ +2015-04-18 Mike Frysinger + + * sim-main.h (SIM_CPU): Delete. + +2015-04-18 Mike Frysinger + + * sim-main.h (sim_cia): Delete. + +2015-04-17 Mike Frysinger + + * sim-main.h (CIA_GET, CIA_SET): Delete. + +2015-04-17 Mike Frysinger + + * interp.c (sh_pc_get, sh_pc_set): New functions. + (sim_open): Call CPU_PC_FETCH & CPU_PC_STORE for all cpus. + +2015-04-15 Mike Frysinger + + * Makefile.in (SIM_OBJS): Delete sim-cpu.o. + * sim-main.h (STATE_CPU): Delete. + +2015-04-13 Mike Frysinger + + * configure: Regenerate. + +2015-04-06 Mike Frysinger + + * Makefile.in (SIM_OBJS): Delete sim-engine.o. + +2015-03-31 Mike Frysinger + + * config.in, configure: Regenerate. + +2015-03-28 Mike Frysinger + + * Makefile.in (SIM_RUN_OBJS, SIM_EXTRA_CFLAGS): Delete. + (SIM_OBJS): Change to $(SIM_NEW_COMMON_OBJS). + * interp.c: Delete run-sim.h include. Include sim-main.h, sim-base.h, + and sim-options.h. + (SEXT, SEXT32): Undefine. + (sim_write): Delete prototype. + (regstacktype, saved_state_type): Move to sim-main.h. + (target_little_endian): Replace with CURRENT_TARGET_BYTE_ORDER. + (host_little_endian): Replace with CURRENT_HOST_BYTE_ORDER. + (sim_kind, myname, tracing, sim_stop, sim_trace, sim_set_profile, + sim_set_profile_size, sim_load, sim_set_callbacks, + sim_complete_command): Delete. + (sim_size): Mark static. + (init_pointers): Delete host_little_endian setup. + (sim_resume): Delete tracing check. + (free_state): New cleanup function. + (sim_open): Rewrite to use new common logic. + (sim_create_inferior): Call init_dsp. + * sim-main.h: New file. + * tconfig.h: Delete file. + +2015-03-28 Mike Frysinger + + * gencode.c (ppi_gensim): Convert old style prototype with ppi_insn. + * interp.c: Include ctype.h and run-sim.h. + [HAVE_TIME_H]: Include time.h + [HAVE_SYS_TIME_H]: Include sys/time.h + [!_WIN32]: Include utime.h and sys/wait.h. + (set_fpscr1, raise_exception, raise_buserror, get_dr, set_dr, set_sr, + do_rdat, do_wdat, process_wlat_addr, process_wwat_addr, + process_wbat_addr, process_rlat_addr, process_rwat_addr, + process_rbat_addr, IOMEM, get_now, now_persec, swapout, swapout16, + ptr, strswaplen, strnswap, dmul, macw, macl, get_loop_bounds_ext, + get_loop_bounds, sim_size, init_dsp, init_pointers, dump_profile, + gotcall, sim_stop, sim_write, sim_read, sim_store_register, + sim_fetch_register, sim_trace, sim_stop_reason, sim_info, + sim_set_profile, sim_set_profile_size, sim_open, + parse_and_set_memory_size, sim_close, sim_load, sim_create_inferior, + sim_do_command, sim_set_callbacks): Convert old style prototype. + (fail): Delete unused function. + (wlat_fast, wwat_fast, wbat_fast, rlat_fast, rwat_fast, rbat_fast): + Delete unused prototypes. + (wlat_fast, wwat_fast, wbat_fast, rlat_fast, rwat_fast, rbat_fast, + swap, swap16): + Convert old style prototype and move INLINE before the type. + (trap): Convert old style prototype. Add casts to wait and sim_write + calls. + (div1): Convert old style prototype. Change return to void. + (do_long_move_insn, do_blog_insn, fsca_s, fsrra_s, mcalloc): Mark + static. + (sim_resume): Convert old style prototype. Align printf format and + args. + +2015-03-28 Mike Frysinger + + * gencode.c (ppi_gensim): Add missing */. Change case 4 to case 5. + +2015-03-28 Mike Frysinger + + * Makefile.in (gencode): Add $(BUILD_CFLAGS), $(BUILD_LDFLAGS), + and $(WARN_CFLAGS). + * gencode.c: Include ctype.h, stdlib.h, string.h, and unistd.h. + (struct op): Mark members const. + (tab): Mark static. + (nibble_type_list): Mark const. + (arg_type_list): Mark const. + (make_enum_list): Delete unused func. + (qfunc, expand_opcode, dumptable, expand_ppi_code): Convert old + style prototype and mark args const. + (sorttab, gengastab, conflict_warn, filltable, expand_ppi_movxy, + gensim, ppi_filltable): Convert old style prototype. + (gensim_caselist): Convert old style prototype. Mark local + variables s and r const. + (gendefines): Convert old style prototype. Mark s const. Move + tolower call into printf statement. + (ppi_gensim): Convert old style prototype. Mark local variable + s const. + (main): Convert old style prototype. Change printf %d to %zu. + +2015-03-28 Mike Frysinger + + * config.in, configure: Regenerate. + * configure.ac: Call SIM_AC_OPTION_ENDIAN, SIM_AC_OPTION_ALIGNMENT, + SIM_AC_OPTION_HOSTENDIAN, SIM_AC_OPTION_ENVIRONMENT, + SIM_AC_OPTION_INLINE, SIM_AC_OPTION_WARNINGS. + +2015-03-16 Mike Frysinger + + * config.in, configure: Regenerate. + * tconfig.in: Rename file ... + * tconfig.h: ... here. + +2015-03-14 Mike Frysinger + + * Makefile.in (SIM_EXTRA_CFLAGS): Set to + -DSIM_USE_DEPRECATED_RUN_FRONTEND. + (SIM_RUN_OBJS): Set to run.o. + +2015-03-14 Mike Frysinger + + * configure.ac (AC_CHECK_HEADERS): Delete. + * aclocal.m4, configure: Regenerate. + +2014-10-14 Oleg Endo (tiny patch) + + * gencode.c (fabs, fneg): Implement as integer operation + instead of using the FP_UNARY macro. + +2014-08-19 Alan Modra + + * configure: Regenerate. + +2014-08-15 Roland McGrath + + * configure: Regenerate. + * config.in: Regenerate. + +2014-03-10 Mike Frysinger + + * interp.c (parse_and_set_memory_size): Add const to str. + (sim_do_command): Add const to cmd and sms_cmd. + +2014-03-05 Mike Frysinger + + * interp.c (sim_load): Add const to prog. + +2014-02-17 Mike Frysinger + + PR gdb/16450 + * interp.c (control_c): Delete. + (sim_resume): Delete signal(SIGINT) handling. + +2013-09-23 Alan Modra + + * configure: Regenerate. + +2013-06-03 Mike Frysinger + + * aclocal.m4, configure: Regenerate. + +2012-06-15 Joel Brobecker + + * config.in, configure: Regenerate. + +2012-03-24 Mike Frysinger + + * aclocal.m4, config.in, configure: Regenerate. + +2012-02-16 Kevin Buettner + + * interp.c (MA): Adjust cast to avoid warning on 64-bit hosts. + + * interp.c (sim_store_register, sim_fetch_register): Return + length, not -1. + +2011-12-03 Mike Frysinger + + * aclocal.m4: New file. + * configure: Regenerate. + +2011-10-17 Mike Frysinger + + * configure.ac: Change include to common/acinclude.m4. + +2011-10-17 Mike Frysinger + + * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER + call. Replace common.m4 include with SIM_AC_COMMON. + * configure: Regenerate. + +2011-04-16 Mike Frysinger + + * interp.c (sim_complete_command): New stub function. + +2010-04-14 Mike Frysinger + + * interp.c (sim_write): Add const to buffer arg. + +2010-01-12 Masaki Muranaka + + * interp.c: Don't include sysdep.h. + Include stdio.h and errno.h. + Include string.h strings.h stdlib.h sys/stat.h if present. + +2010-01-09 Ralf Wildenhues + + * configure: Regenerate. + +2009-08-22 Ralf Wildenhues + + * config.in: Regenerate. + * configure: Likewise. + + * configure: Regenerate. + +2008-07-11 Hans-Peter Nilsson + + * configure: Regenerate to track ../common/common.m4 changes. + * config.in: Ditto. + +2008-06-06 Vladimir Prus + Daniel Jacobowitz + Joseph Myers + + * configure: Regenerate. + +2008-02-04 Antony King + + * interp.c (macl): Fix non-portable implementation. + +2007-10-08 Andrew Stubbs + + * gencode.c (tab): Add RAISE_EXCEPTION_IF_IN_DELAY_SLOT to the + definition of PC relative 'mov.l'/'mov.w' and also 'mova'. + +2007-03-02 Andrew Stubbs + + * gencode.c (tab): Correct pre-decrement instructions when m == n. + +2006-12-21 Hans-Peter Nilsson + + * acconfig.h: Remove. + * config.in: Regenerate. + +2006-06-13 Richard Earnshaw + + * configure: Regenerated. + +2006-06-05 Daniel Jacobowitz + + * configure: Regenerated. + +2006-05-31 Daniel Jacobowitz + + * configure: Regenerated. + +2005-11-10 Andrew Stubbs + + * interp.c (sim_memory_size): Use same amount of memory on Windows as + elsewhere. + +2005-09-19 J"orn Rennecke + + * interp.c (): Include. + (mcalloc): New function / macro. + (mfree): New macro. + (sim_size): Use mcalloc and mfree. + +2005-08-02 J"orn Rennecke + + * interp.c (strswaplen): Add one for '\0' delimiter. + +2005-06-16 Daniel Jacobowitz + + * gencode.c (tab): Avoid lvalue casts. Suggested by + Ralf Corsepius . + +2005-04-12 Jonathan Larmour + + * gencode.c (tab): Avoid inserting code before variables all declared. + +2005-03-23 Mark Kettenis + + * configure: Regenerate. + +2005-01-14 Andrew Cagney + + * configure.ac: Sinclude aclocal.m4 before common.m4. Add + explicit call to AC_CONFIG_HEADER. + * configure: Regenerate. + +2005-01-12 Andrew Cagney + + * configure.ac: Update to use ../common/common.m4. + * configure: Re-generate. + +2005-01-11 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +2005-01-07 Andrew Cagney + + * configure.ac: Rename configure.in, require autoconf 2.59. + * configure: Re-generate. + +2004-12-08 Hans-Peter Nilsson + + * configure: Regenerate for ../common/aclocal.m4 update. + +2004-09-08 DJ Delorie + + Commited by Corinna Vinschen + * gencode.c (movua.l): Compensate for endianness. + +2004-09-08 Corinna Vinschen + + * interp.c (RAISE_EXCEPTION_IF_IN_DELAY_SLOT): New macro. + (in_delay_slot): New flag variable. + (Delay_Slot): Set in_delay_slot. + (sim_resume): Reset in_delay_slot after leaving code switch. + * gencode.c (op tab): Call RAISE_EXCEPTION_IF_IN_DELAY_SLOT for all + instructions not allowed in delay slots. + +2004-09-08 Michael Snyder + + Commited by Corinna Vinschen + Introduce SH2a support. + * interp.c: Change type of jump table to short. Add various macros. + (sim_load): Save the bfd machine code. + (sim_create_inferior): Ditto. + (union saved_state_type): Add tbr, ibnr and ibcr registers. + Move bfd_mach to end of struct. Add regstack pointer. + (init_dsp): Don't swap contents of sh_dsp_table any more. Instead + use it directly in its own switch statement. Allocate space for 512 + register banks. + (do_long_move_insn): New function. + (do_blog_insn): Ditto. + (trap): Use trap #13 and trap #14 to set ibnr and ibcr. + * gencode.c: Move movx/movy insns into separate switch statement. + (op tab): Add sh2a insns. Reject instructions that are disabled + on that chip. + (gensim_caselist): Generate default case here instead of in caller. + (gensim): Generate two separate switch statements. Call + gensim_caselist once for each (for movsxy_tab and for tab). + Add tokens for r15 and multiple regs. + (conflict_warn, warn_conflicts): Add for debugging. + +2004-08-18 J"orn Rennecke + + * gencode.c (tab): For shad snd shld, fix result for + (op1 < 0 && shift_amount == 0). + +2004-02-02 Michael Snyder + + * gencode.c (movua.l): Set thislock to 0, not n. + +2004-02-12 Michael Snyder + + * gencode.c (table): Change from char to short. + (dumptable): Change generated table from char to short. + * interp.c (sh_jump_table, sh_dsp_table, ppi_table): char to short. + (init_dsp): Compute size of sh_dsp_table. + (sim_resume): Change jump_table from char to short. + +2004-01-27 Michael Snyder + + * gencode.c: (op tab): Some refs and defs fixes. + "fsrra" -> "fsrra ". + "sleep": replace array ref with array addr. + "trapa": ditto. + Comment and whitespace clean-ups. + +2004-01-07 Michael Snyder + + * gencode.c: Whitespace cleanup. + * interp.c: Ditto. + + * gencode.c: Replace 'Hitachi' with 'Renesas'. + (op tab): Add new instructions for sh4a, DBR, SBR. + (expand_opcode): Add handling for new movxy combinations. + (gensym_caselist): Ditto. + (expand_ppi_movxy): Remove movx/movy expansions, + now handled in expand_opcode. + (gensym): Add some helpful macros. + (expand_ppi_code): Flatten loop for simplicity, tweak for 12-bit + instead of 8-bit table (some insns are ambiguous to 8 bits). + (ppi_gensim, main): Generate 12-bit instead of 8-bit ppi table. + + * interp.c: Replace 'Hitachi' with 'Renesas'. + (union saved_state_type): Add dbr, sgr, ldst. + (get_loop_bounds_ext): New function. + (init_dsp): Add bfd_mach_sh4al_dsp. + (sim_resume): Handle extended loop bounds. + +2003-12-18 Michael Snyder + + * gencode.c (expand_opcode): Simplify and reorganize. + Eliminate "shift" parameter. Eliminate "4 bits at a time" + assumption. Flatten switch statement to a single level. + Add "eeee" token for even-numbered registers. + (bton): Delete. + (fsca): Use "eeee" token. + (ppi_moves): Rename to "expand_ppi_movxy". Do the ddt + [movx/movy] expansion here, as well as the ppi expansion. + (gensim_caselist): Accept 'eeee' along with 'nnnn'. + +2003-11-03 J"orn Rennecke + + * interp.c (fsca_s, fsrra_s): New functions. + * gencode.c (tab): Add entries for fsca and fsrra. + (expand_opcode): Allow variable length n / m fields. + +2003-10-15 J"orn Rennecke + + * syscall.h (SYS_truncate, SYS_ftruncate): Define. + * interp.c (trap): Add support for SYS_ftruncate and SYS_truncate. + +2003-08-11 Shrinivas Atre + * sim/sh/gencode.c ( tab[] ): Addition of MAC.L handler and + correction for MAC.W handler + * sim/sh/interp.c ( macl ): New Function. Implementation of + MAC.L handler. + +2003-08-07 Michael Snyder + + * gencode.c (expand_ppi_code): Comment spelling fix. + +2003-07-25 Michael Snyder + + * gencode.c (pshl): Change < to <= (shift by 16 is allowed). + Cast argument of >> to unsigned to prevent sign extension. + (psha): Change < to <= (shift by 32 is allowed). + +2003-07-24 Michael Snyder + + * gencode.c: Fix typo in comment. + +2003-07-23 Michael Snyder + + * gencode.c: A few more fix-ups of refs and defs. + (frchg): Raise SIGILL if in double-precision mode. + (ldtlb): We don't simulate cache, so this is a no-op. + (movsxy_tab): Correct a few bit pattern errors. + +2003-07-09 Michael Snyder + + * gencode.c (prnd): Clear LSW of result to zeros. + * gencode.c (pmuls): Expression is mis-parenthesized. + * gencode.c (ppi_gensim): For a conditional ppi insn, if the + condition is false, we want to return (not break). A break + will take us to the end of the function where registers will + be updated, whereas the desired outcome is for nothing to change. + +2003-07-03 Michael Snyder + + * gencode.c (movs): Fix a couple of text transpositions. + +2003-06-27 Michael Snyder + + * gencode.c (op tab): Some fix-ups of refs and defs. + (ocbi, ocbp): Cache not simulated, but may cause memory fault. + (gensym_caselist): Add default case to switch statement. + (expand_ppi_code): Add default case to switch statement. + * gencode.c (op tab): Implement movca.l. + * gencode.c (op movsxy_tab): Fix an error in the bit pattern. + * gencode.c (gensim_caselist): The movy instructions use + registers R6 and R7 (not R4 and R5 like the movx insns). + +2003-06-27 Michael Snyder + + * gencode.c (op movsxy_tab): Fix up some copy/paste errors + in name: s/REG_x/REG_y/. + + * gencode.c (op tab): Move misplaced semicolon. + +2003-02-27 Andrew Cagney + + * interp.c (init_dsp, sim_open, sim_create_inferior): Rename _bfd + to bfd. + +Fri Oct 11 16:22:28 2002 J"orn Rennecke + + * interp.c (trap): Return int. Take extra parameter for address + of the trap instruction. Changed all callers. + Add case 33 for profiling. + * gencode.c (trapa): Handle trap 33 using the trap function. + Add read of vector for generic traps. + +Wed Jul 17 19:36:38 2002 J"orn Rennecke + + * Makefile.in (interp.o): Depend on $(srcroot)/include/gdb/sim-sh.h. + * interp.c: Include "gdb/sim-sh.h". + (sim_store_register, sim_fetch_register): Use constants defined there. + +Tue Jun 18 16:53:11 2002 J"orn Rennecke + + * interp.c (sim_resume): Fix setting of bus error for + instruction fetch. + +2002-06-16 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + 2002-06-08 Andrew Cagney * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h". @@ -679,7 +1198,7 @@ Thu Sep 14 19:32:59 1995 Stu Grossman (grossman@cygnus.com) * gencode.c: Back up PC by 2 for breakpoints. * interp.c: Move fp regs beyond pc/pr/etc to avoid confusing GDB, - which expect pc to immediatly follow regs[]. + which expect pc to immediately follow regs[]. Fri Sep 8 14:18:13 1995 Ian Lance Taylor