X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fsh%2FChangeLog;h=bb57ca1e312af5f2eff5600d02d88ca6f8de779c;hb=bf3d9781ec049aef88547a9be711df2c1291c898;hp=3a7cc82cca6fa490eef2b86d68ecc83899d0c83f;hpb=72ec28b8afa357cdde70c612b4e0e9f37a34f8e4;p=deliverable%2Fbinutils-gdb.git diff --git a/sim/sh/ChangeLog b/sim/sh/ChangeLog index 3a7cc82cca..bb57ca1e31 100644 --- a/sim/sh/ChangeLog +++ b/sim/sh/ChangeLog @@ -1,3 +1,531 @@ +2013-09-23 Alan Modra + + * configure: Regenerate. + +2013-06-03 Mike Frysinger + + * aclocal.m4, configure: Regenerate. + +2012-06-15 Joel Brobecker + + * config.in, configure: Regenerate. + +2012-03-24 Mike Frysinger + + * aclocal.m4, config.in, configure: Regenerate. + +2012-02-16 Kevin Buettner + + * interp.c (MA): Adjust cast to avoid warning on 64-bit hosts. + + * interp.c (sim_store_register, sim_fetch_register): Return + length, not -1. + +2011-12-03 Mike Frysinger + + * aclocal.m4: New file. + * configure: Regenerate. + +2011-10-17 Mike Frysinger + + * configure.ac: Change include to common/acinclude.m4. + +2011-10-17 Mike Frysinger + + * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER + call. Replace common.m4 include with SIM_AC_COMMON. + * configure: Regenerate. + +2011-04-16 Mike Frysinger + + * interp.c (sim_complete_command): New stub function. + +2010-04-14 Mike Frysinger + + * interp.c (sim_write): Add const to buffer arg. + +2010-01-12 Masaki Muranaka + + * interp.c: Don't include sysdep.h. + Include stdio.h and errno.h. + Include string.h strings.h stdlib.h sys/stat.h if present. + +2010-01-09 Ralf Wildenhues + + * configure: Regenerate. + +2009-08-22 Ralf Wildenhues + + * config.in: Regenerate. + * configure: Likewise. + + * configure: Regenerate. + +2008-07-11 Hans-Peter Nilsson + + * configure: Regenerate to track ../common/common.m4 changes. + * config.in: Ditto. + +2008-06-06 Vladimir Prus + Daniel Jacobowitz + Joseph Myers + + * configure: Regenerate. + +2008-02-04 Antony King + + * interp.c (macl): Fix non-portable implementation. + +2007-10-08 Andrew Stubbs + + * gencode.c (tab): Add RAISE_EXCEPTION_IF_IN_DELAY_SLOT to the + definition of PC relative 'mov.l'/'mov.w' and also 'mova'. + +2007-03-02 Andrew Stubbs + + * gencode.c (tab): Correct pre-decrement instructions when m == n. + +2006-12-21 Hans-Peter Nilsson + + * acconfig.h: Remove. + * config.in: Regenerate. + +2006-06-13 Richard Earnshaw + + * configure: Regenerated. + +2006-06-05 Daniel Jacobowitz + + * configure: Regenerated. + +2006-05-31 Daniel Jacobowitz + + * configure: Regenerated. + +2005-11-10 Andrew Stubbs + + * interp.c (sim_memory_size): Use same amount of memory on Windows as + elsewhere. + +2005-09-19 J"orn Rennecke + + * interp.c (): Include. + (mcalloc): New function / macro. + (mfree): New macro. + (sim_size): Use mcalloc and mfree. + +2005-08-02 J"orn Rennecke + + * interp.c (strswaplen): Add one for '\0' delimiter. + +2005-06-16 Daniel Jacobowitz + + * gencode.c (tab): Avoid lvalue casts. Suggested by + Ralf Corsepius . + +2005-04-12 Jonathan Larmour + + * gencode.c (tab): Avoid inserting code before variables all declared. + +2005-03-23 Mark Kettenis + + * configure: Regenerate. + +2005-01-14 Andrew Cagney + + * configure.ac: Sinclude aclocal.m4 before common.m4. Add + explicit call to AC_CONFIG_HEADER. + * configure: Regenerate. + +2005-01-12 Andrew Cagney + + * configure.ac: Update to use ../common/common.m4. + * configure: Re-generate. + +2005-01-11 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +2005-01-07 Andrew Cagney + + * configure.ac: Rename configure.in, require autoconf 2.59. + * configure: Re-generate. + +2004-12-08 Hans-Peter Nilsson + + * configure: Regenerate for ../common/aclocal.m4 update. + +2004-09-08 DJ Delorie + + Commited by Corinna Vinschen + * gencode.c (movua.l): Compensate for endianness. + +2004-09-08 Corinna Vinschen + + * interp.c (RAISE_EXCEPTION_IF_IN_DELAY_SLOT): New macro. + (in_delay_slot): New flag variable. + (Delay_Slot): Set in_delay_slot. + (sim_resume): Reset in_delay_slot after leaving code switch. + * gencode.c (op tab): Call RAISE_EXCEPTION_IF_IN_DELAY_SLOT for all + instructions not allowed in delay slots. + +2004-09-08 Michael Snyder + + Commited by Corinna Vinschen + Introduce SH2a support. + * interp.c: Change type of jump table to short. Add various macros. + (sim_load): Save the bfd machine code. + (sim_create_inferior): Ditto. + (union saved_state_type): Add tbr, ibnr and ibcr registers. + Move bfd_mach to end of struct. Add regstack pointer. + (init_dsp): Don't swap contents of sh_dsp_table any more. Instead + use it directly in its own switch statement. Allocate space for 512 + register banks. + (do_long_move_insn): New function. + (do_blog_insn): Ditto. + (trap): Use trap #13 and trap #14 to set ibnr and ibcr. + * gencode.c: Move movx/movy insns into separate switch statement. + (op tab): Add sh2a insns. Reject instructions that are disabled + on that chip. + (gensim_caselist): Generate default case here instead of in caller. + (gensim): Generate two separate switch statements. Call + gensim_caselist once for each (for movsxy_tab and for tab). + Add tokens for r15 and multiple regs. + (conflict_warn, warn_conflicts): Add for debugging. + +2004-08-18 J"orn Rennecke + + * gencode.c (tab): For shad snd shld, fix result for + (op1 < 0 && shift_amount == 0). + +2004-02-02 Michael Snyder + + * gencode.c (movua.l): Set thislock to 0, not n. + +2004-02-12 Michael Snyder + + * gencode.c (table): Change from char to short. + (dumptable): Change generated table from char to short. + * interp.c (sh_jump_table, sh_dsp_table, ppi_table): char to short. + (init_dsp): Compute size of sh_dsp_table. + (sim_resume): Change jump_table from char to short. + +2004-01-27 Michael Snyder + + * gencode.c: (op tab): Some refs and defs fixes. + "fsrra" -> "fsrra ". + "sleep": replace array ref with array addr. + "trapa": ditto. + Comment and whitespace clean-ups. + +2004-01-07 Michael Snyder + + * gencode.c: Whitespace cleanup. + * interp.c: Ditto. + + * gencode.c: Replace 'Hitachi' with 'Renesas'. + (op tab): Add new instructions for sh4a, DBR, SBR. + (expand_opcode): Add handling for new movxy combinations. + (gensym_caselist): Ditto. + (expand_ppi_movxy): Remove movx/movy expansions, + now handled in expand_opcode. + (gensym): Add some helpful macros. + (expand_ppi_code): Flatten loop for simplicity, tweak for 12-bit + instead of 8-bit table (some insns are ambiguous to 8 bits). + (ppi_gensim, main): Generate 12-bit instead of 8-bit ppi table. + + * interp.c: Replace 'Hitachi' with 'Renesas'. + (union saved_state_type): Add dbr, sgr, ldst. + (get_loop_bounds_ext): New function. + (init_dsp): Add bfd_mach_sh4al_dsp. + (sim_resume): Handle extended loop bounds. + +2003-12-18 Michael Snyder + + * gencode.c (expand_opcode): Simplify and reorganize. + Eliminate "shift" parameter. Eliminate "4 bits at a time" + assumption. Flatten switch statement to a single level. + Add "eeee" token for even-numbered registers. + (bton): Delete. + (fsca): Use "eeee" token. + (ppi_moves): Rename to "expand_ppi_movxy". Do the ddt + [movx/movy] expansion here, as well as the ppi expansion. + (gensim_caselist): Accept 'eeee' along with 'nnnn'. + +2003-11-03 J"orn Rennecke + + * interp.c (fsca_s, fsrra_s): New functions. + * gencode.c (tab): Add entries for fsca and fsrra. + (expand_opcode): Allow variable length n / m fields. + +2003-10-15 J"orn Rennecke + + * syscall.h (SYS_truncate, SYS_ftruncate): Define. + * interp.c (trap): Add support for SYS_ftruncate and SYS_truncate. + +2003-08-11 Shrinivas Atre + * sim/sh/gencode.c ( tab[] ): Addition of MAC.L handler and + correction for MAC.W handler + * sim/sh/interp.c ( macl ): New Function. Implementation of + MAC.L handler. + +2003-08-07 Michael Snyder + + * gencode.c (expand_ppi_code): Comment spelling fix. + +2003-07-25 Michael Snyder + + * gencode.c (pshl): Change < to <= (shift by 16 is allowed). + Cast argument of >> to unsigned to prevent sign extension. + (psha): Change < to <= (shift by 32 is allowed). + +2003-07-24 Michael Snyder + + * gencode.c: Fix typo in comment. + +2003-07-23 Michael Snyder + + * gencode.c: A few more fix-ups of refs and defs. + (frchg): Raise SIGILL if in double-precision mode. + (ldtlb): We don't simulate cache, so this is a no-op. + (movsxy_tab): Correct a few bit pattern errors. + +2003-07-09 Michael Snyder + + * gencode.c (prnd): Clear LSW of result to zeros. + * gencode.c (pmuls): Expression is mis-parenthesized. + * gencode.c (ppi_gensim): For a conditional ppi insn, if the + condition is false, we want to return (not break). A break + will take us to the end of the function where registers will + be updated, whereas the desired outcome is for nothing to change. + +2003-07-03 Michael Snyder + + * gencode.c (movs): Fix a couple of text transpositions. + +2003-06-27 Michael Snyder + + * gencode.c (op tab): Some fix-ups of refs and defs. + (ocbi, ocbp): Cache not simulated, but may cause memory fault. + (gensym_caselist): Add default case to switch statement. + (expand_ppi_code): Add default case to switch statement. + * gencode.c (op tab): Implement movca.l. + * gencode.c (op movsxy_tab): Fix an error in the bit pattern. + * gencode.c (gensim_caselist): The movy instructions use + registers R6 and R7 (not R4 and R5 like the movx insns). + +2003-06-27 Michael Snyder + + * gencode.c (op movsxy_tab): Fix up some copy/paste errors + in name: s/REG_x/REG_y/. + + * gencode.c (op tab): Move misplaced semicolon. + +2003-02-27 Andrew Cagney + + * interp.c (init_dsp, sim_open, sim_create_inferior): Rename _bfd + to bfd. + +Fri Oct 11 16:22:28 2002 J"orn Rennecke + + * interp.c (trap): Return int. Take extra parameter for address + of the trap instruction. Changed all callers. + Add case 33 for profiling. + * gencode.c (trapa): Handle trap 33 using the trap function. + Add read of vector for generic traps. + +Wed Jul 17 19:36:38 2002 J"orn Rennecke + + * Makefile.in (interp.o): Depend on $(srcroot)/include/gdb/sim-sh.h. + * interp.c: Include "gdb/sim-sh.h". + (sim_store_register, sim_fetch_register): Use constants defined there. + +Tue Jun 18 16:53:11 2002 J"orn Rennecke + + * interp.c (sim_resume): Fix setting of bus error for + instruction fetch. + +2002-06-16 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +2002-06-08 Andrew Cagney + + * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h". + +2001-01-30 Ben Elliston + + * interp.c (sim_create_inferior): Record program arguments for + later inspection by the trap handler. + (count_argc): New function. + (prog_argv): Declare static. + (sim_write): Declare. + (trap): Implement argc, argnlen and argn system calls. Do not + abort on unknown system calls--simply return -1. + * syscall.h (SYS_argc, SYS_argnlen, SYS_argn): Define. + +2001-01-24 Alexandre Oliva + + * interp.c (trap): Implement time. + +2000-10-24 Ben Elliston + + * gencode.c (tab): Delimit strings with commas where applicable. + +Tue May 23 21:39:23 2000 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon May 15 22:04:51 2000 J"orn Rennecke + +sh-dsp support, simulator speedup by using host byte order: + + * Makefile.in (interp.o): Depends on ppi.c . + (ppi.c): New rule. + * gencode.c (printonmatch, think, genopc): Deleted. + (MAX_NR_STUFF): Now 42. + (tab): Add SH-DSP CPU instructions. + Amalgamate ldc / stc / lds / sts instructions with similar + bit patterns. Fix opcodes of stc Rm_BANK,@-. + Fix semantics of lds.l @+,MACH (no sign extend). + (movsxy_tab): New array. + For movs, change MMMM field to GGGG, and mmmm field to MMMM. + Added entries for movx, movy and parallel processing insns. + (ppi_tab): New array. + (qfunc): Stabilize sort. + (expand_opcode): Handle [01][01]NN, [01][01]xx and [01][01]yy. + Handle 'M', 'G' 's' 'X', 'a', 'Y' and 'A'. + (dumptable): Now takes three arguments. Changed all callers. + Emit just one contigous jump table. + (filltable): Now takes an argument. Changed all callers. + Make index static. + (ppi_moves, expand_ppi_code, ppi_filltable, ppi_gensim): New functions. + (gensim_caselist): New function, broken out of gensim. + Handle opcode fields 'x', 'y', 's', 'M', 'G', 'X', 'a', and 'Y'. + Handle ref '9'. + (gensim): Handle 'N' in code field and '8' in refs field. + Call gensim_caselist - twice. + (ppi_index): New static variable. + (main): Unsupport default action. + Add dsp support for -x / -s option. Add -p option. + * interp.c (sh_jump_table, sh_dsp_table, ppi_table): Declare. + (saved_state_type): Rearrange to allow amalgamated ldc / stc / + lds / sts to work efficiently. + (target_dsp): New static variable. + (GBR, VBR, SSR, SPC, MACH, MACL): Reflect saved_state_type change. + (FPUL, Rn_BANK, SET_Rn_BANK, M, Q, S, T, SR_BL, SR_RB): Likewise. + (SR_MD, SR_RC, SET_SR_BIT, GET_SR, SET_RC, GET_FPSCR): Likewise. + (RS, RE, MOD, MOD_ME, DSP_R): Likewise. + (set_fpscr1): Likewise. Use target_dsp to check for dsp. + (MOD_MSi, SIG_BUS_FETCH): Deleted. + (CREG, SREG, PR, SR_MASK_DMY, SR_MASK_DMX, SR_DMY): New macros. + (SR_DMX, DSR, MOD_DELTA, GET_DSP_GRD): Likewise. + (SET_MOD): Reflect saved_state_type change. Set MOD_DELTA instead + of MOD_MS, and encode SR_DMY / SR_DMX into high word of MOD_ME. + (set_sr): Reflect saved_state_type change. Fix SR_RB handling. + Use SET_MOD. + (MA, L, TL, TB): Now controlled by ACE_FAST. + (SEXT32): Just cast to int. + (SIGN32): Fixed to only shift by 31. + (CHECK_INSN_PTR): SIGBUS at insn fetch now represented by insn_end 0. + (ppi_insn): Declare. + (ppi.c): Include. + (init_dsp): Set target_dsp. When it changes, switch end of + sh_jump_table with sh_dsp_table. + (sim_resume) Don't declare sh_jump_table0. Use sh_jump_table instead. + Don't Declare PR if it's #defined. + Fix single-stepping (Was broken in Mar 6 16:59:10 patch). + (sim_store_register, sim_read_register): Translate accesses to + reflect saved_state_type change. + + * interp.c (set_sr): Set sr. + (SET_RC, MOD, MOD_MS, MOD_ME, SET_MOD, MOD_MS, MOD_ME): New macros. + (set_fpscr1): Don't bank-switch fpu registers when simulating sh-dsp. + (DSP_R): Fix definition. + (sim_resume): Remove outdated SET_SR use. + + * interp.c (saved_state): New members for struct member asregs: + rs, re, insn_end, xram_start, yram_start. + (struct loop_bounds): New struct. + (SKIP_INSN): New macro. + (get_loop_bounds): New function. + (endianw): Renamed to global_endianw. + (maskw): negated bits. + (PC): Now insn_ptr. + (SR_MASK_RC, SR_RC_INCREMENT, SR_RC, RAISE_EXCEPTION): New macros. + (RS, RE, DSP_R, DSP_GRD, A1, A0, X0, X1, Y0, Y1, M0, A1G): Likewise. + (M1, A0G, RIAT, PT2H, PH2T, SET_NIP, CHECK_INSN_PTR): Likewise. + (SIG_BUS_FETCH): Likewise + (raise_exception, riat_fast): New functions. + (raise_buserror, sim_stop): Use raise_exception. + (PROCESS_SPECIAL_ADDRESS): Use xram_start / yram_start. + (BUSERROR, WRITE_BUSERROR, READ_BUSERROR): + Reverse sense of mask argument. + (FP_OP, set_dr): Use RAISE_EXCEPTION. + (wlat_fast, wwat_fast, wbat_fast, rlat_fast, rwat_fast, rbat_fast): + Declare. Remove redundant masking. + (wwat_fast, rwat_fast): Add argument endianw. Changed callers. + (MA): Updated for change pc -> PC. + (Delay_Slot): Use RIAT. + (empty): Deleted. + (trap): Remove argument little_endian. Add argument endianw. + Changed all callers. Use raise_exception. + (macw): Add argument endainw. Changed all callers. + (init_dsp): New function, extended after broken out of init_pointers. + (sim_resume): Replace pc with insn_ptr. Replace little_endian with + endianw. Replace nia with nip. Reverse sense of maskb / maskw / + maskl. Implement logic for zero-overhead loops. Don't try to + interpret garbage when getting a SIGBUS at insn fetch. + (sim_open): Call init_dsp. + * gencode.c (tab): Use SET_NIP instead of nia = . Use PH2T / PT2H / + RAISE_EXCEPTION where appropriate. + Add extra cycles for brai, braf , bsr, bsrf, jmp, jsr. + + * interp.c (sim_store_register, sim_fetch_register): + Do proper endianness switch. + + * interp.c (saved_state_type): New members for struct member asregs: + xymem_select, xmem, ymem, xmem_offset, ymem_offset. + (special_address): Delete. + (BUSERROR): Now a two-argument predicate. + (PROCESS_SPECIAL_ADDRESS, WRITE_BUSERROR, READ_BUSERROR): New macros. + (wlat_little, wwat_little, wbat_any, wlat_big, wwat_big): Delete. + (process_wlat_addr, process_wwat_addr): New functions. + (process_wbat_addr, process_rlat_addr, process_rwat_addr): Likewise. + (process_rbat_addr): Likewise. + (wlat_fast, wwat_fast, wbat_fast): Use WRITE_BUSERROR. + (rlat_little, rwat_little, rbat_any, rlat_big, rwat_big): Delete. + (rlat_fast, rwat_fast, rbat_fast): Use READ_BUSERROR. + (RWAT, RLAT, RBAT, WWAT, WLAT, WBAT): Delete SLOW versions. + (do_rdat, trap): Delete SLOW code. + (SEXT32, SIGN32): New macros. + (swap, swap16): Now integer in - integer out. Changed all callers. + (strswaplen, strnswap): Delete SLOW versions. + (init_pointers): Initialize dsp memory selection (preliminary). + (sim_store_register, sim_fetch_register): Use swap instead of + big / little endian read / write functions. + + * interp.c (maskl): Deleted. + (endianw, endianb): New variables. + (special_address): Now inline. + (bp_holder): Put raising of buserror there, rename to: + (raise_buserror). + (BUSERROR): Now yields a value. Changed all users. + (wbat_big): Delete. + (wlat_fast, wwat_fast, wbat_fast): New functions. + (rlat_fast, rwat_fast, rbat_fast): Likewise. + (RWAT, RLAT, RBAT, WWAT, WLAT, WBAT): Use new functions. + (do_rdat, do_wdat): Likewise. Take maskl argument instead of + little_endian one. Changed caller macros. + (swap, swap16): Use w[rw]lat_big / w[rw]lat_little directly. + (strswaplen, strnswap): New functions. + (trap): Use them to fix up endian mismatches; + disable SYS_execve and SYS_execv; fix double address translation for + SYS_pipe and SYS_stat. + (sym_write, sym_read): Add endianness translation. + (sym_store_register, sym_fetch_register): Add maskl local variable. + (sim_open): Set endianw and endianb. + Thu Sep 2 18:15:53 1999 Andrew Cagney * configure: Regenerated to track ../common/aclocal.m4 changes.