X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fsh64%2Fcpu.h;h=c2a14e46362439da346d4cf17dc14b3e56e3ca31;hb=a78a19b15254de31c3d38b7e27469aaef0a30e97;hp=a5d6f34b64b2af9d1aa4b5e78493e7eb22d17293;hpb=c7e628df2ea65e93345a60bab86af1428213f94d;p=deliverable%2Fbinutils-gdb.git

diff --git a/sim/sh64/cpu.h b/sim/sh64/cpu.h
index a5d6f34b64..c2a14e4636 100644
--- a/sim/sh64/cpu.h
+++ b/sim/sh64/cpu.h
@@ -2,23 +2,22 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2005 Free Software Foundation, Inc.
+Copyright 1996-2020 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, see <http://www.gnu.org/licenses/>.
 
 */
 
@@ -32,6 +31,12 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 /* Maximum number of instructions that can be executed in parallel.  */
 #define MAX_PARALLEL_INSNS 1
 
+/* The size of an "int" needed to hold an instruction word.
+   This is usually 32 bits, but some architectures needs 64 bits.  */
+typedef CGEN_INSN_INT CGEN_INSN_WORD;
+
+#include "cgen-engine.h"
+
 /* CPU state information.  */
 typedef struct {
   /* Hardware elements.  */
@@ -48,7 +53,7 @@ CPU (h_pc) = ANDDI ((x), INVDI (1));\
 ;} while (0)
   /* General purpose integer registers */
   DI h_gr[64];
-#define GET_H_GR(index) ((((index) == (63))) ? (0) : (CPU (h_gr[index])))
+#define GET_H_GR(index) ((((index) == (63))) ? (MAKEDI (0, 0)) : (CPU (h_gr[index])))
 #define SET_H_GR(index, x) \
 do { \
 if ((((index)) != (63))) {\
@@ -82,22 +87,22 @@ CPU (h_cr[(index)]) = (x);\
 #define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x))
   /* Single/Double precision floating point registers */
   DF h_fsd[16];
-#define GET_H_FSD(index) ((GET_H_PRBIT ()) ? (GET_H_DRC (index)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), CPU (h_fr[index]))))
+#define GET_H_FSD(index) ((GET_H_PRBIT ()) ? (GET_H_DRC (index)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, CPU (h_fr[index]))))
 #define SET_H_FSD(index, x) \
 do { \
 if (GET_H_PRBIT ()) {\
 SET_H_DRC ((index), (x));\
 } else {\
-SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), (x)));\
+SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, (x)));\
 }\
 ;} while (0)
   /* floating point registers for fmov */
   DF h_fmov[16];
-#define GET_H_FMOV(index) ((NOTBI (GET_H_SZBIT ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), GET_H_FRC (index))) : (((((((index) & (1))) == (1))) ? (GET_H_XD (((index) & ((~ (1)))))) : (GET_H_DR (index)))))
+#define GET_H_FMOV(index) ((NOTBI (GET_H_SZBIT ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, GET_H_FRC (index))) : (((((((index) & (1))) == (1))) ? (GET_H_XD (((index) & ((~ (1)))))) : (GET_H_DR (index)))))
 #define SET_H_FMOV(index, x) \
 do { \
 if (NOTBI (GET_H_SZBIT ())) {\
-SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), (x)));\
+SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, (x)));\
 } else {\
 if ((((((index)) & (1))) == (1))) {\
 SET_H_XD ((((index)) & ((~ (1)))), (x));\