X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fsh64%2Fsh64.c;h=4b936dd7065cbef0188f4db7acfeab76ad2554fc;hb=37d5ab199b072e3cf1e8bf2a9262767c4737d256;hp=e82605d2e57b5df4d7f96d60b967ad0d3e9dded1;hpb=9b254dd1ce46c19dde1dde5b8d1e22e862dfacce;p=deliverable%2Fbinutils-gdb.git

diff --git a/sim/sh64/sh64.c b/sim/sh64/sh64.c
index e82605d2e5..4b936dd706 100644
--- a/sim/sh64/sh64.c
+++ b/sim/sh64/sh64.c
@@ -1,5 +1,5 @@
 /* SH5 simulator support code
-   Copyright (C) 2000, 2001, 2006, 2008 Free Software Foundation, Inc.
+   Copyright (C) 2000-2019 Free Software Foundation, Inc.
    Contributed by Red Hat, Inc.
 
 This file is part of the GNU simulators.
@@ -529,22 +529,6 @@ sh64_pref (SIM_CPU *cpu, SI addr)
   /* TODO: Unimplemented.  */
 }
 
-/* Count the number of arguments.  */
-static int
-count_argc (cpu)
-     SIM_CPU *cpu;
-{
-  int i = 0;
-
-  if (! STATE_PROG_ARGV (CPU_STATE (cpu)))
-    return -1;
-  
-  while (STATE_PROG_ARGV (CPU_STATE (cpu)) [i] != NULL)
-    ++i;
-
-  return i;
-}
-
 /* Read a null terminated string from memory, return in a buffer */
 static char *
 fetch_str (current_cpu, pc, addr)
@@ -593,7 +577,7 @@ trap_handler (SIM_CPU *current_cpu, int shmedia_abi_p, UQI trapnum, PCADDR pc)
 	    SET_H_GR (ret_reg,
 		      sim_io_write (CPU_STATE (current_cpu),
 				    PARM1, buf, PARM3));
-	    zfree (buf);
+	    free (buf);
 	    break;
 
 	  case SYS_lseek:
@@ -613,7 +597,7 @@ trap_handler (SIM_CPU *current_cpu, int shmedia_abi_p, UQI trapnum, PCADDR pc)
 		      sim_io_read (CPU_STATE (current_cpu),
 				   PARM1, buf, PARM3));
 	    sim_write (CPU_STATE (current_cpu), PARM2, buf, PARM3);
-	    zfree (buf);
+	    free (buf);
 	    break;
 	    
 	  case SYS_open:
@@ -621,7 +605,7 @@ trap_handler (SIM_CPU *current_cpu, int shmedia_abi_p, UQI trapnum, PCADDR pc)
 	    SET_H_GR (ret_reg,
 		      sim_io_open (CPU_STATE (current_cpu),
 				   buf, PARM2));
-	    zfree (buf);
+	    free (buf);
 	    break;
 
 	  case SYS_close:
@@ -634,11 +618,11 @@ trap_handler (SIM_CPU *current_cpu, int shmedia_abi_p, UQI trapnum, PCADDR pc)
 	    break;
 
 	  case SYS_argc:
-	    SET_H_GR (ret_reg, count_argc (current_cpu));
+	    SET_H_GR (ret_reg, countargv (STATE_PROG_ARGV (CPU_STATE (current_cpu))));
 	    break;
 
 	  case SYS_argnlen:
-	    if (PARM1 < count_argc (current_cpu))
+	    if (PARM1 < countargv (STATE_PROG_ARGV (CPU_STATE (current_cpu))))
 	      SET_H_GR (ret_reg,
 			strlen (STATE_PROG_ARGV (CPU_STATE (current_cpu)) [PARM1]));
 	    else
@@ -646,7 +630,7 @@ trap_handler (SIM_CPU *current_cpu, int shmedia_abi_p, UQI trapnum, PCADDR pc)
 	    break;
 
 	  case SYS_argn:
-	    if (PARM1 < count_argc (current_cpu))
+	    if (PARM1 < countargv (STATE_PROG_ARGV (CPU_STATE (current_cpu))))
 	      {
 		/* Include the NULL byte.  */
 		i = strlen (STATE_PROG_ARGV (CPU_STATE (current_cpu)) [PARM1]) + 1;
@@ -1030,7 +1014,7 @@ sh64_model_init()
   /* Do nothing.  */
 }
 
-static const MODEL sh_models [] =
+static const SIM_MODEL sh_models [] =
 {
   { "sh2",        & sh2_mach,         MODEL_SH5, NULL, sh64_model_init },
   { "sh2e",       & sh2e_mach,        MODEL_SH5, NULL, sh64_model_init },
@@ -1047,7 +1031,7 @@ static const MODEL sh_models [] =
   { 0 }
 };
 
-static const MACH_IMP_PROPERTIES sh5_imp_properties =
+static const SIM_MACH_IMP_PROPERTIES sh5_imp_properties =
 {
   sizeof (SIM_CPU),
 #if WITH_SCACHE
@@ -1057,7 +1041,7 @@ static const MACH_IMP_PROPERTIES sh5_imp_properties =
 #endif
 };
 
-const MACH sh2_mach =
+const SIM_MACH sh2_mach =
 {
   "sh2", "sh2", MACH_SH5,
   16, 16, &sh_models[0], &sh5_imp_properties,
@@ -1065,7 +1049,7 @@ const MACH sh2_mach =
   sh64_prepare_run
 };
 
-const MACH sh2e_mach =
+const SIM_MACH sh2e_mach =
 {
   "sh2e", "sh2e", MACH_SH5,
   16, 16, &sh_models[1], &sh5_imp_properties,
@@ -1073,7 +1057,7 @@ const MACH sh2e_mach =
   sh64_prepare_run
 };
 
-const MACH sh2a_fpu_mach =
+const SIM_MACH sh2a_fpu_mach =
 {
   "sh2a", "sh2a", MACH_SH5,
   16, 16, &sh_models[2], &sh5_imp_properties,
@@ -1081,7 +1065,7 @@ const MACH sh2a_fpu_mach =
   sh64_prepare_run
 };
 
-const MACH sh2a_nofpu_mach =
+const SIM_MACH sh2a_nofpu_mach =
 {
   "sh2a_nofpu", "sh2a_nofpu", MACH_SH5,
   16, 16, &sh_models[3], &sh5_imp_properties,
@@ -1089,7 +1073,7 @@ const MACH sh2a_nofpu_mach =
   sh64_prepare_run
 };
 
-const MACH sh3_mach =
+const SIM_MACH sh3_mach =
 {
   "sh3", "sh3", MACH_SH5,
   16, 16, &sh_models[4], &sh5_imp_properties,
@@ -1097,7 +1081,7 @@ const MACH sh3_mach =
   sh64_prepare_run
 };
 
-const MACH sh3e_mach =
+const SIM_MACH sh3e_mach =
 {
   "sh3e", "sh3e", MACH_SH5,
   16, 16, &sh_models[5], &sh5_imp_properties,
@@ -1105,7 +1089,7 @@ const MACH sh3e_mach =
   sh64_prepare_run
 };
 
-const MACH sh4_mach =
+const SIM_MACH sh4_mach =
 {
   "sh4", "sh4", MACH_SH5,
   16, 16, &sh_models[6], &sh5_imp_properties,
@@ -1113,7 +1097,7 @@ const MACH sh4_mach =
   sh64_prepare_run
 };
 
-const MACH sh4_nofpu_mach =
+const SIM_MACH sh4_nofpu_mach =
 {
   "sh4_nofpu", "sh4_nofpu", MACH_SH5,
   16, 16, &sh_models[7], &sh5_imp_properties,
@@ -1121,7 +1105,7 @@ const MACH sh4_nofpu_mach =
   sh64_prepare_run
 };
 
-const MACH sh4a_mach =
+const SIM_MACH sh4a_mach =
 {
   "sh4a", "sh4a", MACH_SH5,
   16, 16, &sh_models[8], &sh5_imp_properties,
@@ -1129,7 +1113,7 @@ const MACH sh4a_mach =
   sh64_prepare_run
 };
 
-const MACH sh4a_nofpu_mach =
+const SIM_MACH sh4a_nofpu_mach =
 {
   "sh4a_nofpu", "sh4a_nofpu", MACH_SH5,
   16, 16, &sh_models[9], &sh5_imp_properties,
@@ -1137,7 +1121,7 @@ const MACH sh4a_nofpu_mach =
   sh64_prepare_run
 };
 
-const MACH sh4al_mach =
+const SIM_MACH sh4al_mach =
 {
   "sh4al", "sh4al", MACH_SH5,
   16, 16, &sh_models[10], &sh5_imp_properties,
@@ -1145,7 +1129,7 @@ const MACH sh4al_mach =
   sh64_prepare_run
 };
 
-const MACH sh5_mach =
+const SIM_MACH sh5_mach =
 {
   "sh5", "sh5", MACH_SH5,
   32, 32, &sh_models[11], &sh5_imp_properties,