X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fv850%2FMakefile.in;h=00e560e73f1b13d50b45dbceafa224ad4dfb4edd;hb=128e85e3ab36b8e30f6612fb50de3cbb4ede6824;hp=c7125a666c63a4716927f6d291bd3ef5460b32f0;hpb=4dda50b0520889ccb5f71fac4781a6f02bc5a829;p=deliverable%2Fbinutils-gdb.git diff --git a/sim/v850/Makefile.in b/sim/v850/Makefile.in index c7125a666c..00e560e73f 100644 --- a/sim/v850/Makefile.in +++ b/sim/v850/Makefile.in @@ -1,85 +1,45 @@ # Makefile template for Configure for the V850 sim library. -# Copyright (C) 1996, 1997 Free Software Foundation, Inc. +# Copyright (C) 1996-2016 Free Software Foundation, Inc. # Written by Cygnus Support. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or +# the Free Software Foundation; either version 3 of the License, or # (at your option) any later version. -# +# # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -# +# # You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# along with this program. If not, see . + +SHELL = @SHELL@ ## COMMON_PRE_CONFIG_FRAG SIM_OBJS = \ + $(SIM_NEW_COMMON_OBJS) \ simops.o interp.o \ itable.o semantics.o idecode.o icache.o engine.o irun.o support.o \ - sim-bits.o \ - sim-config.o \ - sim-core.o \ - sim-engine.o \ - sim-endian.o \ - sim-events.o \ - sim-hload.o \ - sim-hrw.o \ - sim-io.o \ - sim-load.o \ - sim-memopt.o \ - sim-module.o \ - sim-options.o \ - sim-profile.o \ - sim-resume.o \ - sim-reason.o \ - sim-stop.o \ - sim-trace.o \ - sim-watch.o \ - sim-utils.o -SIM_RUN_OBJS = nrun.o + sim-resume.o # List of extra dependencies. # Generally this consists of simulator specific files included by sim-main.h. SIM_EXTRA_DEPS = v850_sim.h sim-main.h simops.h itable.h # List of flags to always pass to $(CC) -SIM_WARNINGS=@sim_warnings@ -SIM_ENDIAN=@sim_endian@ -SIM_HOSTENDIAN=@sim_hostendian@ -SIM_RESERVED_BITS=@sim_reserved_bits@ SIM_EXTRA_CFLAGS = \ -DDEBUG \ - -I$(srcdir)/../../newlib/libc/sys/sysnecv850 \ - $(SIM_WARNINGS) \ - $(SIM_ENDIAN) \ - $(SIM_HOSTENDIAN) \ - $(SIM_RESERVED_BITS) + -I$(srcdir)/../../newlib/libc/sys/sysnecv850 SIM_EXTRA_CLEAN = clean-extra -INCLUDE = $(sim_main_headers) $(SIM_EXTRA_DEPS) - -## COMMON_POST_CONFIG_FRAG - -simops.h table.c: tmp-gencode -tmp-gencode: gencode - ./gencode >tmp-table.c - mv tmp-table.c table.c - ./gencode -h >tmp-simops.h - mv tmp-simops.h simops.h - touch tmp-gencode -gencode.o: gencode.c - $(CC_FOR_BUILD) $(BUILD_CFLAGS) -c $(srcdir)/gencode.c -v850-opc.o: $(srcdir)/../../opcodes/v850-opc.c - $(CC_FOR_BUILD) $(BUILD_CFLAGS) -c $< -gencode: gencode.o v850-opc.o - $(CC_FOR_BUILD) $(BUILD_CFLAGS) -o gencode gencode.o v850-opc.o +INCLUDE = $(sim_main_headers) $(SIM_EXTRA_DEPS) +NL_TARGET = -DNL_TARGET_v850 +## COMMON_POST_CONFIG_FRAG BUILT_SRC_FROM_IGEN = \ icache.h \ @@ -97,7 +57,7 @@ BUILT_SRC_FROM_IGEN = \ engine.h \ engine.c \ irun.c -$(BUILT_SRC_FROM_IGEN): tmp-igen simops.h +$(BUILT_SRC_FROM_IGEN): tmp-igen # .PHONY: clean-igen @@ -108,12 +68,15 @@ clean-igen: ../igen/igen: cd ../igen && $(MAKE) +IGEN_TRACE= # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries IGEN_INSN=$(srcdir)/v850.igen IGEN_DC=$(srcdir)/v850-dc tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen cd ../igen && $(MAKE) ../igen/igen \ + $(IGEN_TRACE) \ -G gen-direct-access \ + -G gen-zero-r0 \ -i $(IGEN_INSN) \ -o $(IGEN_DC) \ -x \ @@ -132,27 +95,26 @@ tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen -n engine.h -he tmp-engine.h \ -n engine.c -e tmp-engine.c \ -n irun.c -r tmp-irun.c - $(srcdir)/../../move-if-change tmp-icache.h icache.h - $(srcdir)/../../move-if-change tmp-icache.c icache.c - $(srcdir)/../../move-if-change tmp-idecode.h idecode.h - $(srcdir)/../../move-if-change tmp-idecode.c idecode.c - $(srcdir)/../../move-if-change tmp-semantics.h semantics.h - $(srcdir)/../../move-if-change tmp-semantics.c semantics.c - $(srcdir)/../../move-if-change tmp-model.h model.h - $(srcdir)/../../move-if-change tmp-model.c model.c - $(srcdir)/../../move-if-change tmp-support.h support.h - $(srcdir)/../../move-if-change tmp-support.c support.c - $(srcdir)/../../move-if-change tmp-itable.h itable.h - $(srcdir)/../../move-if-change tmp-itable.c itable.c - $(srcdir)/../../move-if-change tmp-engine.h engine.h - $(srcdir)/../../move-if-change tmp-engine.c engine.c - $(srcdir)/../../move-if-change tmp-irun.c irun.c + $(SHELL) $(srcdir)/../../move-if-change tmp-icache.h icache.h + $(SHELL) $(srcdir)/../../move-if-change tmp-icache.c icache.c + $(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h idecode.h + $(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c idecode.c + $(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h semantics.h + $(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c semantics.c + $(SHELL) $(srcdir)/../../move-if-change tmp-model.h model.h + $(SHELL) $(srcdir)/../../move-if-change tmp-model.c model.c + $(SHELL) $(srcdir)/../../move-if-change tmp-support.h support.h + $(SHELL) $(srcdir)/../../move-if-change tmp-support.c support.c + $(SHELL) $(srcdir)/../../move-if-change tmp-itable.h itable.h + $(SHELL) $(srcdir)/../../move-if-change tmp-itable.c itable.c + $(SHELL) $(srcdir)/../../move-if-change tmp-engine.h engine.h + $(SHELL) $(srcdir)/../../move-if-change tmp-engine.c engine.c + $(SHELL) $(srcdir)/../../move-if-change tmp-irun.c irun.c touch tmp-igen clean-extra: clean-igen rm -f table.c simops.h gencode -#interp.o: interp.c table.c $(INCLUDE) -simops.o: simops.c $(INCLUDE) -#table.o: table.c +interp.o: interp.c $(INCLUDE) +simops.o: simops.c simops.h $(INCLUDE) targ-vals.h semantics.o: $(INCLUDE)