X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fv850%2Fsim-main.h;h=e9f7aadac203175004424ec617343364361e41c0;hb=38f48d729d916673434b57dabd7e88e637544033;hp=44a5669a4d4278fc21bc79c6ef959307a10efbd2;hpb=6aead89a5fa550f1845fb5b3c85f50e53afb6f92;p=deliverable%2Fbinutils-gdb.git diff --git a/sim/v850/sim-main.h b/sim/v850/sim-main.h index 44a5669a4d..e9f7aadac2 100644 --- a/sim/v850/sim-main.h +++ b/sim/v850/sim-main.h @@ -1,23 +1,22 @@ +#ifndef SIM_MAIN_H +#define SIM_MAIN_H + +/* General config options */ + #define WITH_CORE #define WITH_MODULO_MEMORY 1 #define WITH_WATCHPOINTS 1 -#define WITH_TARGET_WORD_MSB 31 -#include "sim-basics.h" -#include -typedef address_word sim_cia; +/* The v850 has 32bit words, numbered 31 (MSB) to 0 (LSB) */ + +#define WITH_TARGET_WORD_MSB 31 -/* This simulator doesn't cache state */ -#define SIM_ENGINE_HALT_HOOK(sd,last_cpu,cia) while (0) -#define SIM_ENGINE_RESTART_HOOK(sd,last_cpu,cia) while (0) +#include "sim-basics.h" +#include "sim-signal.h" -/* Get the number of instructions. FIXME: must be a more elegant way - of doing this. */ -#include "itable.h" -#define MAX_INSNS (nr_itable_entries) -#define INSN_NAME(i) itable[(i)].name +typedef address_word sim_cia; #include "sim-base.h" @@ -41,7 +40,6 @@ typedef struct _v850_regs { reg_t sregs[32]; /* system registers, including psw */ reg_t pc; int dummy_mem; /* where invalid accesses go */ - int pending_nmi; } v850_regs; struct _sim_cpu @@ -49,11 +47,13 @@ struct _sim_cpu /* ... simulator specific members ... */ v850_regs reg; reg_t psw_mask; /* only allow non-reserved bits to be set */ + sim_event *pending_nmi; /* ... base type ... */ sim_cpu_base base; }; -#define CPU_CIA(CPU) ((CPU)->reg.pc) +#define CIA_GET(CPU) ((CPU)->reg.pc + 0) +#define CIA_SET(CPU,VAL) ((CPU)->reg.pc = (VAL)) struct sim_state { sim_cpu cpu[MAX_NR_PROCESSORS]; @@ -82,9 +82,6 @@ extern SIM_DESC simulator; #define V850_HIGH_START 0xffe000 -#define SIG_V850_EXIT -1 /* indication of a normal exit */ - - /* Because we are still using the old semantic table, provide compat macro's that store the instruction where the old simops expects it. */ @@ -138,19 +135,13 @@ nia = PC #define FEPSW (State.sregs[3]) #define ECR (State.sregs[4]) #define PSW (State.sregs[5]) -/* start-sanitize-v850e */ #define CTPC (SR[16]) #define CTPSW (SR[17]) -/* end-sanitize-v850e */ #define DBPC (State.sregs[18]) #define DBPSW (State.sregs[19]) -/* start-sanitize-v850e */ #define CTBP (State.sregs[20]) -/* end-sanitize-v850e */ -/* start-sanitize-v850eq */ #define PSW_US BIT32 (8) -/* end-sanitize-v850eq */ #define PSW_NP 0x80 #define PSW_EP 0x40 #define PSW_ID 0x20 @@ -196,32 +187,26 @@ nia = PC #define RLW(x) load_mem (x, 4) -#ifdef _WIN32 -#ifndef SIGTRAP -#define SIGTRAP 5 -#endif -#ifndef SIGQUIT -#define SIGQUIT 3 -#endif -#endif - /* Function declarations. */ -#define IMEM(EA) \ -sim_core_read_aligned_2 (STATE_CPU (sd, 0), \ - PC, sim_core_execute_map, (EA)) +#define IMEM16(EA) \ +sim_core_read_aligned_2 (CPU, PC, exec_map, (EA)) -#define IMEM_IMMED(EA,N) \ +#define IMEM16_IMMED(EA,N) \ sim_core_read_aligned_2 (STATE_CPU (sd, 0), \ - PC, sim_core_execute_map, (EA) + (N) * 2) + PC, exec_map, (EA) + (N) * 2) #define load_mem(ADDR,LEN) \ sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \ - PC, sim_core_read_map, (ADDR)) + PC, read_map, (ADDR)) #define store_mem(ADDR,LEN,DATA) \ sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \ - PC, sim_core_write_map, (ADDR), (DATA)) + PC, write_map, (ADDR), (DATA)) + + +/* compare cccc field against PSW */ +int condition_met (unsigned code); /* Debug/tracing calls */ @@ -253,17 +238,13 @@ enum op_types OP_EX2, OP_LDSR, OP_STSR, -/* start-sanitize-v850e */ OP_BIT_CHANGE, OP_REG_REG_REG, OP_REG_REG3, -/* end-sanitize-v850e */ -/* start-sanitize-v850eq */ OP_IMM_REG_REG_REG, OP_PUSHPOP1, OP_PUSHPOP2, OP_PUSHPOP3, -/* end-sanitize-v850eq */ }; #ifdef DEBUG @@ -275,124 +256,135 @@ extern int trace_num_values; extern unsigned32 trace_values[]; extern unsigned32 trace_pc; extern const char *trace_name; -extern const char *trace_module; +extern int trace_module; -#define TRACE_ALU_INPUT0() \ +#define TRACE_BRANCH0() \ do { \ - if (TRACE_ALU_P (CPU)) { \ - trace_module = "alu"; \ + if (TRACE_BRANCH_P (CPU)) { \ + trace_module = TRACE_BRANCH_IDX; \ trace_pc = cia; \ trace_name = itable[MY_INDEX].name; \ trace_num_values = 0; \ + trace_result (1, (nia)); \ } \ } while (0) -#define TRACE_ALU_INPUT1(IN1) \ +#define TRACE_BRANCH1(IN1) \ do { \ - if (TRACE_ALU_P (CPU)) { \ - trace_module = "alu"; \ + if (TRACE_BRANCH_P (CPU)) { \ + trace_module = TRACE_BRANCH_IDX; \ trace_pc = cia; \ trace_name = itable[MY_INDEX].name; \ trace_values[0] = (IN1); \ trace_num_values = 1; \ + trace_result (1, (nia)); \ } \ } while (0) -#define TRACE_ALU_INPUT2(IN1, IN2) \ +#define TRACE_BRANCH2(IN1, IN2) \ do { \ - if (TRACE_ALU_P (CPU)) { \ - trace_module = "alu"; \ + if (TRACE_BRANCH_P (CPU)) { \ + trace_module = TRACE_BRANCH_IDX; \ trace_pc = cia; \ trace_name = itable[MY_INDEX].name; \ trace_values[0] = (IN1); \ trace_values[1] = (IN2); \ trace_num_values = 2; \ + trace_result (1, (nia)); \ } \ } while (0) -#define TRACE_ALU_RESULT(RESULT) \ +#define TRACE_BRANCH3(IN1, IN2, IN3) \ do { \ - if (TRACE_ALU_P (CPU)) { \ - trace_result (1, (RESULT)); \ + if (TRACE_BRANCH_P (CPU)) { \ + trace_module = TRACE_BRANCH_IDX; \ + trace_pc = cia; \ + trace_name = itable[MY_INDEX].name; \ + trace_values[0] = (IN1); \ + trace_values[1] = (IN2); \ + trace_values[2] = (IN3); \ + trace_num_values = 3; \ + trace_result (1, (nia)); \ } \ } while (0) -#define TRACE_BRANCH1(IN1) \ +#define TRACE_LD(ADDR,RESULT) \ do { \ - if (TRACE_BRANCH_P (CPU)) { \ - trace_module = "branch"; \ + if (TRACE_MEMORY_P (CPU)) { \ + trace_module = TRACE_MEMORY_IDX; \ trace_pc = cia; \ trace_name = itable[MY_INDEX].name; \ - trace_values[0] = (IN1); \ + trace_values[0] = (ADDR); \ trace_num_values = 1; \ - trace_result (1, (nia)); \ + trace_result (1, (RESULT)); \ } \ } while (0) -#define TRACE_BRANCH2(IN1, IN2) \ +#define TRACE_LD_NAME(NAME, ADDR,RESULT) \ do { \ - if (TRACE_BRANCH_P (CPU)) { \ - trace_module = "branch"; \ + if (TRACE_MEMORY_P (CPU)) { \ + trace_module = TRACE_MEMORY_IDX; \ trace_pc = cia; \ - trace_name = itable[MY_INDEX].name; \ - trace_values[0] = (IN1); \ - trace_values[1] = (IN2); \ - trace_num_values = 2; \ - trace_result (1, (nia)); \ + trace_name = (NAME); \ + trace_values[0] = (ADDR); \ + trace_num_values = 1; \ + trace_result (1, (RESULT)); \ } \ } while (0) -#define TRACE_BRANCH3(IN1, IN2, IN3) \ +#define TRACE_ST(ADDR,RESULT) \ do { \ - if (TRACE_BRANCH_P (CPU)) { \ - trace_module = "branch"; \ + if (TRACE_MEMORY_P (CPU)) { \ + trace_module = TRACE_MEMORY_IDX; \ trace_pc = cia; \ trace_name = itable[MY_INDEX].name; \ - trace_values[0] = (IN1); \ - trace_values[1] = (IN2); \ - trace_values[2] = (IN3); \ - trace_num_values = 3; \ - trace_result (1, (nia)); \ + trace_values[0] = (ADDR); \ + trace_num_values = 1; \ + trace_result (1, (RESULT)); \ } \ } while (0) - #else #define trace_input(NAME, IN1, IN2) #define trace_output(RESULT) #define trace_result(HAS_RESULT, RESULT) #define TRACE_ALU_INPUT0() -#define TRACE_ALU_INPUT1(IN1) -#define TRACE_ALU_INPUT2(IN1, IN2) +#define TRACE_ALU_INPUT1(IN0) +#define TRACE_ALU_INPUT2(IN0, IN1) +#define TRACE_ALU_INPUT2(IN0, IN1) +#define TRACE_ALU_INPUT2(IN0, IN1 INS2) #define TRACE_ALU_RESULT(RESULT) +#define TRACE_BRANCH0() #define TRACE_BRANCH1(IN1) #define TRACE_BRANCH2(IN1, IN2) #define TRACE_BRANCH2(IN1, IN2, IN3) + +#define TRACE_LD(ADDR,RESULT) +#define TRACE_ST(ADDR,RESULT) + #endif +#define GPR_SET(N, VAL) (State.regs[(N)] = (VAL)) +#define GPR_CLEAR(N) (State.regs[(N)] = 0) -/* start-sanitize-v850eq */ extern void divun ( unsigned int N, unsigned long int als, unsigned long int sfi, - unsigned long int * quotient_ptr, - unsigned long int * remainder_ptr, - boolean * overflow_ptr + unsigned32 /*unsigned long int*/ * quotient_ptr, + unsigned32 /*unsigned long int*/ * remainder_ptr, + int *overflow_ptr ); extern void divn ( unsigned int N, unsigned long int als, unsigned long int sfi, - signed long int * quotient_ptr, - signed long int * remainder_ptr, - boolean * overflow_ptr + signed32 /*signed long int*/ * quotient_ptr, + signed32 /*signed long int*/ * remainder_ptr, + int *overflow_ptr ); -/* end-sanitize-v850eq */ -/* start-sanitize-v850e */ extern int type1_regs[]; extern int type2_regs[]; -/* end-sanitize-v850e */ -/* start-sanitize-v850eq */ extern int type3_regs[]; -/* end-sanitize-v850eq */ + +#endif