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perf/x86: Implement IBS pmu control ops
authorRobert Richter <robert.richter@amd.com>
Thu, 15 Dec 2011 16:56:38 +0000 (17:56 +0100)
committerIngo Molnar <mingo@elte.hu>
Thu, 8 Mar 2012 10:35:22 +0000 (11:35 +0100)
commit4db2e8e6500d9ba6406f2714fa3968b39a325274
tree2c4c3378fe8ca0d1ce379e826f82e28446a40903tree | snapshot
parentb7074f1fbd6149eac1ec25063e4a364c39a85473commit | diff
perf/x86: Implement IBS pmu control ops

Add code to control the IBS pmu. We need to maintain per-cpu
states. Since some states are used and changed by the nmi
handler, access to these states must be atomic.

Signed-off-by: Robert Richter <robert.richter@amd.com>
Acked-by: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Link: http://lkml.kernel.org/r/1323968199-9326-4-git-send-email-robert.richter@amd.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
arch/x86/kernel/cpu/perf_event_amd_ibs.c diff | blob | blame | history
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