drm/i915: properly enable the blc controller on the right pipe
authorDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 5 Jun 2012 10:14:54 +0000 (12:14 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 12 Jun 2012 17:27:58 +0000 (19:27 +0200)
commit24ded204429fa0f5501d37c63ee35c555c0b75ee
tree0fcebac4835709b28ed26b30d02b64a88c0e158a
parent7cf4160148136deb31ee5f2802857dd935a38529
drm/i915: properly enable the blc controller on the right pipe

On gen4+ we have a bitfield to specify from which pipe the backlight
controller should take it's clock. For PCH split platforms we've
already set these up, but only at initialization time. And without
taking into account the 3rd pipe added with ivb.

For gen4, we've completely ignored these. Although we do restrict lvds
to the 2nd pipe, so this is only a problem on machines where we boot
up with the lvds on the first pipe.

So restructure the code to enable the backlight on the right pipe at
modeset time.

v2: For odd reasons panel_enable_backlight gets called twice in a
modeset, so we can't WARN_ON in there if the backlight controller is
switched on already.

v3: backlight enable can also be called through dpms on, so the check
in there is legit. Update the comment to reflect that.

Tested-By: Kamal Mostafa <kamal@canonical.com>
Bugzilla: https://bugs.launchpad.net/bugs/954661
Cc: Carsten Emde <C.Emde@osadl.org>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_drv.h
drivers/gpu/drm/i915/intel_lvds.c
drivers/gpu/drm/i915/intel_panel.c
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