drm/i915: PSR: Flush means invalidate + flush
authorRodrigo Vivi <rodrigo.vivi@intel.com>
Wed, 8 Jul 2015 23:21:31 +0000 (16:21 -0700)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 9 Jul 2015 14:35:35 +0000 (16:35 +0200)
commit169de1316c1e69ad169d81c60549479640461630
treecca3622cb8877467534efdc4b47d14de2614b0aa
parentde152b627eb3018de91ec5c5a50b38e17d80a88b
drm/i915: PSR: Flush means invalidate + flush

Since flush actually means invalidate + flush we need to force psr
exit on PSR flush.

On Core platforms there is no way to disable hw tracking and
do the pure sw tracking so we simulate it by fully disable psr and
reschedule a enable back.
So a good idea is to minimize sequential disable/enable in cases we
know that HW tracking like when flush has been originated by a flip.
Also flip had just invalidated it already.

It also uses origin to minimize the a bit the amount of
disable/enabled, mainly when flip already had invalidated.

With this patch in place it is possible to do a flush on dirty areas
properly in a following patch.

v2: Remove duplicated exit on HSW+Sprites as pointed out by Paulo.

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_drv.h
drivers/gpu/drm/i915/intel_frontbuffer.c
drivers/gpu/drm/i915/intel_psr.c
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