spi: bcm2835aux: fix CPOL/CPHA setting
authorStephan Olbrich <stephanolbrich@gmx.de>
Sun, 14 Feb 2016 10:04:29 +0000 (11:04 +0100)
committerMark Brown <broonie@kernel.org>
Mon, 15 Feb 2016 20:45:47 +0000 (20:45 +0000)
commite9dd4edcc98593bbcdffc0c4f37545b8fd0ad3ea
tree69d6cc2f8d528c87b0828401659ad6ec3f751965
parentb4e2adef62062cf716d1c81adc12ad6def516f72
spi: bcm2835aux: fix CPOL/CPHA setting

The auxiliary spi supports only CPHA=0 modes as the first bit is
always output to the pin before the first clock cycle. In CPHA=1
modes the first clock edge outputs the second bit hence the slave
can never read the first bit.

Also the CPHA registers switch between clocking data in/out on
rising/falling edge hence depend on the CPOL setting.

Signed-off-by: Stephan Olbrich <stephanolbrich@gmx.de>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
drivers/spi/spi-bcm2835aux.c
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