RISC-V: Make objdump disassembly work right for binary files.
authorJim Wilson <jimw@sifive.com>
Thu, 27 Jun 2019 00:17:09 +0000 (17:17 -0700)
committerJim Wilson <jimw@sifive.com>
Thu, 27 Jun 2019 00:17:09 +0000 (17:17 -0700)
commitd7560e2df501c7da1b0e4e64116dd52fe5715a96
treeffcd2ca790a3e0937d93ba4dbd9101dc46a5f247
parent696d5b3801a0e9d6514a92734bde09985f968a2f
RISC-V: Make objdump disassembly work right for binary files.

Without the ELF header to set info->endian, it ends up as BFD_UNKNOWN_ENDIAN
which gets printed as big-endian.  But RISC-V instructions are always little
endian, so we can set endian_code correctly, and then set display_endian from
that.  This is similar to how the aarch64 support works, but without the
support for constant pools, as we don't have that on RISC-V.

opcodes/
PR binutils/24739
* riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
Set info->display_endian to info->endian_code.
opcodes/ChangeLog
opcodes/riscv-dis.c
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