MIPS: bugfix: missed cache flush of TLB refill handler

MIPS: bugfix: missed cache flush of TLB refill handler

Commit

    Commit 1d40cfcd3442a53e98468cdb3e6d4d9a568d76cf
    Author: Ralf Baechle <ralf@linux-mips.org>
    Date:   Fri Jul 15 15:23:23 2005 +0000

    Avoid SMP cacheflushes.  This is a minor optimization of startup but
    will also avoid smp_call_function from doing stupid things when called
    from a CPU that is not yet marked online.

missed an appropriate cache flush of TLB refill handler because that time it was
at fixed location CAC_BASE. After years the refill handler in EBASE vector
is not at that location and can be allocated in some another memory and needs
I-cache sync as other TLB exception vectors.

Besides that, the new function - local_flash_icache_range() was introduced
to avoid SMP cacheflushes.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: paul.gortmaker@windriver.com
Cc: jchandra@broadcom.com
Cc: linux-kernel@vger.kernel.org
Cc: david.daney@cavium.com
Patchwork: https://patchwork.linux-mips.org/patch/7312/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>