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riscv: Template memory ordering and percpu access mode
authorMathieu Desnoyers <mathieu.desnoyers@efficios.com>
Tue, 25 Apr 2023 16:02:24 +0000 (12:02 -0400)
committerMathieu Desnoyers <mathieu.desnoyers@efficios.com>
Tue, 25 Apr 2023 22:38:09 +0000 (18:38 -0400)
commit154b6bde7177cab2480f0a46bb9dbf2133a94e7e
tree1c45e99478f34e27ff4e6739f50744af6261d2bctree | snapshot
parentf3b2cb145d71d54e6d4002683586c64b9cb1ba42commit | diff
riscv: Template memory ordering and percpu access mode

Introduce a rseq-riscv-bits.h template header which is internally included
to generate the static inline functions covering:

- relaxed and release memory ordering,
- per-cpu-id and per-mm-cid per-cpu data access.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Ia88fd435f0593f31f31eec5cd8cd8099b1cb8af8
include/rseq/rseq-riscv-bits.h [new file with mode: 0644] blob
include/rseq/rseq-riscv.h diff | blob | blame | history
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