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(parent: 926655f) | patch
clk: tegra: Initialize PLL_C to sane rate on Tegra30
authorLucas Stach <dev@lynxeye.de>
Mon, 29 Feb 2016 20:46:06 +0000 (21:46 +0100)
committerThierry Reding <treding@nvidia.com>
Thu, 28 Apr 2016 10:41:51 +0000 (12:41 +0200)
commita02cc84a31d3bd46a10546ff7024e7b5a186d339
treecf51407240888a2c212593cd89541e97ba88a014tree | snapshot
parent926655f929063619b13db8b4f2ef8c9a08605492commit | diff
clk: tegra: Initialize PLL_C to sane rate on Tegra30

If the bootloader does not touch PLL_C it will stay in its reset state,
failing to lock when enabled. This leads to consumers of this clock to
fail probing. Fix this by always programming the PLL with a sane rate,
which allows it to lock, at startup.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-tegra30.c diff | blob | blame | history
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