drm/i915: Check pixel clock limits on pre-gen4
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 4 Sep 2013 15:30:04 +0000 (18:30 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 17 Sep 2013 08:02:22 +0000 (10:02 +0200)
commitad3a44799510e778a6b4bf7999618634bdd6615d
treedefcdf6e4cb6420ee803a832b454fc4cde32dc6b
parent282740f73a93461645bb87cd62e428aa625619fb
drm/i915: Check pixel clock limits on pre-gen4

We don't want to try to push the hardware beyond it's capabilities,
so check the pixel clock against the display core clock limit. Do
it for pre-gen4 for now since that's where we alread have the double
wide pixel clock limit check.

Let's assume that when double wide mode is enabled the max
pixel clock limit is also doubled.

FIXME: panel fitter downscaling probably affects the limit on
non-pch platforms too, so we'd need another version of
ilk_pipe_pixel_rate() to figure that out.

FIXME: should check the limits on all platforms. Also sprites
affect the max allowed pixel rate on some platforms, so we need
to eventually tie all the planes and pipes into one check in
the future. But we need plane state pre-compute before that can
happen.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_display.c
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