Fixes reclocking failure on some chips where we attempted to set PDAEMON
to PLL mode.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
clk0 = calc_div(dev, clk, clk0, freq, &div1D);
/* see if we can get any closer using PLLs */
clk0 = calc_div(dev, clk, clk0, freq, &div1D);
/* see if we can get any closer using PLLs */
+ if (clk0 != freq && (0x00004387 & (1 << clk))) {
if (clk < 7)
clk1 = calc_pll(dev, clk, freq, &info->coef);
else
if (clk < 7)
clk1 = calc_pll(dev, clk, freq, &info->coef);
else