- /* gpios could be shared on router platforms
- * ignore reservation if it's high priority (e.g., test apps)
- */
- if ((priority != GPIO_HI_PRIORITY) &&
- (BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) {
- mask = priority ? (si_gpioreservation & mask) :
- ((si_gpioreservation | mask) & ~(si_gpioreservation));
- val &= mask;
- }
-
- regoff = OFFSETOF(chipcregs_t, gpioouten);
- return si_corereg(sih, SI_CC_IDX, regoff, mask, val);
-}
-
-/* mask&set gpio output bits */
-uint32 si_gpioout(si_t *sih, uint32 mask, uint32 val, u8 priority)
-{
- uint regoff;
-
- regoff = 0;
-
- /* gpios could be shared on router platforms
- * ignore reservation if it's high priority (e.g., test apps)
- */
- if ((priority != GPIO_HI_PRIORITY) &&
- (BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) {
- mask = priority ? (si_gpioreservation & mask) :
- ((si_gpioreservation | mask) & ~(si_gpioreservation));
- val &= mask;
- }
-
- regoff = OFFSETOF(chipcregs_t, gpioout);
- return si_corereg(sih, SI_CC_IDX, regoff, mask, val);
-}
-
-/* reserve one gpio */
-uint32 si_gpioreserve(si_t *sih, uint32 gpio_bitmask, u8 priority)
-{
- si_info_t *sii;
-
- sii = SI_INFO(sih);
-
- /* only cores on SI_BUS share GPIO's and only applcation users need to
- * reserve/release GPIO
- */
- if ((BUSTYPE(sih->bustype) != SI_BUS) || (!priority)) {
- ASSERT((BUSTYPE(sih->bustype) == SI_BUS) && (priority));
- return 0xffffffff;
- }
- /* make sure only one bit is set */
- if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
- ASSERT((gpio_bitmask)
- && !((gpio_bitmask) & (gpio_bitmask - 1)));
- return 0xffffffff;
- }
-
- /* already reserved */
- if (si_gpioreservation & gpio_bitmask)
- return 0xffffffff;
- /* set reservation */
- si_gpioreservation |= gpio_bitmask;
-
- return si_gpioreservation;
-}
-
-/* release one gpio */
-/*
- * releasing the gpio doesn't change the current value on the GPIO last write value
- * persists till some one overwrites it
- */
-
-uint32 si_gpiorelease(si_t *sih, uint32 gpio_bitmask, u8 priority)
-{
- si_info_t *sii;
-
- sii = SI_INFO(sih);
-
- /* only cores on SI_BUS share GPIO's and only applcation users need to
- * reserve/release GPIO
- */
- if ((BUSTYPE(sih->bustype) != SI_BUS) || (!priority)) {
- ASSERT((BUSTYPE(sih->bustype) == SI_BUS) && (priority));
- return 0xffffffff;
- }
- /* make sure only one bit is set */
- if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
- ASSERT((gpio_bitmask)
- && !((gpio_bitmask) & (gpio_bitmask - 1)));
- return 0xffffffff;
- }
-
- /* already released */
- if (!(si_gpioreservation & gpio_bitmask))
- return 0xffffffff;
-
- /* clear reservation */
- si_gpioreservation &= ~gpio_bitmask;
-
- return si_gpioreservation;
-}
-
-/* return the current gpioin register value */
-uint32 si_gpioin(si_t *sih)
-{
- si_info_t *sii;
- uint regoff;
-
- sii = SI_INFO(sih);
- regoff = 0;
-
- regoff = OFFSETOF(chipcregs_t, gpioin);
- return si_corereg(sih, SI_CC_IDX, regoff, 0, 0);
-}
-
-/* mask&set gpio interrupt polarity bits */
-uint32 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val, u8 priority)
-{
- si_info_t *sii;
- uint regoff;
-
- sii = SI_INFO(sih);
- regoff = 0;
-
- /* gpios could be shared on router platforms */
- if ((BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) {
- mask = priority ? (si_gpioreservation & mask) :
- ((si_gpioreservation | mask) & ~(si_gpioreservation));
- val &= mask;
- }
-
- regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
- return si_corereg(sih, SI_CC_IDX, regoff, mask, val);
-}
-
-/* mask&set gpio interrupt mask bits */
-uint32 si_gpiointmask(si_t *sih, uint32 mask, uint32 val, u8 priority)
-{
- si_info_t *sii;
- uint regoff;
-
- sii = SI_INFO(sih);
- regoff = 0;
-
- /* gpios could be shared on router platforms */
- if ((BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) {
- mask = priority ? (si_gpioreservation & mask) :
- ((si_gpioreservation | mask) & ~(si_gpioreservation));
- val &= mask;
- }
-
- regoff = OFFSETOF(chipcregs_t, gpiointmask);
- return si_corereg(sih, SI_CC_IDX, regoff, mask, val);
-}
-
-/* assign the gpio to an led */
-uint32 si_gpioled(si_t *sih, uint32 mask, uint32 val)
-{
- si_info_t *sii;
-
- sii = SI_INFO(sih);
- if (sih->ccrev < 16)
- return 0xffffffff;
-
- /* gpio led powersave reg */
- return si_corereg
- (sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask,
- val);
-}
-
-/* mask&set gpio timer val */
-uint32 si_gpiotimerval(si_t *sih, uint32 mask, uint32 gpiotimerval)
-{
- si_info_t *sii;
-
- sii = SI_INFO(sih);
-
- if (sih->ccrev < 16)
- return 0xffffffff;
-
- return si_corereg(sih, SI_CC_IDX,
- OFFSETOF(chipcregs_t, gpiotimerval), mask,
- gpiotimerval);
-}
-
-uint32 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val)
-{
- si_info_t *sii;
- uint offs;
-
- sii = SI_INFO(sih);
- if (sih->ccrev < 20)
- return 0xffffffff;
-
- offs =
- (updown ? OFFSETOF(chipcregs_t, gpiopulldown) :
- OFFSETOF(chipcregs_t, gpiopullup));
- return si_corereg(sih, SI_CC_IDX, offs, mask, val);
-}
-
-uint32 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val)
-{
- si_info_t *sii;
- uint offs;
-
- sii = SI_INFO(sih);
- if (sih->ccrev < 11)
- return 0xffffffff;
-
- if (regtype == GPIO_REGEVT)
- offs = OFFSETOF(chipcregs_t, gpioevent);
- else if (regtype == GPIO_REGEVT_INTMSK)
- offs = OFFSETOF(chipcregs_t, gpioeventintmask);
- else if (regtype == GPIO_REGEVT_INTPOL)
- offs = OFFSETOF(chipcregs_t, gpioeventintpolarity);
- else
- return 0xffffffff;
-
- return si_corereg(sih, SI_CC_IDX, offs, mask, val);
-}
-
-void *BCMATTACHFN(si_gpio_handler_register) (si_t *sih, uint32 event,
- bool level, gpio_handler_t cb,
- void *arg) {
- si_info_t *sii;
- gpioh_item_t *gi;
-
- ASSERT(event);
- ASSERT(cb != NULL);
-
- sii = SI_INFO(sih);
- if (sih->ccrev < 11)
- return NULL;
-
- gi = MALLOC(sii->osh, sizeof(gpioh_item_t));
- if (gi == NULL)
- return NULL;
-
- bzero(gi, sizeof(gpioh_item_t));
- gi->event = event;
- gi->handler = cb;
- gi->arg = arg;
- gi->level = level;
-
- gi->next = sii->gpioh_head;
- sii->gpioh_head = gi;
-
- return (void *)(gi);
-}
-
-void BCMATTACHFN(si_gpio_handler_unregister) (si_t *sih, void *gpioh)
-{
- si_info_t *sii;
- gpioh_item_t *p, *n;
-
- sii = SI_INFO(sih);
- if (sih->ccrev < 11)
- return;
-
- ASSERT(sii->gpioh_head != NULL);
- if ((void *)sii->gpioh_head == gpioh) {
- sii->gpioh_head = sii->gpioh_head->next;
- MFREE(sii->osh, gpioh, sizeof(gpioh_item_t));
- return;
- } else {
- p = sii->gpioh_head;
- n = p->next;
- while (n) {
- if ((void *)n == gpioh) {
- p->next = n->next;
- MFREE(sii->osh, gpioh, sizeof(gpioh_item_t));
- return;
- }
- p = n;
- n = n->next;
- }
- }
-
- ASSERT(0); /* Not found in list */
-}
-
-void si_gpio_handler_process(si_t *sih)
-{
- si_info_t *sii;
- gpioh_item_t *h;
- uint32 status;
- uint32 level = si_gpioin(sih);
- uint32 edge = si_gpioevent(sih, GPIO_REGEVT, 0, 0);
-
- sii = SI_INFO(sih);
- for (h = sii->gpioh_head; h != NULL; h = h->next) {
- if (h->handler) {
- status = (h->level ? level : edge);
-
- if (status & h->event)
- h->handler(status, h->arg);
- }
- }
-
- si_gpioevent(sih, GPIO_REGEVT, edge, edge); /* clear edge-trigger status */
-}
-
-uint32 si_gpio_int_enable(si_t *sih, bool enable)
-{
- si_info_t *sii;
- uint offs;
-
- sii = SI_INFO(sih);
- if (sih->ccrev < 11)
- return 0xffffffff;
-
- offs = OFFSETOF(chipcregs_t, intmask);
- return si_corereg
- (sih, SI_CC_IDX, offs, CI_GPIO, (enable ? CI_GPIO : 0));
-}
-
-/* Return the size of the specified SOCRAM bank */
-static uint
-socram_banksize(si_info_t *sii, sbsocramregs_t *regs, u8 index,
- u8 mem_type)
-{
- uint banksize, bankinfo;
- uint bankidx = index | (mem_type << SOCRAM_BANKIDX_MEMTYPE_SHIFT);
-
- ASSERT(mem_type <= SOCRAM_MEMTYPE_DEVRAM);