Fix PR15984 - Add flags to various opcodes

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 2810aaa5276ea93bbe92730299045da248ad7259..74f61a11bae5f8b9e83c67551d592cb85b56cdfc 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -2,6 +2,11 @@ Tue May 26 16:14:39 1998  Nick Clifton  <nickc@cygnus.com>
 
        * d30v-opc.c (d30v_format_table): Change definition of SHORT_B3
        and SHORT_B3b formats to use Rb instead of Ra.
 
        * d30v-opc.c (d30v_format_table): Change definition of SHORT_B3
        and SHORT_B3b formats to use Rb instead of Ra.

+       
+       Add FLAG_MUL16 to MUL2XH opcode.
+
+       Add FLAG_ADDSUBppp to SRC and SATHp opcodes to implement extension
+       to existing 1.1.1 parallelisation prohibition procedure.

 
 Fri May 22 16:00:00 1998  Doug Evans  <devans@canuck.cygnus.com>
 
 
 Fri May 22 16:00:00 1998  Doug Evans  <devans@canuck.cygnus.com>
 

diff --git a/opcodes/d30v-opc.c b/opcodes/d30v-opc.c
index 9d27b13de430ed04234c6843154e37d6c48d2cd2..ab6cc65fa94b23d85d5ea5ebe3f672a387945b7b 100644 (file)
--- a/opcodes/d30v-opc.c
+++ b/opcodes/d30v-opc.c
@@ -279,7 +279,7 @@ const struct d30v_opcode d30v_opcode_table[] = {
   { "mulhxhl", IALU2, 0x6, { SHORT_A }, IU, FLAG_MUL16, 0, 0 },
   { "mulhxhh", IALU2, 0x7, { SHORT_A }, IU, FLAG_MUL16, 0, 0 },
   { "mulx", IALU2, 0x18, { SHORT_AA }, IU, FLAG_MUL32, 0, 0 },
   { "mulhxhl", IALU2, 0x6, { SHORT_A }, IU, FLAG_MUL16, 0, 0 },
   { "mulhxhh", IALU2, 0x7, { SHORT_A }, IU, FLAG_MUL16, 0, 0 },
   { "mulx", IALU2, 0x18, { SHORT_AA }, IU, FLAG_MUL32, 0, 0 },

-  { "mulx2h", IALU2, 0x1, { SHORT_A2 }, IU, FLAG_MUL32, 0, 0 },
+  { "mulx2h", IALU2, 0x1, { SHORT_A2 }, IU, FLAG_MUL32 | FLAG_MUL16, 0, 0 },

   { "mulxs", IALU2, 0x19, { SHORT_AA }, IU, FLAG_MUL32, 0, 0 },
   { "mvfacc", IALU2, 0x1f, { SHORT_RA }, IU, 0, 0, 0 },
   { "mvfsys", BRA, 0x1e, { SHORT_C1 }, MU, FLAG_ALL, FLAG_ALL, 0 },
   { "mulxs", IALU2, 0x19, { SHORT_AA }, IU, FLAG_MUL32, 0, 0 },
   { "mvfacc", IALU2, 0x1f, { SHORT_RA }, IU, 0, 0, 0 },
   { "mvfsys", BRA, 0x1e, { SHORT_C1 }, MU, FLAG_ALL, FLAG_ALL, 0 },


@@ -298,15 +298,15 @@ const struct d30v_opcode d30v_opcode_table[] = {
   { "rtd", BRA, 0xa, { SHORT_NONE }, MU, 0, 0, 0 },
   { "sat", IALU2, 0x8, { SHORT_A5 }, IU, 0, 0, 0 },
   { "sat2h", IALU2, 0x9, { SHORT_A5 }, IU, 0, 0, 0 },
   { "rtd", BRA, 0xa, { SHORT_NONE }, MU, 0, 0, 0 },
   { "sat", IALU2, 0x8, { SHORT_A5 }, IU, 0, 0, 0 },
   { "sat2h", IALU2, 0x9, { SHORT_A5 }, IU, 0, 0, 0 },

-  { "sathl", IALU2, 0x1c, { SHORT_A5 }, IU, 0, 0, 0 },
-  { "sathh", IALU2, 0x1d, { SHORT_A5 }, IU, 0, 0, 0 },
+  { "sathl", IALU2, 0x1c, { SHORT_A5 }, IU, FLAG_ADDSUBppp, 0, 0 },
+  { "sathh", IALU2, 0x1d, { SHORT_A5 }, IU, FLAG_ADDSUBppp, 0, 0 },

   { "satz", IALU2, 0xa, { SHORT_A5 }, IU, 0, 0, 0 },
   { "satz2h", IALU2, 0xb, { SHORT_A5 }, IU, 0, 0, 0 },
   { "sra", LOGIC, 0x10, { SHORT_A }, EITHER, 0, 0, 0 },
   { "sra2h", LOGIC, 0x11, { SHORT_A }, EITHER, 0, 0, 0 },
   { "srahh", LOGIC, 0x5, { SHORT_A }, EITHER, 0, 0, 0 },
   { "srahl", LOGIC, 0x4, { SHORT_A }, EITHER, 0, 0, 0 },
   { "satz", IALU2, 0xa, { SHORT_A5 }, IU, 0, 0, 0 },
   { "satz2h", IALU2, 0xb, { SHORT_A5 }, IU, 0, 0, 0 },
   { "sra", LOGIC, 0x10, { SHORT_A }, EITHER, 0, 0, 0 },
   { "sra2h", LOGIC, 0x11, { SHORT_A }, EITHER, 0, 0, 0 },
   { "srahh", LOGIC, 0x5, { SHORT_A }, EITHER, 0, 0, 0 },
   { "srahl", LOGIC, 0x4, { SHORT_A }, EITHER, 0, 0, 0 },

-  { "src", LOGIC, 0x16, { SHORT_A }, EITHER, 0, 0, 0 },
+  { "src", LOGIC, 0x16, { SHORT_A }, EITHER, FLAG_ADDSUBppp, 0, 0 },

   { "srl", LOGIC, 0x12, { SHORT_A }, EITHER, 0, 0, 0 },
   { "srl2h", LOGIC, 0x13, { SHORT_A }, EITHER, 0, 0, 0 },
   { "srlhh", LOGIC, 0x7, { SHORT_A }, EITHER, 0, 0, 0 },
   { "srl", LOGIC, 0x12, { SHORT_A }, EITHER, 0, 0, 0 },
   { "srl2h", LOGIC, 0x13, { SHORT_A }, EITHER, 0, 0, 0 },
   { "srlhh", LOGIC, 0x7, { SHORT_A }, EITHER, 0, 0, 0 },