-{ "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, 0, 0, v9 }, /* rdpr %priv,r */
-{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0), "1,2,!", 0, 0, 0, v9 }, /* wrpr r1,r2,%priv */
-{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|SIMM13(~0), "1,!", 0, 0, 0, v9 }, /* wrpr r1,%priv */
-{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "1,i,!", 0, 0, 0, v9 }, /* wrpr r1,i,%priv */
-{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "i,1,!", F_ALIAS, 0, 0, v9 }, /* wrpr i,r1,%priv */
-{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RS1(~0), "i,!", 0, 0, 0, v9 }, /* wrpr i,%priv */
-
-{ "rdhpr", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|SIMM13(~0), "$,d", 0, 0, 0, v9 }, /* rdhpr %hpriv,r */
-{ "wrhpr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0), "1,2,%", 0, 0, 0, v9 }, /* wrhpr r1,r2,%hpriv */
-{ "wrhpr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|SIMM13(~0), "1,%", 0, 0, 0, v9 }, /* wrhpr r1,%hpriv */
-{ "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "1,i,%", 0, 0, 0, v9 }, /* wrhpr r1,i,%hpriv */
-{ "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "i,1,%", F_ALIAS, 0, 0, v9 }, /* wrhpr i,r1,%hpriv */
-{ "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RS1(~0), "i,%", 0, 0, 0, v9 }, /* wrhpr i,%hpriv */
+/* Instructions to read and write from/to privileged registers. */
+
+#define rdpr(reg,hwcap,hwcap2,arch) \
+ { "rdpr", F3(2, 0x2a, 0)|RS1((reg)), F3(~2, ~0x2a, ~0)|RS1(~(reg))|SIMM13(~0),"?,d", 0, (hwcap), (hwcap2), (arch) } /* rdpr %priv,r */
+
+rdpr (0, 0, 0, v9), /* rdpr %tpc,r */
+rdpr (1, 0, 0, v9), /* rdpr %tnpc,r */
+rdpr (2, 0, 0, v9), /* rdpr %tstate,r */
+rdpr (3, 0, 0, v9), /* rdpr %tt,r */
+rdpr (4, 0, 0, v9), /* rdpr %tick,r */
+rdpr (5, 0, 0, v9), /* rdpr %tba,r */
+rdpr (6, 0, 0, v9), /* rdpr %pstate,r */
+rdpr (7, 0, 0, v9), /* rdpr %tl,r */
+rdpr (8, 0, 0, v9), /* rdpr %pil,r */
+rdpr (9, 0, 0, v9), /* rdpr %cwp,r */
+rdpr (10, 0, 0, v9), /* rdpr %cansave,r */
+rdpr (11, 0, 0, v9), /* rdpr %canrestore,r */
+rdpr (12, 0, 0, v9), /* rdpr %cleanwin,r */
+rdpr (13, 0, 0, v9), /* rdpr %otherwin,r */
+rdpr (14, 0, 0, v9), /* rdpr %wstate,r */
+rdpr (15, 0, 0, v9), /* rdpr %fq,r */
+rdpr (16, 0, 0, v9), /* rdpr %gl,r */
+rdpr (23, 0, HWCAP2_SPARC5, v9m), /* rdpr %pmcdper,r */
+rdpr (31, 0, 0, v9), /* rdpr %ver,r */
+
+#define wrpr(reg,hwcap,hwcap2,arch) \
+{ "wrpr", F3(2, 0x32, 0)|RD((reg)), F3(~2, ~0x32, ~0)|RD(~(reg)), "1,2,!", 0, (hwcap), (hwcap2), (arch) }, /* wrpr r1,r2,%priv */ \
+{ "wrpr", F3(2, 0x32, 0)|RD((reg)), F3(~2, ~0x32, ~0)|RD(~(reg))|SIMM13(~0), "1,!", 0, (hwcap), (hwcap2), (arch) }, /* wrpr r1,%priv */ \
+{ "wrpr", F3(2, 0x32, 1)|RD((reg)), F3(~2, ~0x32, ~1)|RD(~(reg)), "1,i,!", 0, (hwcap), (hwcap2), (arch) }, /* wrpr r1,i,%priv */ \
+{ "wrpr", F3(2, 0x32, 1)|RD((reg)), F3(~2, ~0x32, ~1)|RD(~(reg)), "i,1,!", F_ALIAS, (hwcap), (hwcap2), (arch) }, /* wrpr i,r1,%priv */ \
+{ "wrpr", F3(2, 0x32, 1)|RD((reg)), F3(~2, ~0x32, ~1)|RD(~(reg))|RS1(~0), "i,!", 0, (hwcap), (hwcap2), (arch) } /* wrpr i,%priv */
+
+wrpr (0, 0, 0, v9), /* wrpr ...,%tpc */
+wrpr (1, 0, 0, v9), /* wrpr ...,%tnpc */
+wrpr (2, 0, 0, v9), /* wrpr ...,%tstate */
+wrpr (3, 0, 0, v9), /* wrpr ...,%tt */
+wrpr (4, 0, 0, v9), /* wrpr ...,%tick */
+wrpr (5, 0, 0, v9), /* wrpr ...,%tba */
+wrpr (6, 0, 0, v9), /* wrpr ...,%pstate */
+wrpr (7, 0, 0, v9), /* wrpr ...,%tl */
+wrpr (8, 0, 0, v9), /* wrpr ...,%pil */
+wrpr (9, 0, 0, v9), /* wrpr ...,%cwp */
+wrpr (10, 0, 0, v9), /* wrpr ...,%cansave */
+wrpr (11, 0, 0, v9), /* wrpr ...,%canrestore */
+wrpr (12, 0, 0, v9), /* wrpr ...,%cleanwin */
+wrpr (13, 0, 0, v9), /* wrpr ...,%otherwin */
+wrpr (14, 0, 0, v9), /* wrpr ...,%wstate */
+wrpr (15, 0, 0, v9), /* wrpr ...,%fq */
+wrpr (16, 0, 0, v9), /* wrpr ...,%gl */
+wrpr (23, 0, HWCAP2_SPARC5, v9m), /* wdpr ...,%pmcdper */
+wrpr (31, 0, 0, v9), /* wrpr ...,%ver */
+
+/* Instructions to read and write from/to hyperprivileged
+ registers. */
+
+#define rdhpr(reg,hwcap,hwcap2,arch) \
+{ "rdhpr", F3(2, 0x29, 0)|RS1((reg)), F3(~2, ~0x29, ~0)|RS1(~(reg))|SIMM13(~0), "$,d", 0, (hwcap), (hwcap2), (arch) }
+
+rdhpr (0, HWCAP_VIS, 0, v9a), /* rdhpr %hpstate,r */
+rdhpr (1, HWCAP_VIS, 0, v9a), /* rdhpr %htstate,r */
+rdhpr (3, HWCAP_VIS, 0, v9a), /* rdhpr %hintp,r */
+rdhpr (5, HWCAP_VIS, 0, v9a), /* rdhpr %htba,r */
+rdhpr (6, HWCAP_VIS, 0, v9a), /* rdhpr %hver,r */
+rdhpr (23, 0, HWCAP2_SPARC5, v9m), /* rdhpr %hmcdper,r */
+rdhpr (24, 0, HWCAP2_SPARC5, v9m), /* rdhpr %hmcddfr,r */
+rdhpr (27, 0, HWCAP2_SPARC5, v9m), /* rdhpr %hva_mask_nz,r */
+rdhpr (28, HWCAP_VIS, 0, v9a), /* rdhpr %hstick_offset,r */
+rdhpr (29, HWCAP_VIS, 0, v9a), /* rdhpar %hstick_enable,r */
+rdhpr (31, HWCAP_VIS, 0, v9a), /* rdhpr %hstick_cmpr,r */
+
+#define wrhpr(reg,hwcap,hwcap2,arch) \
+{ "wrhpr", F3(2, 0x33, 0)|RD((reg)), F3(~2, ~0x33, ~0)|RD(~(reg)),"1,2,%", 0, (hwcap), (hwcap2), (arch) }, /* wrhpr r1,r2,%hpriv */ \
+{ "wrhpr", F3(2, 0x33, 0)|RD((reg)), F3(~2, ~0x33, ~0)|RD(~(reg))|SIMM13(~0), "1,%", 0, (hwcap), (hwcap2), (arch) }, /* wrhpr r1,%hpriv */ \
+{ "wrhpr", F3(2, 0x33, 1)|RD((reg)), F3(~2, ~0x33, ~1)|RD(~(reg)), "1,i,%", 0, (hwcap), (hwcap2), (arch) }, /* wrhpr r1,i,%hpriv */ \
+{ "wrhpr", F3(2, 0x33, 1)|RD((reg)), F3(~2, ~0x33, ~1)|RD(~(reg)), "i,1,%", F_ALIAS, (hwcap), (hwcap2), (arch) }, /* wrhpr i,r1,%hpriv */ \
+{ "wrhpr", F3(2, 0x33, 1)|RD((reg)), F3(~2, ~0x33, ~1)|RD(~(reg))|RS1(~0), "i,%", 0, (hwcap), (hwcap2), (arch) } /* wrhpr i,%hpriv */
+
+wrhpr (0, HWCAP_VIS, 0, v9a), /* wrhpr ...,%hpstate */
+wrhpr (1, HWCAP_VIS, 0, v9a), /* wrhpr ...,%htstate */
+wrhpr (3, HWCAP_VIS, 0, v9a), /* wrhpr ...,%hintp */
+wrhpr (5, HWCAP_VIS, 0, v9a), /* wrhpr ...,%htba */
+wrhpr (23, 0, HWCAP2_SPARC5, v9m), /* wrhpr ...,%hmcdper */
+wrhpr (24, 0, HWCAP2_SPARC5, v9m), /* wrhpr ...,%hmcddfr */
+wrhpr (27, 0, HWCAP2_SPARC5, v9m), /* wrhpr ...,%hva_mask_nz */
+wrhpr (28, HWCAP_VIS, 0, v9a), /* wrhpr ...,%hstick_offset */
+wrhpr (29, HWCAP_VIS, 0, v9a), /* wrhpr ...,%hstick_enable */
+wrhpr (31, HWCAP_VIS, 0, v9a), /* wrhpr ...,%hstick_cmpr */