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Fixed some bugs in handling vxworks960 -- not reading registers right,
author
Ken Raeburn
<raeburn@cygnus>
Thu, 9 Jul 1992 23:40:01 +0000
(23:40 +0000)
committer
Ken Raeburn
<raeburn@cygnus>
Thu, 9 Jul 1992 23:40:01 +0000
(23:40 +0000)
trying to use FP regs (not supported by target), botching IP.
gdb/tm-i960.h
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diff --git
a/gdb/tm-i960.h
b/gdb/tm-i960.h
index 561b06ae1d7d490da8d5e355b6529d10d7cf7ddc..bbe4d89c90c2c6aaae96c09d386fc62cf3f9f079 100644
(file)
--- a/
gdb/tm-i960.h
+++ b/
gdb/tm-i960.h
@@
-94,7
+94,7
@@
extern CORE_ADDR saved_pc_after_call ();
/* 8 */ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",\
/* 16 */ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", \
/* 24 */ "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp", \
/* 8 */ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",\
/* 16 */ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", \
/* 24 */ "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp", \
- /* 32 */ "pc
", "ac", "ip", "tc
", "fp0", "fp1", "fp2", "fp3",\
+ /* 32 */ "pc
w", "ac", "tc", "ip
", "fp0", "fp1", "fp2", "fp3",\
}
/* Register numbers of various important registers (used to index
}
/* Register numbers of various important registers (used to index
@@
-110,8
+110,8
@@
extern CORE_ADDR saved_pc_after_call ();
#define FP_REGNUM 31 /* Contains address of executing stack frame */
#define PCW_REGNUM 32 /* process control word */
#define ACW_REGNUM 33 /* arithmetic control word */
#define FP_REGNUM 31 /* Contains address of executing stack frame */
#define PCW_REGNUM 32 /* process control word */
#define ACW_REGNUM 33 /* arithmetic control word */
-#define
IP_REGNUM 34 /* instruction pointer
*/
-#define
TCW_REGNUM 35 /* trace control word
*/
+#define
TCW_REGNUM 34 /* trace control word
*/
+#define
IP_REGNUM 35 /* instruction pointer
*/
#define FP0_REGNUM 36 /* First floating point register */
/* Some registers have more than one name */
#define FP0_REGNUM 36 /* First floating point register */
/* Some registers have more than one name */
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