* sim/mips/interp.c: Correct some HASFPU problems.

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 29f7d03431e4c5d9afced1e8017d406962e8d960..058b2bd5e5cfc76017942ad3e281133183454411 100644 (file)
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,7 @@
+Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
+
+       * interp.c: Correct some HASFPU problems.
+

 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 
        * configure: Regenerated to track ../common/aclocal.m4 changes.
 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 
        * configure: Regenerated to track ../common/aclocal.m4 changes.

diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index 879e79eee0fd4805057523a4b9bd4e14b3c9e824..3a98883e3bfe1e23078b0795e6bed79d08269291 100644 (file)
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -886,8 +886,10 @@ sim_open (kind, cb, abfd, argv)
     for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++) {
       if (rn < 32)
        register_widths[rn] = GPRLEN;
     for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++) {
       if (rn < 32)
        register_widths[rn] = GPRLEN;

+#if defined(HASFPU)

       else if ((rn >= FGRIDX) && (rn < (FGRIDX + 32)))
        register_widths[rn] = GPRLEN;
       else if ((rn >= FGRIDX) && (rn < (FGRIDX + 32)))
        register_widths[rn] = GPRLEN;

+#endif

       else if ((rn >= 33) && (rn <= 37))
        register_widths[rn] = GPRLEN;
       else if ((rn == SRIDX) || (rn == FCR0IDX) || (rn == FCR31IDX) || ((rn >= 72) && (rn <= 89)))
       else if ((rn >= 33) && (rn <= 37))
        register_widths[rn] = GPRLEN;
       else if ((rn == SRIDX) || (rn == FCR0IDX) || (rn == FCR31IDX) || ((rn >= 72) && (rn <= 89)))


@@ -2015,6 +2017,7 @@ mips16_entry (insn)
 
       SP += 32;
 
 
       SP += 32;
 

+#if defined(HASFPU)

       if (aregs == 5)
        {
          FGR[0] = WORD64LO (GPR[4]);
       if (aregs == 5)
        {
          FGR[0] = WORD64LO (GPR[4]);


@@ -2027,6 +2030,7 @@ mips16_entry (insn)
          fpr_state[0] = fmt_uninterpreted;
          fpr_state[1] = fmt_uninterpreted;
        }
          fpr_state[0] = fmt_uninterpreted;
          fpr_state[1] = fmt_uninterpreted;
        }

+#endif /* defined(HASFPU) */

 
       PC = RA;
     }
 
       PC = RA;
     }


@@ -3987,16 +3991,18 @@ COP_SW(coproc_num,coproc_reg)
      int coproc_num, coproc_reg;
 {
   unsigned int value = 0;
      int coproc_num, coproc_reg;
 {
   unsigned int value = 0;

-  FP_formats hold;

 
   switch (coproc_num) {
 #if defined(HASFPU)
     case 1:
 #if 1
 
   switch (coproc_num) {
 #if defined(HASFPU)
     case 1:
 #if 1

-     hold = fpr_state[coproc_reg];
-     fpr_state[coproc_reg] = fmt_word;
-     value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
-     fpr_state[coproc_reg] = hold;
+      {
+        FP_formats hold;
+        hold = fpr_state[coproc_reg];
+        fpr_state[coproc_reg] = fmt_word;
+        value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
+        fpr_state[coproc_reg] = hold;
+      }

 #else
 #if 1
      value = (unsigned int)ValueFPR(coproc_reg,fpr_state[coproc_reg]);
 #else
 #if 1
      value = (unsigned int)ValueFPR(coproc_reg,fpr_state[coproc_reg]);


@@ -4410,7 +4416,11 @@ sim_engine_run (sd, next_cpu_nr, siggnal)
               printf("pending_slot_value[%d] = 0x%s\n",index,pr_addr(pending_slot_value[index]));
 #endif /* DEBUG */
               if (pending_slot_reg[index] == COCIDX) {
               printf("pending_slot_value[%d] = 0x%s\n",index,pr_addr(pending_slot_value[index]));
 #endif /* DEBUG */
               if (pending_slot_reg[index] == COCIDX) {

+#if defined(HASFPU)

                 SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
                 SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));

+#else
+                ;
+#endif

               } else {
                 registers[pending_slot_reg[index]] = pending_slot_value[index];
 #if defined(HASFPU)
               } else {
                 registers[pending_slot_reg[index]] = pending_slot_value[index];
 #if defined(HASFPU)