+void __init orion_gpio_init(int gpio_base, int ngpio,
+ u32 base, int mask_offset, int secondary_irq_base)
+{
+ struct orion_gpio_chip *ochip;
+ int i;
+
+ if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
+ return;
+
+ ochip = orion_gpio_chips + orion_gpio_chip_count;
+ ochip->chip.label = "orion_gpio";
+ ochip->chip.request = orion_gpio_request;
+ ochip->chip.direction_input = orion_gpio_direction_input;
+ ochip->chip.get = orion_gpio_get;
+ ochip->chip.direction_output = orion_gpio_direction_output;
+ ochip->chip.set = orion_gpio_set;
+ ochip->chip.to_irq = orion_gpio_to_irq;
+ ochip->chip.base = gpio_base;
+ ochip->chip.ngpio = ngpio;
+ ochip->chip.can_sleep = 0;
+ spin_lock_init(&ochip->lock);
+ ochip->base = (void __iomem *)base;
+ ochip->valid_input = 0;
+ ochip->valid_output = 0;
+ ochip->mask_offset = mask_offset;
+ ochip->secondary_irq_base = secondary_irq_base;
+
+ gpiochip_add(&ochip->chip);
+
+ orion_gpio_chip_count++;
+
+ /*
+ * Mask and clear GPIO interrupts.
+ */
+ writel(0, GPIO_EDGE_CAUSE(ochip));
+ writel(0, GPIO_EDGE_MASK(ochip));
+ writel(0, GPIO_LEVEL_MASK(ochip));
+
+ for (i = 0; i < ngpio; i++) {
+ unsigned int irq = secondary_irq_base + i;
+
+ set_irq_chip(irq, &orion_gpio_irq_chip);
+ set_irq_handler(irq, handle_level_irq);
+ set_irq_chip_data(irq, ochip);
+ irq_desc[irq].status |= IRQ_LEVEL;
+ set_irq_flags(irq, IRQF_VALID);
+ }
+}
+