- reference SRs by names where possible, not by numbers;
- get rid of __stringify around SR names where possible;
- remove unneeded SR names from asm/regs.h;
- add SREG_ prefix to remaining SR names;
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
20 files changed:
/* 'reset' window registers */
movi a4, 1
/* 'reset' window registers */
movi a4, 1
rsync
movi a4, 0x00040000
rsync
movi a4, 0x00040000
rsync
/* copy the loader to its address
rsync
/* copy the loader to its address
"l32i %0, %2, 0 \n\t"
"add %0, %0, %1 \n\t"
"s32i %0, %2, 0 \n\t"
"l32i %0, %2, 0 \n\t"
"add %0, %0, %1 \n\t"
"s32i %0, %2, 0 \n\t"
- "wsr a15, "__stringify(PS)" \n\t"
"rsync \n"
: "=&a" (vval)
: "a" (i), "a" (v)
"rsync \n"
: "=&a" (vval)
: "a" (i), "a" (v)
"l32i %0, %2, 0 \n\t"
"sub %0, %0, %1 \n\t"
"s32i %0, %2, 0 \n\t"
"l32i %0, %2, 0 \n\t"
"sub %0, %0, %1 \n\t"
"s32i %0, %2, 0 \n\t"
- "wsr a15, "__stringify(PS)" \n\t"
"rsync \n"
: "=&a" (vval)
: "a" (i), "a" (v)
"rsync \n"
: "=&a" (vval)
: "a" (i), "a" (v)
"l32i %0, %2, 0 \n\t"
"add %0, %0, %1 \n\t"
"s32i %0, %2, 0 \n\t"
"l32i %0, %2, 0 \n\t"
"add %0, %0, %1 \n\t"
"s32i %0, %2, 0 \n\t"
- "wsr a15, "__stringify(PS)" \n\t"
"rsync \n"
: "=&a" (vval)
: "a" (i), "a" (v)
"rsync \n"
: "=&a" (vval)
: "a" (i), "a" (v)
"l32i %0, %2, 0 \n\t"
"sub %0, %0, %1 \n\t"
"s32i %0, %2, 0 \n\t"
"l32i %0, %2, 0 \n\t"
"sub %0, %0, %1 \n\t"
"s32i %0, %2, 0 \n\t"
- "wsr a15, "__stringify(PS)" \n\t"
"rsync \n"
: "=&a" (vval)
: "a" (i), "a" (v)
"rsync \n"
: "=&a" (vval)
: "a" (i), "a" (v)
"xor %1, %4, %3 \n\t"
"and %0, %0, %4 \n\t"
"s32i %0, %2, 0 \n\t"
"xor %1, %4, %3 \n\t"
"and %0, %0, %4 \n\t"
"s32i %0, %2, 0 \n\t"
- "wsr a15, "__stringify(PS)" \n\t"
"rsync \n"
: "=&a" (vval), "=a" (mask)
: "a" (v), "a" (all_f), "1" (mask)
"rsync \n"
: "=&a" (vval), "=a" (mask)
: "a" (v), "a" (all_f), "1" (mask)
"l32i %0, %2, 0 \n\t"
"or %0, %0, %1 \n\t"
"s32i %0, %2, 0 \n\t"
"l32i %0, %2, 0 \n\t"
"or %0, %0, %1 \n\t"
"s32i %0, %2, 0 \n\t"
- "wsr a15, "__stringify(PS)" \n\t"
"rsync \n"
: "=&a" (vval)
: "a" (mask), "a" (v)
"rsync \n"
: "=&a" (vval)
: "a" (mask), "a" (v)
static inline u32 xtensa_get_cacheattr(void)
{
u32 r;
static inline u32 xtensa_get_cacheattr(void)
{
u32 r;
- asm volatile(" rsr %0, CACHEATTR" : "=a"(r));
+ asm volatile(" rsr %0, cacheattr" : "=a"(r));
"bne %0, %2, 1f \n\t"
"s32i %3, %1, 0 \n\t"
"1: \n\t"
"bne %0, %2, 1f \n\t"
"s32i %3, %1, 0 \n\t"
"1: \n\t"
- "wsr a15, "__stringify(PS)" \n\t"
"rsync \n\t"
: "=&a" (old)
: "a" (p), "a" (old), "r" (new)
"rsync \n\t"
: "=&a" (old)
: "a" (p), "a" (old), "r" (new)
__asm__ __volatile__("rsil a15, "__stringify(LOCKLEVEL)"\n\t"
"l32i %0, %1, 0 \n\t"
"s32i %2, %1, 0 \n\t"
__asm__ __volatile__("rsil a15, "__stringify(LOCKLEVEL)"\n\t"
"l32i %0, %1, 0 \n\t"
"s32i %2, %1, 0 \n\t"
- "wsr a15, "__stringify(PS)" \n\t"
"rsync \n\t"
: "=&a" (tmp)
: "a" (m), "a" (val)
"rsync \n\t"
: "=&a" (tmp)
: "a" (m), "a" (val)
#if XCHAL_HAVE_CP
#define RSR_CPENABLE(x) do { \
#if XCHAL_HAVE_CP
#define RSR_CPENABLE(x) do { \
- __asm__ __volatile__("rsr %0," __stringify(CPENABLE) : "=a" (x)); \
+ __asm__ __volatile__("rsr %0, cpenable" : "=a" (x)); \
} while(0);
#define WSR_CPENABLE(x) do { \
} while(0);
#define WSR_CPENABLE(x) do { \
- __asm__ __volatile__("wsr %0," __stringify(CPENABLE) "; rsync" \
- :: "a" (x)); \
+ __asm__ __volatile__("wsr %0, cpenable; rsync" :: "a" (x)); \
} while(0);
#endif /* XCHAL_HAVE_CP */
} while(0);
#endif /* XCHAL_HAVE_CP */
static __inline__ u32 xtensa_get_ccount(void)
{
u32 ccount;
static __inline__ u32 xtensa_get_ccount(void)
{
u32 ccount;
- asm volatile ("rsr %0, 234; # CCOUNT\n" : "=r" (ccount));
+ asm volatile ("rsr %0, ccount\n" : "=r" (ccount));
static inline unsigned long arch_local_save_flags(void)
{
unsigned long flags;
static inline unsigned long arch_local_save_flags(void)
{
unsigned long flags;
- asm volatile("rsr %0,"__stringify(PS) : "=a" (flags));
+ asm volatile("rsr %0, ps" : "=a" (flags));
static inline void arch_local_irq_restore(unsigned long flags)
{
static inline void arch_local_irq_restore(unsigned long flags)
{
- asm volatile("wsr %0, "__stringify(PS)" ; rsync"
+ asm volatile("wsr %0, ps; rsync"
:: "a" (flags) : "memory");
}
:: "a" (flags) : "memory");
}
static inline void set_rasid_register (unsigned long val)
{
static inline void set_rasid_register (unsigned long val)
{
- __asm__ __volatile__ (" wsr %0, "__stringify(RASID)"\n\t"
+ __asm__ __volatile__ (" wsr %0, rasid\n\t"
" isync\n" : : "a" (val));
}
static inline unsigned long get_rasid_register (void)
{
unsigned long tmp;
" isync\n" : : "a" (val));
}
static inline unsigned long get_rasid_register (void)
{
unsigned long tmp;
- __asm__ __volatile__ (" rsr %0,"__stringify(RASID)"\n\t" : "=a" (tmp));
+ __asm__ __volatile__ (" rsr %0, rasid\n\t" : "=a" (tmp));
-#define LBEG 0
-#define LEND 1
-#define LCOUNT 2
-#define SAR 3
-#define BR 4
-#define SCOMPARE1 12
-#define ACCHI 16
-#define ACCLO 17
-#define MR 32
-#define WINDOWBASE 72
-#define WINDOWSTART 73
-#define PTEVADDR 83
-#define RASID 90
-#define ITLBCFG 91
-#define DTLBCFG 92
-#define IBREAKENABLE 96
-#define DDR 104
-#define IBREAKA 128
-#define DBREAKA 144
-#define DBREAKC 160
-#define EPC 176
-#define EPC_1 177
-#define DEPC 192
-#define EPS 192
-#define EPS_1 193
-#define EXCSAVE 208
-#define EXCSAVE_1 209
-#define INTERRUPT 226
-#define INTENABLE 228
-#define PS 230
-#define THREADPTR 231
-#define EXCCAUSE 232
-#define DEBUGCAUSE 233
-#define CCOUNT 234
-#define PRID 235
-#define ICOUNT 236
-#define ICOUNTLEVEL 237
-#define EXCVADDR 238
-#define CCOMPARE 240
-#define MISC_SR 244
-
-/* Special names for read-only and write-only interrupt registers. */
-
-#define INTREAD 226
-#define INTSET 226
-#define INTCLEAR 227
+#define SREG_MR 32
+#define SREG_IBREAKA 128
+#define SREG_DBREAKA 144
+#define SREG_DBREAKC 160
+#define SREG_EPC 176
+#define SREG_EPS 192
+#define SREG_EXCSAVE 208
+#define SREG_CCOMPARE 240
+#define SREG_MISC 244
/* EXCCAUSE register fields */
/* EXCCAUSE register fields */
-#define WSR_CCOUNT(r) asm volatile ("wsr %0,"__stringify(CCOUNT) :: "a" (r))
-#define RSR_CCOUNT(r) asm volatile ("rsr %0,"__stringify(CCOUNT) : "=a" (r))
-#define WSR_CCOMPARE(x,r) asm volatile ("wsr %0,"__stringify(CCOMPARE)"+"__stringify(x) :: "a"(r))
-#define RSR_CCOMPARE(x,r) asm volatile ("rsr %0,"__stringify(CCOMPARE)"+"__stringify(x) : "=a"(r))
+#define WSR_CCOUNT(r) asm volatile ("wsr %0, ccount" :: "a" (r))
+#define RSR_CCOUNT(r) asm volatile ("rsr %0, ccount" : "=a" (r))
+#define WSR_CCOMPARE(x,r) asm volatile ("wsr %0,"__stringify(SREG_CCOMPARE)"+"__stringify(x) :: "a"(r))
+#define RSR_CCOMPARE(x,r) asm volatile ("rsr %0,"__stringify(SREG_CCOMPARE)"+"__stringify(x) : "=a"(r))
static inline unsigned long get_ccount (void)
{
static inline unsigned long get_ccount (void)
{
static inline void set_itlbcfg_register (unsigned long val)
{
static inline void set_itlbcfg_register (unsigned long val)
{
- __asm__ __volatile__("wsr %0, "__stringify(ITLBCFG)"\n\t" "isync\n\t"
+ __asm__ __volatile__("wsr %0, itlbcfg\n\t" "isync\n\t"
: : "a" (val));
}
static inline void set_dtlbcfg_register (unsigned long val)
{
: : "a" (val));
}
static inline void set_dtlbcfg_register (unsigned long val)
{
- __asm__ __volatile__("wsr %0, "__stringify(DTLBCFG)"; dsync\n\t"
+ __asm__ __volatile__("wsr %0, dtlbcfg; dsync\n\t"
: : "a" (val));
}
static inline void set_ptevaddr_register (unsigned long val)
{
: : "a" (val));
}
static inline void set_ptevaddr_register (unsigned long val)
{
- __asm__ __volatile__(" wsr %0, "__stringify(PTEVADDR)"; isync\n"
+ __asm__ __volatile__(" wsr %0, ptevaddr; isync\n"
: : "a" (val));
}
static inline unsigned long read_ptevaddr_register (void)
{
unsigned long tmp;
: : "a" (val));
}
static inline unsigned long read_ptevaddr_register (void)
{
unsigned long tmp;
- __asm__ __volatile__("rsr %0, "__stringify(PTEVADDR)"\n\t" : "=a" (tmp));
+ __asm__ __volatile__("rsr %0, ptevaddr\n\t" : "=a" (tmp));
s32i a7, a2, PT_AREG7
s32i a8, a2, PT_AREG8
s32i a7, a2, PT_AREG7
s32i a8, a2, PT_AREG8
- rsr a0, DEPC
- xsr a3, EXCSAVE_1
+ rsr a0, depc
+ xsr a3, excsave1
s32i a0, a2, PT_AREG2
s32i a3, a2, PT_AREG3
/* Keep value of SAR in a0 */
s32i a0, a2, PT_AREG2
s32i a3, a2, PT_AREG3
/* Keep value of SAR in a0 */
- rsr a0, SAR
- rsr a8, EXCVADDR # load unaligned memory address
+ rsr a0, sar
+ rsr a8, excvaddr # load unaligned memory address
/* Now, identify one of the following load/store instructions.
*
/* Now, identify one of the following load/store instructions.
*
/* Extract the instruction that caused the unaligned access. */
/* Extract the instruction that caused the unaligned access. */
- rsr a7, EPC_1 # load exception address
+ rsr a7, epc1 # load exception address
movi a3, ~3
and a3, a3, a7 # mask lower bits
movi a3, ~3
and a3, a3, a7 # mask lower bits
- rsr a5, LEND # check if we reached LEND
+ rsr a5, lend # check if we reached LEND
- rsr a5, LCOUNT # and LCOUNT != 0
+ rsr a5, lcount # and LCOUNT != 0
beqz a5, 1f
addi a5, a5, -1 # decrement LCOUNT and set
beqz a5, 1f
addi a5, a5, -1 # decrement LCOUNT and set
- rsr a7, LBEG # set PC to LBEGIN
- wsr a5, LCOUNT
+ rsr a7, lbeg # set PC to LBEGIN
+ wsr a5, lcount
-1: wsr a7, EPC_1 # skip load instruction
+1: wsr a7, epc1 # skip load instruction
extui a4, a4, INSN_T, 4 # extract target register
movi a5, .Lload_table
addx8 a4, a4, a5
extui a4, a4, INSN_T, 4 # extract target register
movi a5, .Lload_table
addx8 a4, a4, a5
- rsr a4, LEND # check if we reached LEND
+ rsr a4, lend # check if we reached LEND
- rsr a4, LCOUNT # and LCOUNT != 0
+ rsr a4, lcount # and LCOUNT != 0
beqz a4, 1f
addi a4, a4, -1 # decrement LCOUNT and set
beqz a4, 1f
addi a4, a4, -1 # decrement LCOUNT and set
- rsr a7, LBEG # set PC to LBEGIN
- wsr a4, LCOUNT
+ rsr a7, lbeg # set PC to LBEGIN
+ wsr a4, lcount
-1: wsr a7, EPC_1 # skip store instruction
+1: wsr a7, epc1 # skip store instruction
movi a4, ~3
and a4, a4, a8 # align memory address
movi a4, ~3
and a4, a4, a8 # align memory address
s32i a4, a3, EXC_TABLE_FIXUP
/* Restore working register */
s32i a4, a3, EXC_TABLE_FIXUP
/* Restore working register */
/* restore SAR and return */
/* restore SAR and return */
l32i a0, a2, PT_AREG0
l32i a2, a2, PT_AREG2
rfe
l32i a0, a2, PT_AREG0
l32i a2, a2, PT_AREG2
rfe
l32i a6, a2, PT_AREG6
l32i a5, a2, PT_AREG5
l32i a4, a2, PT_AREG4
l32i a6, a2, PT_AREG6
l32i a5, a2, PT_AREG5
l32i a4, a2, PT_AREG4
bbsi.l a2, PS_UM_BIT, 1f # jump if user mode
movi a0, _kernel_exception
bbsi.l a2, PS_UM_BIT, 1f # jump if user mode
movi a0, _kernel_exception
/* IO protection is currently unsupported. */
ENTRY(fast_io_protect)
/* IO protection is currently unsupported. */
ENTRY(fast_io_protect)
movi a0, unrecoverable_exception
callx0 a0
movi a0, unrecoverable_exception
callx0 a0
*/
ENTRY(fast_coprocessor_double)
*/
ENTRY(fast_coprocessor_double)
movi a0, unrecoverable_exception
callx0 a0
movi a0, unrecoverable_exception
callx0 a0
/* Save remaining registers a1-a3 and SAR */
/* Save remaining registers a1-a3 and SAR */
s32i a1, a2, PT_AREG1
s32i a3, a2, PT_SAR
mov a1, a2
s32i a1, a2, PT_AREG1
s32i a3, a2, PT_SAR
mov a1, a2
/* Find coprocessor number. Subtract first CP EXCCAUSE from EXCCAUSE */
/* Find coprocessor number. Subtract first CP EXCCAUSE from EXCCAUSE */
addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED
/* Set corresponding CPENABLE bit -> (sar:cp-index, a3: 1<<cp-index)*/
ssl a3 # SAR: 32 - coprocessor_number
movi a2, 1
addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED
/* Set corresponding CPENABLE bit -> (sar:cp-index, a3: 1<<cp-index)*/
ssl a3 # SAR: 32 - coprocessor_number
movi a2, 1
rsync
/* Retrieve previous owner. (a3 still holds CP number) */
rsync
/* Retrieve previous owner. (a3 still holds CP number) */
/* Note that only a0 and a1 were preserved. */
/* Note that only a0 and a1 were preserved. */
addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED
movi a0, coprocessor_owner
addx4 a0, a3, a0
addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED
movi a0, coprocessor_owner
addx4 a0, a3, a0
l32i a0, a1, PT_SAR
l32i a3, a1, PT_AREG3
l32i a2, a1, PT_AREG2
l32i a0, a1, PT_SAR
l32i a3, a1, PT_AREG3
l32i a2, a1, PT_AREG2
l32i a0, a1, PT_AREG0
l32i a1, a1, PT_AREG1
l32i a0, a1, PT_AREG0
l32i a1, a1, PT_AREG1
/* Save a2, a3, and depc, restore excsave_1 and set SP. */
/* Save a2, a3, and depc, restore excsave_1 and set SP. */
- xsr a3, EXCSAVE_1
- rsr a0, DEPC
+ xsr a3, excsave1
+ rsr a0, depc
s32i a1, a2, PT_AREG1
s32i a0, a2, PT_AREG2
s32i a3, a2, PT_AREG3
s32i a1, a2, PT_AREG1
s32i a0, a2, PT_AREG2
s32i a3, a2, PT_AREG3
/* Save SAR and turn off single stepping */
movi a2, 0
/* Save SAR and turn off single stepping */
movi a2, 0
- rsr a3, SAR
- xsr a2, ICOUNTLEVEL
+ rsr a3, sar
+ xsr a2, icountlevel
s32i a3, a1, PT_SAR
s32i a2, a1, PT_ICOUNTLEVEL
/* Rotate ws so that the current windowbase is at bit0. */
/* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */
s32i a3, a1, PT_SAR
s32i a2, a1, PT_ICOUNTLEVEL
/* Rotate ws so that the current windowbase is at bit0. */
/* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */
- rsr a2, WINDOWBASE
- rsr a3, WINDOWSTART
+ rsr a2, windowbase
+ rsr a3, windowstart
ssr a2
s32i a2, a1, PT_WINDOWBASE
s32i a3, a1, PT_WINDOWSTART
ssr a2
s32i a2, a1, PT_WINDOWBASE
s32i a3, a1, PT_WINDOWSTART
/* WINDOWBASE still in SAR! */
/* WINDOWBASE still in SAR! */
- rsr a2, SAR # original WINDOWBASE
+ rsr a2, sar # original WINDOWBASE
movi a3, 1
ssl a2
sll a3, a3
movi a3, 1
ssl a2
sll a3, a3
- wsr a3, WINDOWSTART # set corresponding WINDOWSTART bit
- wsr a2, WINDOWBASE # and WINDOWSTART
+ wsr a3, windowstart # set corresponding WINDOWSTART bit
+ wsr a2, windowbase # and WINDOWSTART
rsync
/* We are back to the original stack pointer (a1) */
rsync
/* We are back to the original stack pointer (a1) */
/* Save a0, a2, a3, DEPC and set SP. */
/* Save a0, a2, a3, DEPC and set SP. */
- xsr a3, EXCSAVE_1 # restore a3, excsave_1
- rsr a0, DEPC # get a2
+ xsr a3, excsave1 # restore a3, excsave_1
+ rsr a0, depc # get a2
s32i a1, a2, PT_AREG1
s32i a0, a2, PT_AREG2
s32i a3, a2, PT_AREG3
s32i a1, a2, PT_AREG1
s32i a0, a2, PT_AREG2
s32i a3, a2, PT_AREG3
/* Save SAR and turn off single stepping */
movi a2, 0
/* Save SAR and turn off single stepping */
movi a2, 0
- rsr a3, SAR
- xsr a2, ICOUNTLEVEL
+ rsr a3, sar
+ xsr a2, icountlevel
s32i a3, a1, PT_SAR
s32i a2, a1, PT_ICOUNTLEVEL
/* Rotate ws so that the current windowbase is at bit0. */
/* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */
s32i a3, a1, PT_SAR
s32i a2, a1, PT_ICOUNTLEVEL
/* Rotate ws so that the current windowbase is at bit0. */
/* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */
- rsr a2, WINDOWBASE # don't need to save these, we only
- rsr a3, WINDOWSTART # need shifted windowstart: windowmask
+ rsr a2, windowbase # don't need to save these, we only
+ rsr a3, windowstart # need shifted windowstart: windowmask
ssr a2
slli a2, a3, 32-WSBITS
src a2, a3, a2
ssr a2
slli a2, a3, 32-WSBITS
src a2, a3, a2
/* Save some registers, disable loops and clear the syscall flag. */
/* Save some registers, disable loops and clear the syscall flag. */
- rsr a2, DEBUGCAUSE
- rsr a3, EPC_1
+ rsr a2, debugcause
+ rsr a3, epc1
s32i a2, a1, PT_DEBUGCAUSE
s32i a3, a1, PT_PC
movi a2, -1
s32i a2, a1, PT_DEBUGCAUSE
s32i a3, a1, PT_PC
movi a2, -1
s32i a2, a1, PT_SYSCALL
movi a2, 0
s32i a3, a1, PT_EXCVADDR
s32i a2, a1, PT_SYSCALL
movi a2, 0
s32i a3, a1, PT_EXCVADDR
s32i a2, a1, PT_LCOUNT
/* It is now save to restore the EXC_TABLE_FIXUP variable. */
s32i a2, a1, PT_LCOUNT
/* It is now save to restore the EXC_TABLE_FIXUP variable. */
s32i a0, a1, PT_EXCCAUSE
s32i a3, a2, EXC_TABLE_FIXUP
s32i a0, a1, PT_EXCCAUSE
s32i a3, a2, EXC_TABLE_FIXUP
* (interrupts disabled) and if this exception is not an interrupt.
*/
* (interrupts disabled) and if this exception is not an interrupt.
*/
addi a0, a0, -4
movi a2, 1
extui a3, a3, 0, 1 # a3 = PS.INTLEVEL[0]
moveqz a3, a2, a0 # a3 = 1 iff interrupt exception
movi a2, 1 << PS_WOE_BIT
or a3, a3, a2
addi a0, a0, -4
movi a2, 1
extui a3, a3, 0, 1 # a3 = PS.INTLEVEL[0]
moveqz a3, a2, a0 # a3 = 1 iff interrupt exception
movi a2, 1 << PS_WOE_BIT
or a3, a3, a2
- rsr a0, EXCCAUSE
- xsr a3, PS
+ rsr a0, exccause
+ xsr a3, ps
s32i a3, a1, PT_PS # save ps
s32i a3, a1, PT_PS # save ps
- rsr a2, LBEG
- rsr a3, LEND
+ rsr a2, lbeg
+ rsr a3, lend
s32i a2, a1, PT_LBEG
s32i a3, a1, PT_LEND
s32i a2, a1, PT_LBEG
s32i a3, a1, PT_LEND
load_xtregs_opt a1 a2 a4 a5 a6 a7 PT_XTREGS_OPT
load_xtregs_opt a1 a2 a4 a5 a6 a7 PT_XTREGS_OPT
- wsr a3, PS /* disable interrupts */
+ wsr a3, ps /* disable interrupts */
_bbci.l a3, PS_UM_BIT, kernel_exception_exit
_bbci.l a3, PS_UM_BIT, kernel_exception_exit
l32i a2, a1, PT_WINDOWBASE
l32i a3, a1, PT_WINDOWSTART
l32i a2, a1, PT_WINDOWBASE
l32i a3, a1, PT_WINDOWSTART
- wsr a1, DEPC # use DEPC as temp storage
- wsr a3, WINDOWSTART # restore WINDOWSTART
+ wsr a1, depc # use DEPC as temp storage
+ wsr a3, windowstart # restore WINDOWSTART
ssr a2 # preserve user's WB in the SAR
ssr a2 # preserve user's WB in the SAR
- wsr a2, WINDOWBASE # switch to user's saved WB
+ wsr a2, windowbase # switch to user's saved WB
- rsr a1, DEPC # restore stack pointer
+ rsr a1, depc # restore stack pointer
l32i a2, a1, PT_WMASK # register frames saved (in bits 4...9)
rotw -1 # we restore a4..a7
_bltui a6, 16, 1f # only have to restore current window?
l32i a2, a1, PT_WMASK # register frames saved (in bits 4...9)
rotw -1 # we restore a4..a7
_bltui a6, 16, 1f # only have to restore current window?
/* Clear unrestored registers (don't leak anything to user-land */
/* Clear unrestored registers (don't leak anything to user-land */
-1: rsr a0, WINDOWBASE
- rsr a3, SAR
+1: rsr a0, windowbase
+ rsr a3, sar
sub a3, a0, a3
beqz a3, 2f
extui a3, a3, 0, WBBITS
sub a3, a0, a3
beqz a3, 2f
extui a3, a3, 0, WBBITS
/* Test WINDOWSTART now. If spilled, do the movsp */
/* Test WINDOWSTART now. If spilled, do the movsp */
addi a0, a3, -1
and a3, a3, a0
_bnez a3, common_exception_exit
addi a0, a3, -1
and a3, a3, a0
_bnez a3, common_exception_exit
1: l32i a2, a1, PT_PC
l32i a3, a1, PT_SAR
1: l32i a2, a1, PT_PC
l32i a3, a1, PT_SAR
- wsr a2, EPC_1
- wsr a3, SAR
+ wsr a2, epc1
+ wsr a3, sar
/* Restore LBEG, LEND, LCOUNT */
l32i a2, a1, PT_LBEG
l32i a3, a1, PT_LEND
/* Restore LBEG, LEND, LCOUNT */
l32i a2, a1, PT_LBEG
l32i a3, a1, PT_LEND
- wsr a3, LEND
- wsr a2, LCOUNT
+ wsr a3, lend
+ wsr a2, lcount
/* We control single stepping through the ICOUNTLEVEL register. */
l32i a2, a1, PT_ICOUNTLEVEL
movi a3, -2
/* We control single stepping through the ICOUNTLEVEL register. */
l32i a2, a1, PT_ICOUNTLEVEL
movi a3, -2
- wsr a2, ICOUNTLEVEL
- wsr a3, ICOUNT
+ wsr a2, icountlevel
+ wsr a3, icount
/* Check if it was double exception. */
/* Check if it was double exception. */
l32i a1, a1, PT_AREG1
rfe
l32i a1, a1, PT_AREG1
rfe
l32i a0, a1, PT_AREG0
l32i a1, a1, PT_AREG1
rfde
l32i a0, a1, PT_AREG0
l32i a1, a1, PT_AREG1
rfde
- rsr a0, EPS + XCHAL_DEBUGLEVEL
+ rsr a0, SREG_EPS + XCHAL_DEBUGLEVEL
bbsi.l a0, PS_EXCM_BIT, 1f # exception mode
bbsi.l a0, PS_EXCM_BIT, 1f # exception mode
- /* Set EPC_1 and EXCCAUSE */
+ /* Set EPC1 and EXCCAUSE */
- wsr a2, DEPC # save a2 temporarily
- rsr a2, EPC + XCHAL_DEBUGLEVEL
- wsr a2, EPC_1
+ wsr a2, depc # save a2 temporarily
+ rsr a2, SREG_EPC + XCHAL_DEBUGLEVEL
+ wsr a2, epc1
movi a2, EXCCAUSE_MAPPED_DEBUG
movi a2, EXCCAUSE_MAPPED_DEBUG
/* Restore PS to the value before the debug exc but with PS.EXCM set.*/
movi a2, 1 << PS_EXCM_BIT
or a2, a0, a2
movi a0, debug_exception # restore a3, debug jump vector
/* Restore PS to the value before the debug exc but with PS.EXCM set.*/
movi a2, 1 << PS_EXCM_BIT
or a2, a0, a2
movi a0, debug_exception # restore a3, debug jump vector
- wsr a2, PS
- xsr a0, EXCSAVE + XCHAL_DEBUGLEVEL
+ wsr a2, ps
+ xsr a0, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
/* Switch to kernel/user stack, restore jump vector, and save a0 */
/* Switch to kernel/user stack, restore jump vector, and save a0 */
movi a0, 0
s32i a1, a2, PT_AREG1
s32i a0, a2, PT_DEPC # mark it as a regular exception
movi a0, 0
s32i a1, a2, PT_AREG1
s32i a0, a2, PT_DEPC # mark it as a regular exception
s32i a3, a2, PT_AREG3
s32i a0, a2, PT_AREG2
mov a1, a2
j _kernel_exception
s32i a3, a2, PT_AREG3
s32i a0, a2, PT_AREG2
mov a1, a2
j _kernel_exception
l32i a2, a2, EXC_TABLE_KSTK # load kernel stack pointer
s32i a0, a2, PT_AREG0
movi a0, 0
s32i a1, a2, PT_AREG1
s32i a0, a2, PT_DEPC
l32i a2, a2, EXC_TABLE_KSTK # load kernel stack pointer
s32i a0, a2, PT_AREG0
movi a0, 0
s32i a1, a2, PT_AREG1
s32i a0, a2, PT_DEPC
s32i a3, a2, PT_AREG3
s32i a0, a2, PT_AREG2
mov a1, a2
s32i a3, a2, PT_AREG3
s32i a0, a2, PT_AREG2
mov a1, a2
- wsr a0, WINDOWSTART
- wsr a1, WINDOWBASE
+ wsr a0, windowstart
+ wsr a1, windowbase
rsync
movi a1, (1 << PS_WOE_BIT) | 1
rsync
movi a1, (1 << PS_WOE_BIT) | 1
l32i a0, a2, PT_DEPC
_bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, .Lunhandled_double
l32i a0, a2, PT_DEPC
_bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, .Lunhandled_double
s32i a4, a2, PT_AREG4 # save a4 and
s32i a0, a2, PT_AREG2 # a2 to stack
s32i a4, a2, PT_AREG4 # save a4 and
s32i a0, a2, PT_AREG2 # a2 to stack
/* Restore a3, excsave_1 */
/* Restore a3, excsave_1 */
- xsr a3, EXCSAVE_1 # make sure excsave_1 is valid for dbl.
- rsr a4, EPC_1 # get exception address
+ xsr a3, excsave1 # make sure excsave_1 is valid for dbl.
+ rsr a4, epc1 # get exception address
s32i a3, a2, PT_AREG3 # save a3 to stack
#ifdef ALLOCA_EXCEPTION_IN_IRAM
s32i a3, a2, PT_AREG3 # save a3 to stack
#ifdef ALLOCA_EXCEPTION_IN_IRAM
jx a3
.Lunhandled_double:
jx a3
.Lunhandled_double:
movi a0, unrecoverable_exception
callx0 a0
movi a0, unrecoverable_exception
callx0 a0
#endif
addi a4, a4, 3 # step over movsp
_EXTUI_MOVSP_DST(a0) # extract destination register
#endif
addi a4, a4, 3 # step over movsp
_EXTUI_MOVSP_DST(a0) # extract destination register
- wsr a4, EPC_1 # save new epc_1
+ wsr a4, epc1 # save new epc_1
_bnei a0, 1, 1f # no 'movsp a1, ax': jump
_bnei a0, 1, 1f # no 'movsp a1, ax': jump
l32i a0, a2, PT_DEPC
bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, fast_syscall_unrecoverable
l32i a0, a2, PT_DEPC
bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, fast_syscall_unrecoverable
- rsr a0, DEPC # get syscall-nr
+ rsr a0, depc # get syscall-nr
_beqz a0, fast_syscall_spill_registers
_beqi a0, __NR_xtensa, fast_syscall_xtensa
_beqz a0, fast_syscall_spill_registers
_beqi a0, __NR_xtensa, fast_syscall_xtensa
l32i a0, a2, PT_DEPC
bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, fast_syscall_unrecoverable
l32i a0, a2, PT_DEPC
bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, fast_syscall_unrecoverable
- rsr a0, DEPC # get syscall-nr
+ rsr a0, depc # get syscall-nr
_beqz a0, fast_syscall_spill_registers
_beqi a0, __NR_xtensa, fast_syscall_xtensa
_beqz a0, fast_syscall_spill_registers
_beqi a0, __NR_xtensa, fast_syscall_xtensa
/* Restore all states. */
l32i a0, a2, PT_AREG0 # restore a0
/* Restore all states. */
l32i a0, a2, PT_AREG0 # restore a0
- xsr a2, DEPC # restore a2, depc
- rsr a3, EXCSAVE_1
+ xsr a2, depc # restore a2, depc
+ rsr a3, excsave1
movi a0, unrecoverable_exception
callx0 a0
movi a0, unrecoverable_exception
callx0 a0
ENTRY(fast_syscall_xtensa)
ENTRY(fast_syscall_xtensa)
- xsr a3, EXCSAVE_1 # restore a3, excsave1
+ xsr a3, excsave1 # restore a3, excsave1
s32i a7, a2, PT_AREG7 # we need an additional register
movi a7, 4 # sizeof(unsigned int)
s32i a7, a2, PT_AREG7 # we need an additional register
movi a7, 4 # sizeof(unsigned int)
movi a0, fast_syscall_spill_registers_fixup
s32i a0, a3, EXC_TABLE_FIXUP
movi a0, fast_syscall_spill_registers_fixup
s32i a0, a3, EXC_TABLE_FIXUP
s32i a0, a3, EXC_TABLE_PARAM
/* Save a3 and SAR on stack. */
s32i a0, a3, EXC_TABLE_PARAM
/* Save a3 and SAR on stack. */
- rsr a0, SAR
- xsr a3, EXCSAVE_1 # restore a3 and excsave_1
+ rsr a0, sar
+ xsr a3, excsave1 # restore a3 and excsave_1
s32i a3, a2, PT_AREG3
s32i a4, a2, PT_AREG4
s32i a0, a2, PT_AREG5 # store SAR to PT_AREG5
s32i a3, a2, PT_AREG3
s32i a4, a2, PT_AREG4
s32i a0, a2, PT_AREG5 # store SAR to PT_AREG5
l32i a3, a2, PT_AREG5
l32i a4, a2, PT_AREG4
l32i a0, a2, PT_AREG0
l32i a3, a2, PT_AREG5
l32i a4, a2, PT_AREG4
l32i a0, a2, PT_AREG0
l32i a3, a2, PT_AREG3
/* Restore clobbered registers. */
l32i a3, a2, PT_AREG3
/* Restore clobbered registers. */
fast_syscall_spill_registers_fixup:
fast_syscall_spill_registers_fixup:
- rsr a2, WINDOWBASE # get current windowbase (a2 is saved)
- xsr a0, DEPC # restore depc and a0
+ rsr a2, windowbase # get current windowbase (a2 is saved)
+ xsr a0, depc # restore depc and a0
ssl a2 # set shift (32 - WB)
/* We need to make sure the current registers (a0-a3) are preserved.
ssl a2 # set shift (32 - WB)
/* We need to make sure the current registers (a0-a3) are preserved.
* in WS, so that the exception handlers save them to the task stack.
*/
* in WS, so that the exception handlers save them to the task stack.
*/
- rsr a3, EXCSAVE_1 # get spill-mask
+ rsr a3, excsave1 # get spill-mask
slli a2, a3, 1 # shift left by one
slli a3, a2, 32-WSBITS
src a2, a2, a3 # a1 = xxwww1yyxxxwww1yy......
slli a2, a3, 1 # shift left by one
slli a3, a2, 32-WSBITS
src a2, a2, a3 # a1 = xxwww1yyxxxwww1yy......
- wsr a2, WINDOWSTART # set corrected windowstart
+ wsr a2, windowstart # set corrected windowstart
movi a3, exc_table
l32i a2, a3, EXC_TABLE_DOUBLE_SAVE # restore a2
movi a3, exc_table
l32i a2, a3, EXC_TABLE_DOUBLE_SAVE # restore a2
rsync
/* We are now in the original frame when we entered _spill_registers:
rsync
/* We are now in the original frame when we entered _spill_registers:
/* Jump to the exception handler. */
movi a3, exc_table
/* Jump to the exception handler. */
movi a3, exc_table
addx4 a0, a0, a3 # find entry in table
l32i a0, a0, EXC_TABLE_FAST_USER # load handler
jx a0
addx4 a0, a0, a3 # find entry in table
l32i a0, a0, EXC_TABLE_FAST_USER # load handler
jx a0
/* When we return here, all registers have been restored (a2: DEPC) */
/* When we return here, all registers have been restored (a2: DEPC) */
- wsr a2, DEPC # exception address
+ wsr a2, depc # exception address
/* Restore fixup handler. */
/* Restore fixup handler. */
movi a2, fast_syscall_spill_registers_fixup
s32i a2, a3, EXC_TABLE_FIXUP
movi a2, fast_syscall_spill_registers_fixup
s32i a2, a3, EXC_TABLE_FIXUP
s32i a2, a3, EXC_TABLE_PARAM
l32i a2, a3, EXC_TABLE_KSTK
/* Load WB at the time the exception occurred. */
s32i a2, a3, EXC_TABLE_PARAM
l32i a2, a3, EXC_TABLE_KSTK
/* Load WB at the time the exception occurred. */
- rsr a3, SAR # WB is still in SAR
+ rsr a3, sar # WB is still in SAR
rsync
/* Restore a3 and return. */
movi a3, exc_table
rsync
/* Restore a3 and return. */
movi a3, exc_table
* Rotate ws right so that a4 = yyxxxwww1.
*/
* Rotate ws right so that a4 = yyxxxwww1.
*/
- rsr a4, WINDOWBASE
- rsr a3, WINDOWSTART # a3 = xxxwww1yy
+ rsr a4, windowbase
+ rsr a3, windowstart # a3 = xxxwww1yy
ssr a4 # holds WB
slli a4, a3, WSBITS
or a3, a3, a4 # a3 = xxxwww1yyxxxwww1yy
ssr a4 # holds WB
slli a4, a3, WSBITS
or a3, a3, a4 # a3 = xxxwww1yyxxxwww1yy
/* Skip empty frames - get 'oldest' WINDOWSTART-bit. */
/* Skip empty frames - get 'oldest' WINDOWSTART-bit. */
- wsr a3, WINDOWSTART # save shifted windowstart
+ wsr a3, windowstart # save shifted windowstart
neg a4, a3
and a3, a4, a3 # first bit set from right: 000010000
neg a4, a3
and a3, a4, a3 # first bit set from right: 000010000
sub a4, a3, a4 # WSBITS-a4:number of 0-bits from right
ssr a4 # save in SAR for later.
sub a4, a3, a4 # WSBITS-a4:number of 0-bits from right
ssr a4 # save in SAR for later.
srl a3, a3 # shift windowstart
/* WB is now just one frame below the oldest frame in the register
srl a3, a3 # shift windowstart
/* WB is now just one frame below the oldest frame in the register
.Lexit: /* Done. Do the final rotation, set WS, and return. */
rotw 1
.Lexit: /* Done. Do the final rotation, set WS, and return. */
rotw 1
ssl a3
movi a3, 1
sll a3, a3
ssl a3
movi a3, 1
sll a3, a3
ret
.Lc4: s32e a4, a9, -16
ret
.Lc4: s32e a4, a9, -16
* however, this condition is unrecoverable in kernel space.
*/
* however, this condition is unrecoverable in kernel space.
*/
_bbci.l a0, PS_UM_BIT, 1f
/* User space: Setup a dummy frame and kill application.
_bbci.l a0, PS_UM_BIT, 1f
/* User space: Setup a dummy frame and kill application.
- wsr a0, WINDOWSTART
- wsr a1, WINDOWBASE
+ wsr a0, windowstart
+ wsr a1, windowbase
rsync
movi a0, 0
movi a3, exc_table
l32i a1, a3, EXC_TABLE_KSTK
rsync
movi a0, 0
movi a3, exc_table
l32i a1, a3, EXC_TABLE_KSTK
movi a4, (1 << PS_WOE_BIT) | 1
movi a4, (1 << PS_WOE_BIT) | 1
1: /* Kernel space: PANIC! */
1: /* Kernel space: PANIC! */
movi a0, unrecoverable_exception
callx0 a0 # should not return
1: j 1b
movi a0, unrecoverable_exception
callx0 a0 # should not return
1: j 1b
/* We deliberately destroy a3 that holds the exception table. */
/* We deliberately destroy a3 that holds the exception table. */
-8: rsr a3, EXCVADDR # fault address
+8: rsr a3, excvaddr # fault address
_PGD_OFFSET(a0, a3, a1)
l32i a0, a0, 0 # read pmdval
beqz a0, 2f
_PGD_OFFSET(a0, a3, a1)
l32i a0, a0, 0 # read pmdval
beqz a0, 2f
*/
extui a3, a3, 28, 2 # addr. bit 28 and 29 0,1,2,3
*/
extui a3, a3, 28, 2 # addr. bit 28 and 29 0,1,2,3
addx2 a3, a3, a3 # -> 0,3,6,9
srli a1, a1, PAGE_SHIFT
extui a3, a3, 2, 2 # -> 0,0,1,2
addx2 a3, a3, a3 # -> 0,3,6,9
srli a1, a1, PAGE_SHIFT
extui a3, a3, 2, 2 # -> 0,0,1,2
l32i a0, a2, PT_AREG0
l32i a1, a2, PT_AREG1
l32i a2, a2, PT_DEPC
l32i a0, a2, PT_AREG0
l32i a1, a2, PT_AREG1
l32i a2, a2, PT_DEPC
bgeui a2, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
/* Restore excsave1 and return. */
bgeui a2, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
/* Restore excsave1 and return. */
rfe
/* Return from double exception. */
rfe
/* Return from double exception. */
/* Make sure the exception originated in the special functions */
movi a0, __tlbtemp_mapping_start
/* Make sure the exception originated in the special functions */
movi a0, __tlbtemp_mapping_start
bltu a3, a0, 2f
movi a0, __tlbtemp_mapping_end
bgeu a3, a0, 2f
bltu a3, a0, 2f
movi a0, __tlbtemp_mapping_end
bgeu a3, a0, 2f
/* Check if excvaddr was in one of the TLBTEMP_BASE areas. */
movi a3, TLBTEMP_BASE_1
/* Check if excvaddr was in one of the TLBTEMP_BASE areas. */
movi a3, TLBTEMP_BASE_1
bltu a0, a3, 2f
addi a1, a0, -(2 << (DCACHE_ALIAS_ORDER + PAGE_SHIFT))
bltu a0, a3, 2f
addi a1, a0, -(2 << (DCACHE_ALIAS_ORDER + PAGE_SHIFT))
/* Check if we have to restore an ITLB mapping. */
movi a1, __tlbtemp_mapping_itlb
/* Check if we have to restore an ITLB mapping. */
movi a1, __tlbtemp_mapping_itlb
sub a3, a3, a1
/* Calculate VPN */
sub a3, a3, a1
/* Calculate VPN */
2: /* Invalid PGD, default exception handling */
movi a3, exc_table
2: /* Invalid PGD, default exception handling */
movi a3, exc_table
- rsr a1, DEPC
- xsr a3, EXCSAVE_1
+ rsr a1, depc
+ xsr a3, excsave1
s32i a1, a2, PT_AREG2
s32i a3, a2, PT_AREG3
mov a1, a2
s32i a1, a2, PT_AREG2
s32i a3, a2, PT_AREG3
mov a1, a2
bbsi.l a2, PS_UM_BIT, 1f
j _kernel_exception
1: j _user_exception
bbsi.l a2, PS_UM_BIT, 1f
j _kernel_exception
1: j _user_exception
l32i a0, a1, TASK_MM # tsk->mm
beqz a0, 9f
l32i a0, a1, TASK_MM # tsk->mm
beqz a0, 9f
-8: rsr a1, EXCVADDR # fault address
+8: rsr a1, excvaddr # fault address
_PGD_OFFSET(a0, a1, a4)
l32i a0, a0, 0
beqz a0, 2f
_PGD_OFFSET(a0, a1, a4)
l32i a0, a0, 0
beqz a0, 2f
movi a1, _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_HW_WRITE
or a4, a4, a1
movi a1, _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_HW_WRITE
or a4, a4, a1
s32i a4, a0, 0
/* We need to flush the cache if we have page coloring. */
s32i a4, a0, 0
/* We need to flush the cache if we have page coloring. */
/* Restore excsave1 and a3. */
/* Restore excsave1 and a3. */
bgeui a2, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
bgeui a2, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
rfe
/* Double exception. Restore FIXUP handler and return. */
rfe
/* Double exception. Restore FIXUP handler and return. */
2: /* If there was a problem, handle fault in C */
2: /* If there was a problem, handle fault in C */
- rsr a4, DEPC # still holds a2
- xsr a3, EXCSAVE_1
+ rsr a4, depc # still holds a2
+ xsr a3, excsave1
s32i a4, a2, PT_AREG2
s32i a3, a2, PT_AREG3
l32i a4, a2, PT_AREG4
mov a1, a2
s32i a4, a2, PT_AREG2
s32i a3, a2, PT_AREG3
l32i a4, a2, PT_AREG4
mov a1, a2
bbsi.l a2, PS_UM_BIT, 1f
j _kernel_exception
1: j _user_exception
bbsi.l a2, PS_UM_BIT, 1f
j _kernel_exception
1: j _user_exception
/* Disable ints while we manipulate the stack pointer. */
movi a14, (1 << PS_EXCM_BIT) | LOCKLEVEL
/* Disable ints while we manipulate the stack pointer. */
movi a14, (1 << PS_EXCM_BIT) | LOCKLEVEL
- xsr a14, PS
- rsr a3, EXCSAVE_1
+ xsr a14, ps
+ rsr a3, excsave1
rsync
s32i a3, a3, EXC_TABLE_FIXUP /* enter critical section */
rsync
s32i a3, a3, EXC_TABLE_FIXUP /* enter critical section */
#if (XTENSA_HAVE_COPROCESSORS || XTENSA_HAVE_IO_PORTS)
l32i a3, a5, THREAD_CPENABLE
#if (XTENSA_HAVE_COPROCESSORS || XTENSA_HAVE_IO_PORTS)
l32i a3, a5, THREAD_CPENABLE
s32i a3, a4, THREAD_CPENABLE
#endif
s32i a3, a4, THREAD_CPENABLE
#endif
* we return from kernel space.
*/
* we return from kernel space.
*/
- rsr a3, EXCSAVE_1 # exc_table
+ rsr a3, excsave1 # exc_table
movi a6, 0
addi a7, a5, PT_REGS_OFFSET
s32i a6, a3, EXC_TABLE_FIXUP
movi a6, 0
addi a7, a5, PT_REGS_OFFSET
s32i a6, a3, EXC_TABLE_FIXUP
load_xtregs_user a5 a6 a8 a9 a10 a11 THREAD_XTREGS_USER
load_xtregs_user a5 a6 a8 a9 a10 a11 THREAD_XTREGS_USER
mov a2, a12 # return 'prev'
rsync
mov a2, a12 # return 'prev'
rsync
/* Disable interrupts and exceptions. */
movi a0, LOCKLEVEL
/* Disable interrupts and exceptions. */
movi a0, LOCKLEVEL
/* Preserve the pointer to the boot parameter list in EXCSAVE_1 */
/* Preserve the pointer to the boot parameter list in EXCSAVE_1 */
/* Start with a fresh windowbase and windowstart. */
movi a1, 1
movi a0, 0
/* Start with a fresh windowbase and windowstart. */
movi a1, 1
movi a0, 0
- wsr a1, WINDOWSTART
- wsr a0, WINDOWBASE
+ wsr a1, windowstart
+ wsr a0, windowbase
rsync
/* Set a0 to 0 for the remaining initialization. */
rsync
/* Set a0 to 0 for the remaining initialization. */
/* Clear debugging registers. */
#if XCHAL_HAVE_DEBUG
/* Clear debugging registers. */
#if XCHAL_HAVE_DEBUG
- wsr a0, IBREAKENABLE
- wsr a0, ICOUNT
+ wsr a0, ibreakenable
+ wsr a0, icount
.set _index, 0
.rept XCHAL_NUM_DBREAK - 1
.set _index, 0
.rept XCHAL_NUM_DBREAK - 1
- wsr a0, DBREAKC + _index
+ wsr a0, SREG_DBREAKC + _index
.set _index, _index + 1
.endr
#endif
/* Clear CCOUNT (not really necessary, but nice) */
.set _index, _index + 1
.endr
#endif
/* Clear CCOUNT (not really necessary, but nice) */
- wsr a0, CCOUNT # not really necessary, but nice
+ wsr a0, ccount # not really necessary, but nice
/* Disable zero-loops. */
#if XCHAL_HAVE_LOOPS
/* Disable zero-loops. */
#if XCHAL_HAVE_LOOPS
#endif
/* Disable all timers. */
.set _index, 0
.rept XCHAL_NUM_TIMERS - 1
#endif
/* Disable all timers. */
.set _index, 0
.rept XCHAL_NUM_TIMERS - 1
- wsr a0, CCOMPARE + _index
+ wsr a0, SREG_CCOMPARE + _index
.set _index, _index + 1
.endr
/* Interrupt initialization. */
movi a2, XCHAL_INTTYPE_MASK_SOFTWARE | XCHAL_INTTYPE_MASK_EXTERN_EDGE
.set _index, _index + 1
.endr
/* Interrupt initialization. */
movi a2, XCHAL_INTTYPE_MASK_SOFTWARE | XCHAL_INTTYPE_MASK_EXTERN_EDGE
- wsr a0, INTENABLE
- wsr a2, INTCLEAR
+ wsr a0, intenable
+ wsr a2, intclear
/* Disable coprocessors. */
#if XCHAL_CP_NUM > 0
/* Disable coprocessors. */
#if XCHAL_CP_NUM > 0
#endif
/* Set PS.INTLEVEL=1, PS.WOE=0, kernel stack, PS.EXCM=0
#endif
/* Set PS.INTLEVEL=1, PS.WOE=0, kernel stack, PS.EXCM=0
rsync
/* Initialize the caches.
rsync
/* Initialize the caches.
addi a1, a1, KERNEL_STACK_SIZE
movi a2, 0x00040001 # WOE=1, INTLEVEL=1, UM=0
addi a1, a1, KERNEL_STACK_SIZE
movi a2, 0x00040001 # WOE=1, INTLEVEL=1, UM=0
- wsr a2, PS # (enable reg-windows; progmode stack)
+ wsr a2, ps # (enable reg-windows; progmode stack)
rsync
/* Set up EXCSAVE[DEBUGLEVEL] to point to the Debug Exception Handler.*/
movi a2, debug_exception
rsync
/* Set up EXCSAVE[DEBUGLEVEL] to point to the Debug Exception Handler.*/
movi a2, debug_exception
- wsr a2, EXCSAVE + XCHAL_DEBUGLEVEL
+ wsr a2, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
/* Set up EXCSAVE[1] to point to the exc_table. */
movi a6, exc_table
/* Set up EXCSAVE[1] to point to the exc_table. */
movi a6, exc_table
/* init_arch kick-starts the linux kernel */
/* init_arch kick-starts the linux kernel */
static void xtensa_irq_mask(struct irq_data *d)
{
cached_irq_mask &= ~(1 << d->irq);
static void xtensa_irq_mask(struct irq_data *d)
{
cached_irq_mask &= ~(1 << d->irq);
- set_sr (cached_irq_mask, INTENABLE);
+ set_sr (cached_irq_mask, intenable);
}
static void xtensa_irq_unmask(struct irq_data *d)
{
cached_irq_mask |= 1 << d->irq;
}
static void xtensa_irq_unmask(struct irq_data *d)
{
cached_irq_mask |= 1 << d->irq;
- set_sr (cached_irq_mask, INTENABLE);
+ set_sr (cached_irq_mask, intenable);
}
static void xtensa_irq_enable(struct irq_data *d)
}
static void xtensa_irq_enable(struct irq_data *d)
static void xtensa_irq_ack(struct irq_data *d)
{
static void xtensa_irq_ack(struct irq_data *d)
{
- set_sr(1 << d->irq, INTCLEAR);
+ set_sr(1 << d->irq, intclear);
}
static int xtensa_irq_retrigger(struct irq_data *d)
}
static int xtensa_irq_retrigger(struct irq_data *d)
void do_interrupt (struct pt_regs *regs)
{
void do_interrupt (struct pt_regs *regs)
{
- unsigned long intread = get_sr (INTREAD);
- unsigned long intenable = get_sr (INTENABLE);
+ unsigned long intread = get_sr (interrupt);
+ unsigned long intenable = get_sr (intenable);
int i, mask;
/* Handle all interrupts (no priorities).
int i, mask;
/* Handle all interrupts (no priorities).
for (i=0, mask = 1; i < XCHAL_NUM_INTERRUPTS; i++, mask <<= 1) {
if (mask & (intread & intenable)) {
for (i=0, mask = 1; i < XCHAL_NUM_INTERRUPTS; i++, mask <<= 1) {
if (mask & (intread & intenable)) {
- set_sr (mask, INTCLEAR);
+ set_sr (mask, intclear);
/* Initialize EXCSAVE_1 to hold the address of the exception table. */
i = (unsigned long)exc_table;
/* Initialize EXCSAVE_1 to hold the address of the exception table. */
i = (unsigned long)exc_table;
- __asm__ __volatile__("wsr %0, "__stringify(EXCSAVE_1)"\n" : : "a" (i));
+ __asm__ __volatile__("wsr %0, excsave1\n" : : "a" (i));
unsigned int a0, ps;
__asm__ __volatile__ (
unsigned int a0, ps;
__asm__ __volatile__ (
- "movi a14," __stringify (PS_EXCM_BIT) " | 1\n\t"
+ "movi a14, " __stringify(PS_EXCM_BIT | 1) "\n\t"
- "rsr a13," __stringify(SAR) "\n\t"
- "xsr a14," __stringify(PS) "\n\t"
+ "rsr a13, sar\n\t"
+ "xsr a14, ps\n\t"
"movi a0, _spill_registers\n\t"
"rsync\n\t"
"callx0 a0\n\t"
"mov a0, a12\n\t"
"movi a0, _spill_registers\n\t"
"rsync\n\t"
"callx0 a0\n\t"
"mov a0, a12\n\t"
- "wsr a13," __stringify(SAR) "\n\t"
- "wsr a14," __stringify(PS) "\n\t"
+ "wsr a13, sar\n\t"
+ "wsr a14, ps\n\t"
:: "a" (&a0), "a" (&ps)
: "a2", "a3", "a4", "a7", "a11", "a12", "a13", "a14", "a15", "memory");
}
:: "a" (&a0), "a" (&ps)
: "a2", "a3", "a4", "a7", "a11", "a12", "a13", "a14", "a15", "memory");
}
ENTRY(_UserExceptionVector)
ENTRY(_UserExceptionVector)
- xsr a3, EXCSAVE_1 # save a3 and get dispatch table
- wsr a2, DEPC # save a2
+ xsr a3, excsave1 # save a3 and get dispatch table
+ wsr a2, depc # save a2
l32i a2, a3, EXC_TABLE_KSTK # load kernel stack to a2
s32i a0, a2, PT_AREG0 # save a0 to ESF
l32i a2, a3, EXC_TABLE_KSTK # load kernel stack to a2
s32i a0, a2, PT_AREG0 # save a0 to ESF
- rsr a0, EXCCAUSE # retrieve exception cause
+ rsr a0, exccause # retrieve exception cause
s32i a0, a2, PT_DEPC # mark it as a regular exception
addx4 a0, a0, a3 # find entry in table
l32i a0, a0, EXC_TABLE_FAST_USER # load handler
s32i a0, a2, PT_DEPC # mark it as a regular exception
addx4 a0, a0, a3 # find entry in table
l32i a0, a0, EXC_TABLE_FAST_USER # load handler
ENTRY(_KernelExceptionVector)
ENTRY(_KernelExceptionVector)
- xsr a3, EXCSAVE_1 # save a3, and get dispatch table
- wsr a2, DEPC # save a2
+ xsr a3, excsave1 # save a3, and get dispatch table
+ wsr a2, depc # save a2
addi a2, a1, -16-PT_SIZE # adjust stack pointer
s32i a0, a2, PT_AREG0 # save a0 to ESF
addi a2, a1, -16-PT_SIZE # adjust stack pointer
s32i a0, a2, PT_AREG0 # save a0 to ESF
- rsr a0, EXCCAUSE # retrieve exception cause
+ rsr a0, exccause # retrieve exception cause
s32i a0, a2, PT_DEPC # mark it as a regular exception
addx4 a0, a0, a3 # find entry in table
l32i a0, a0, EXC_TABLE_FAST_KERNEL # load handler address
s32i a0, a2, PT_DEPC # mark it as a regular exception
addx4 a0, a0, a3 # find entry in table
l32i a0, a0, EXC_TABLE_FAST_KERNEL # load handler address
/* Deliberately destroy excsave (don't assume it's value was valid). */
/* Deliberately destroy excsave (don't assume it's value was valid). */
- wsr a3, EXCSAVE_1 # save a3
+ wsr a3, excsave1 # save a3
/* Check for kernel double exception (usually fatal). */
/* Check for kernel double exception (usually fatal). */
_bbci.l a3, PS_UM_BIT, .Lksp
/* Check if we are currently handling a window exception. */
/* Note: We don't need to indicate that we enter a critical section. */
_bbci.l a3, PS_UM_BIT, .Lksp
/* Check if we are currently handling a window exception. */
/* Note: We don't need to indicate that we enter a critical section. */
- xsr a0, DEPC # get DEPC, save a0
+ xsr a0, depc # get DEPC, save a0
movi a3, XCHAL_WINDOW_VECTORS_VADDR
_bltu a0, a3, .Lfixup
movi a3, XCHAL_WINDOW_VECTORS_VADDR
_bltu a0, a3, .Lfixup
* Note: We can trash the current window frame (a0...a3) and depc!
*/
* Note: We can trash the current window frame (a0...a3) and depc!
*/
- wsr a2, DEPC # save stack pointer temporarily
- rsr a0, PS
+ wsr a2, depc # save stack pointer temporarily
+ rsr a0, ps
extui a0, a0, PS_OWB_SHIFT, 4
extui a0, a0, PS_OWB_SHIFT, 4
rsync
/* We are now in the previous window frame. Save registers again. */
rsync
/* We are now in the previous window frame. Save registers again. */
- xsr a2, DEPC # save a2 and get stack pointer
+ xsr a2, depc # save a2 and get stack pointer
- wsr a3, EXCSAVE_1 # save a3
+ wsr a3, excsave1 # save a3
s32i a0, a2, PT_DEPC # mark it as a regular exception
addx4 a0, a0, a3
l32i a0, a0, EXC_TABLE_FAST_USER
s32i a0, a2, PT_DEPC # mark it as a regular exception
addx4 a0, a0, a3
l32i a0, a0, EXC_TABLE_FAST_USER
/* a0: depc, a1: a1, a2: kstk, a3: a2, depc: a0, excsave: a3 */
/* a0: depc, a1: a1, a2: kstk, a3: a2, depc: a0, excsave: a3 */
s32i a0, a2, PT_DEPC
s32i a3, a2, PT_AREG0
/* a0: avail, a1: a1, a2: kstk, a3: avail, depc: a2, excsave: a3 */
movi a3, exc_table
s32i a0, a2, PT_DEPC
s32i a3, a2, PT_AREG0
/* a0: avail, a1: a1, a2: kstk, a3: avail, depc: a2, excsave: a3 */
movi a3, exc_table
addx4 a0, a0, a3
l32i a0, a0, EXC_TABLE_FAST_USER
jx a0
addx4 a0, a0, a3
l32i a0, a0, EXC_TABLE_FAST_USER
jx a0
.Lksp: /* a0: a0, a1: a1, a2: a2, a3: trashed, depc: depc, excsave: a3 */
.Lksp: /* a0: a0, a1: a1, a2: a2, a3: trashed, depc: depc, excsave: a3 */
beqi a3, EXCCAUSE_ITLB_MISS, 1f
addi a3, a3, -EXCCAUSE_DTLB_MISS
bnez a3, .Lunrecoverable
beqi a3, EXCCAUSE_ITLB_MISS, 1f
addi a3, a3, -EXCCAUSE_DTLB_MISS
bnez a3, .Lunrecoverable
.Lunrecoverable_fixup:
l32i a2, a3, EXC_TABLE_DOUBLE_SAVE
.Lunrecoverable_fixup:
l32i a2, a3, EXC_TABLE_DOUBLE_SAVE
- rsr a3, EXCSAVE_1
- wsr a0, EXCSAVE_1
+ rsr a3, excsave1
+ wsr a0, excsave1
movi a0, unrecoverable_exception
callx0 a0
movi a0, unrecoverable_exception
callx0 a0
.section .DebugInterruptVector.text, "ax"
ENTRY(_DebugInterruptVector)
.section .DebugInterruptVector.text, "ax"
ENTRY(_DebugInterruptVector)
- xsr a0, EXCSAVE + XCHAL_DEBUGLEVEL
+ xsr a0, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
* jump to the reset vector. */
__asm__ __volatile__("movi a2, 15\n\t"
* jump to the reset vector. */
__asm__ __volatile__("movi a2, 15\n\t"
- "wsr a2, " __stringify(ICOUNTLEVEL) "\n\t"
+ "wsr a2, icountlevel\n\t"
- "wsr a2, " __stringify(ICOUNT) "\n\t"
- "wsr a2, " __stringify(IBREAKENABLE) "\n\t"
- "wsr a2, " __stringify(LCOUNT) "\n\t"
+ "wsr a2, icount\n\t"
+ "wsr a2, ibreakenable\n\t"
+ "wsr a2, lcount\n\t"
- "wsr a2, " __stringify(PS) "\n\t"
"isync\n\t"
"jx %0\n\t"
:
"isync\n\t"
"jx %0\n\t"
:
* jump to the reset vector. */
__asm__ __volatile__ ("movi a2, 15\n\t"
* jump to the reset vector. */
__asm__ __volatile__ ("movi a2, 15\n\t"
- "wsr a2, " __stringify(ICOUNTLEVEL) "\n\t"
+ "wsr a2, icountlevel\n\t"
- "wsr a2, " __stringify(ICOUNT) "\n\t"
- "wsr a2, " __stringify(IBREAKENABLE) "\n\t"
- "wsr a2, " __stringify(LCOUNT) "\n\t"
+ "wsr a2, icount\n\t"
+ "wsr a2, ibreakenable\n\t"
+ "wsr a2, lcount\n\t"
- "wsr a2, " __stringify(PS) "\n\t"
"isync\n\t"
"jx %0\n\t"
:
"isync\n\t"
"jx %0\n\t"
: