abort for instructions we're not implementing now.
+Wed Nov 27 09:20:42 1996 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c: Implement remaining 2 byte instructions. Call
+ abort for instructions we're not implementing now.
+
Tue Nov 26 15:43:41 1996 Jeffrey A Law (law@cygnus.com)
* simops.c: Implement lots of random instructions.
Tue Nov 26 15:43:41 1996 Jeffrey A Law (law@cygnus.com)
* simops.c: Implement lots of random instructions.
+ State.regs[REG_D0 + ((insn & 0x30) >> 8)]
+ = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
+ + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4);
+ State.regs[REG_A0 + ((insn & 0x30) >> 8)]
+ = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
+ + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4);
+ store_mem ((State.regs[REG_A0 + (insn & 0x3)]
+ + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4,
+ State.regs[REG_D0 + ((insn & 0x30) >> 8)]);
+ store_mem ((State.regs[REG_A0 + (insn & 0x3)]
+ + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4,
+ State.regs[REG_A0 + ((insn & 0x30) >> 8)]);
+ State.regs[REG_D0 + ((insn & 0x30) >> 8)]
+ = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
+ + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 1);
}
/* movbu (abs16), dn */
}
/* movbu (abs16), dn */
+ store_mem ((State.regs[REG_A0 + (insn & 0x3)]
+ + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 1,
+ State.regs[REG_D0 + ((insn & 0x30) >> 8)]);
}
/* movbu dm, (abs16) */
}
/* movbu dm, (abs16) */
+ State.regs[REG_D0 + ((insn & 0x30) >> 8)]
+ = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
+ + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 2);
}
/* movhu (abs16), dn */
}
/* movhu (abs16), dn */
+ store_mem ((State.regs[REG_A0 + (insn & 0x3)]
+ + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 2,
+ State.regs[REG_D0 + ((insn & 0x30) >> 8)]);
}
/* movhu dm, (abs16) */
}
/* movhu dm, (abs16) */
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
}
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
}
void OP_C800 ()
{
/* The dispatching code will add 2 after we return, so
void OP_C800 ()
{
/* The dispatching code will add 2 after we return, so
State.pc += SEXT8 (insn & 0xff) - 2;
}
State.pc += SEXT8 (insn & 0xff) - 2;
}
void OP_C900 ()
{
/* The dispatching code will add 2 after we return, so
void OP_C900 ()
{
/* The dispatching code will add 2 after we return, so
State.pc += SEXT8 (insn & 0xff) - 2;
}
State.pc += SEXT8 (insn & 0xff) - 2;
}
+ /* The dispatching code will add 2 after we return, so
+ we subtract two here to make things right. */
+ if (!((PSW & PSW_Z)
+ || (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0)))
+ State.pc += SEXT8 (insn & 0xff) - 2;
+ /* The dispatching code will add 2 after we return, so
+ we subtract two here to make things right. */
+ if (!(((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0))
+ State.pc += SEXT8 (insn & 0xff) - 2;
+ /* The dispatching code will add 2 after we return, so
+ we subtract two here to make things right. */
+ if ((PSW & PSW_Z)
+ || (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0))
+ State.pc += SEXT8 (insn & 0xff) - 2;
+ /* The dispatching code will add 2 after we return, so
+ we subtract two here to make things right. */
+ if (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0)
+ State.pc += SEXT8 (insn & 0xff) - 2;
+ /* The dispatching code will add 2 after we return, so
+ we subtract two here to make things right. */
+ if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
+ State.pc += SEXT8 (insn & 0xff) - 2;
+ /* The dispatching code will add 2 after we return, so
+ we subtract two here to make things right. */
+ if (!(PSW & PSW_C))
+ State.pc += SEXT8 (insn & 0xff) - 2;
+ /* The dispatching code will add 2 after we return, so
+ we subtract two here to make things right. */
+ if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
+ State.pc += SEXT8 (insn & 0xff) - 2;
+ /* The dispatching code will add 2 after we return, so
+ we subtract two here to make things right. */
+ if (PSW & PSW_C)
+ State.pc += SEXT8 (insn & 0xff) - 2;
+ /* The dispatching code will add 3 after we return, so
+ we subtract two here to make things right. */
+ if (!(PSW & PSW_V))
+ State.pc += SEXT8 (insn & 0xff) - 3;
+ /* The dispatching code will add 3 after we return, so
+ we subtract two here to make things right. */
+ if (PSW & PSW_V)
+ State.pc += SEXT8 (insn & 0xff) - 3;
+ /* The dispatching code will add 3 after we return, so
+ we subtract two here to make things right. */
+ if (!(PSW & PSW_N))
+ State.pc += SEXT8 (insn & 0xff) - 3;
+ /* The dispatching code will add 3 after we return, so
+ we subtract two here to make things right. */
+ if (PSW & PSW_N)
+ State.pc += SEXT8 (insn & 0xff) - 3;
+ /* The dispatching code will add 2 after we return, so
+ we subtract two here to make things right. */
+ State.pc += SEXT8 (insn & 0xff) - 2;
}
/* leq */
void OP_D8 ()
{
}
/* leq */
void OP_D8 ()
{
}
/* lne */
void OP_D9 ()
{
}
/* lne */
void OP_D9 ()
{
}
/* lgt */
void OP_D1 ()
{
}
/* lgt */
void OP_D1 ()
{
}
/* lge */
void OP_D2 ()
{
}
/* lge */
void OP_D2 ()
{
}
/* lle */
void OP_D3 ()
{
}
/* lle */
void OP_D3 ()
{
}
/* llt */
void OP_D0 ()
{
}
/* llt */
void OP_D0 ()
{
}
/* lhi */
void OP_D5 ()
{
}
/* lhi */
void OP_D5 ()
{
}
/* lcc */
void OP_D6 ()
{
}
/* lcc */
void OP_D6 ()
{
}
/* lls */
void OP_D7 ()
{
}
/* lls */
void OP_D7 ()
{
}
/* lcs */
void OP_D4 ()
{
}
/* lcs */
void OP_D4 ()
{
}
/* lra */
void OP_DA ()
{
}
/* lra */
void OP_DA ()
{
}
/* setlb */
void OP_DB ()
{
}
/* setlb */
void OP_DB ()
{
/* rti */
void OP_F0FD ()
{
/* rti */
void OP_F0FD ()
{
}
/* trap */
void OP_F0FE ()
{
}
/* trap */
void OP_F0FE ()
{
}
/* rtm */
void OP_F0FF ()
{
}
/* rtm */
void OP_F0FF ()
{