+ /* Create any fixups. */
+ for (i = 0; i < fixup_count; ++i)
+ {
+ int op_type, reloc_type;
+ const struct txvu_operand *operand;
+
+ /* Create a fixup for this operand.
+ At this point we do not use a bfd_reloc_code_real_type for
+ operands residing in the insn, but instead just use the
+ operand index. This lets us easily handle fixups for any
+ operand type, although that is admittedly not a very exciting
+ feature. We pick a BFD reloc type in md_apply_fix. */
+
+ op_type = fixups[i].opindex;
+ reloc_type = op_type + (int) BFD_RELOC_UNUSED;
+ operand = &txvu_operands[op_type];
+ fix_new_exp (frag_now, buf - frag_now->fr_literal, 4,
+ &fixups[i].exp,
+ (operand->flags & TXVU_OPERAND_RELATIVE_BRANCH) != 0,
+ (bfd_reloc_code_real_type) reloc_type);
+ }
+
+ /* All done. */
+ return str;
+}
+
+/* Assemble one instruction.
+ CPU indicates what component we're assembling for.
+ The assembled instruction is stored in INSN_BUF.
+
+ The result is a pointer to beyond the end of the scanned insn
+ or NULL if an error occured. This is to handle the VU where two
+ instructions appear on one line. If this is the upper insn, the caller
+ can pass back to result to us parse the lower insn. */
+
+static char *
+assemble_one_insn (cpu, opcode, operand_table, str, insn_buf)
+ enum cputype cpu;
+ const struct txvu_opcode *opcode;
+ const struct txvu_operand *operand_table;
+ char *str;
+ TXVU_INSN *insn_buf;
+{
+ char *start;