- Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+ Copyright (C) 1996, 1997, 1998, 2000 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
#define IMM16_PCREL (IMM16+1)
{16, 0, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
#define IMM16_PCREL (IMM16+1)
{16, 0, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
may promote to a 32bit displacement. */
#define IMM16_MEM (IMM16_PCREL+1)
{16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
may promote to a 32bit displacement. */
#define IMM16_MEM (IMM16_PCREL+1)
{16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
#define DI (MDR+1)
{2, 2, MN10300_OPERAND_DREG},
#define DI (MDR+1)
{2, 2, MN10300_OPERAND_DREG},
#define SD8 (DI+1)
{8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
#define SD8 (DI+1)
{8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
#define SD16 (SD8+1)
{16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
#define SD16 (SD8+1)
{16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
#define RD2 (RD0+1)
{4, -4, MN10300_OPERAND_RREG},
#define RD2 (RD0+1)
{4, -4, MN10300_OPERAND_RREG},
may promote to a 32bit displacement. */
#define IMM8_MEM (RD2+1)
{8, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
may promote to a 32bit displacement. */
#define IMM8_MEM (RD2+1)
{8, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
#define RI (IMM8_MEM+1)
{4, 4, MN10300_OPERAND_RREG},
#define RI (IMM8_MEM+1)
{4, 4, MN10300_OPERAND_RREG},
#define SD24 (RI+1)
{8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
#define SD24 (RI+1)
{8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
#define SIMM24 (IMM24+1)
{8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_SIGNED},
#define SIMM24 (IMM24+1)
{8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_SIGNED},
may promote to a 32bit displacement. */
#define IMM24_MEM (SIMM24+1)
{8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
may promote to a 32bit displacement. */
#define IMM24_MEM (SIMM24+1)
{8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
-/* 32bit immediate, high 24 bits in the main instruction
- word, 8 in the extension word.
+/* 32bit immediate, high 8 bits in the main instruction
+ word, 24 in the extension word.
The "bits" field indicates how many bits are in the
main instruction word for MN10300_OPERAND_SPLIT! */
The "bits" field indicates how many bits are in the
main instruction word for MN10300_OPERAND_SPLIT! */
{ "inc", 0x40, 0xf3, 0, FMT_S0, 0, {DN1}},
{ "inc", 0x41, 0xf3, 0, FMT_S0, 0, {AN1}},
{ "inc", 0xf9b800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
{ "inc", 0x40, 0xf3, 0, FMT_S0, 0, {DN1}},
{ "inc", 0x41, 0xf3, 0, FMT_S0, 0, {AN1}},
{ "inc", 0xf9b800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
{ "inc4", 0x50, 0xfc, 0, FMT_S0, 0, {AN0}},
{ "inc4", 0xf9c800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
{ "inc4", 0x50, 0xfc, 0, FMT_S0, 0, {AN0}},
{ "inc4", 0xf9c800, 0xffff00, 0, FMT_D6, AM33, {RN02}},