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clk: rockchip: fix rk3288 clk_usbphy480m_gate bit location in register
author
Kever Yang
<kever.yang@rock-chips.com>
Thu, 13 Nov 2014 07:19:21 +0000
(15:19 +0800)
committer
Heiko Stuebner
<heiko@sntech.de>
Sat, 15 Nov 2014 23:02:24 +0000
(
00:02
+0100)
According to rk3288 trm, the clk_usbphy480m_gate is located at
bit 14 of CRU_CLKGATE5_CON register.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-rk3288.c
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diff --git
a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk/rockchip/clk-rk3288.c
index b4a74c2d79e0f653316f29f81a84097ef12951fd..f27cdae61fd54147f72daabdf486b7732b17363c 100644
(file)
--- a/
drivers/clk/rockchip/clk-rk3288.c
+++ b/
drivers/clk/rockchip/clk-rk3288.c
@@
-588,7
+588,7
@@
static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
COMPOSITE_NODIV(0, "usbphy480m_src", mux_usbphy480m_p, 0,
RK3288_CLKSEL_CON(13), 11, 2, MFLAGS,
- RK3288_CLKGATE_CON(5), 1
5
, GFLAGS),
+ RK3288_CLKGATE_CON(5), 1
4
, GFLAGS),
COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
RK3288_CLKGATE_CON(3), 6, GFLAGS),
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