clk: sunxi: Introduce mbus compatible
authorMaxime Ripard <maxime.ripard@free-electrons.com>
Thu, 10 Jul 2014 21:53:40 +0000 (23:53 +0200)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Sat, 27 Sep 2014 06:58:02 +0000 (08:58 +0200)
Even though the mbus clock is a regular module clock, given its nature, it
needs to be enabled all the time.

Introduce a new compatible, to differentiate it from the other module clocks.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Documentation/devicetree/bindings/clock/sunxi.txt
drivers/clk/sunxi/clk-sunxi.c

index d3a5c3c6d6774602667a69e9e93e7511039ef3f4..b938a990602ae820e30371e5c71bc02d1b96a4b0 100644 (file)
@@ -46,6 +46,7 @@ Required properties:
        "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
        "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
        "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
+       "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
        "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
        "allwinner,sun7i-a20-out-clk" - for the external output clocks
        "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
index 393df321010bb03713f7bfa5d1b94f29da12d003..17e1e3bec954d9704d566cf6b22ebbe32717a38d 100644 (file)
@@ -1119,6 +1119,7 @@ static const struct of_device_id clk_factors_match[] __initconst = {
        {.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
        {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
        {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
+       {.compatible = "allwinner,sun5i-a13-mbus-clk", .data = &sun4i_mod0_data,},
        {.compatible = "allwinner,sun4i-a10-mod0-clk", .data = &sun4i_mod0_data,},
        {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
        {}
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